10b57cec5SDimitry Andric /*===---- prfchwintrin.h - PREFETCHW intrinsic -----------------------------=== 20b57cec5SDimitry Andric * 30b57cec5SDimitry Andric * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric * See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric * 70b57cec5SDimitry Andric *===-----------------------------------------------------------------------=== 80b57cec5SDimitry Andric */ 90b57cec5SDimitry Andric 100b57cec5SDimitry Andric #if !defined(__X86INTRIN_H) && !defined(_MM3DNOW_H_INCLUDED) 11*0fca6ea1SDimitry Andric #error "Never use <prfchwintrin.h> directly; include <x86intrin.h> instead." 120b57cec5SDimitry Andric #endif 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric #ifndef __PRFCHWINTRIN_H 150b57cec5SDimitry Andric #define __PRFCHWINTRIN_H 160b57cec5SDimitry Andric 170b57cec5SDimitry Andric /// Loads a memory sequence containing the specified memory address into 18*0fca6ea1SDimitry Andric /// all data cache levels. 19*0fca6ea1SDimitry Andric /// 20*0fca6ea1SDimitry Andric /// The cache-coherency state is set to exclusive. Data can be read from 21*0fca6ea1SDimitry Andric /// and written to the cache line without additional delay. 220b57cec5SDimitry Andric /// 230b57cec5SDimitry Andric /// \headerfile <x86intrin.h> 240b57cec5SDimitry Andric /// 250b57cec5SDimitry Andric /// This intrinsic corresponds to the \c PREFETCHT0 instruction. 260b57cec5SDimitry Andric /// 270b57cec5SDimitry Andric /// \param __P 280b57cec5SDimitry Andric /// A pointer specifying the memory address to be prefetched. 290b57cec5SDimitry Andric static __inline__ void __attribute__((__always_inline__, __nodebug__)) 300b57cec5SDimitry Andric _m_prefetch(void *__P) 310b57cec5SDimitry Andric { 320b57cec5SDimitry Andric __builtin_prefetch (__P, 0, 3 /* _MM_HINT_T0 */); 330b57cec5SDimitry Andric } 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric /// Loads a memory sequence containing the specified memory address into 36*0fca6ea1SDimitry Andric /// the L1 data cache and sets the cache-coherency state to modified. 37*0fca6ea1SDimitry Andric /// 38*0fca6ea1SDimitry Andric /// This provides a hint to the processor that the cache line will be 39*0fca6ea1SDimitry Andric /// modified. It is intended for use when the cache line will be written to 40*0fca6ea1SDimitry Andric /// shortly after the prefetch is performed. 410b57cec5SDimitry Andric /// 420b57cec5SDimitry Andric /// Note that the effect of this intrinsic is dependent on the processor 430b57cec5SDimitry Andric /// implementation. 440b57cec5SDimitry Andric /// 450b57cec5SDimitry Andric /// \headerfile <x86intrin.h> 460b57cec5SDimitry Andric /// 470b57cec5SDimitry Andric /// This intrinsic corresponds to the \c PREFETCHW instruction. 480b57cec5SDimitry Andric /// 490b57cec5SDimitry Andric /// \param __P 500b57cec5SDimitry Andric /// A pointer specifying the memory address to be prefetched. 510b57cec5SDimitry Andric static __inline__ void __attribute__((__always_inline__, __nodebug__)) 52349cc55cSDimitry Andric _m_prefetchw(volatile const void *__P) 530b57cec5SDimitry Andric { 54349cc55cSDimitry Andric #pragma clang diagnostic push 55349cc55cSDimitry Andric #pragma clang diagnostic ignored "-Wcast-qual" 56349cc55cSDimitry Andric __builtin_prefetch ((const void*)__P, 1, 3 /* _MM_HINT_T0 */); 57349cc55cSDimitry Andric #pragma clang diagnostic pop 580b57cec5SDimitry Andric } 590b57cec5SDimitry Andric 600b57cec5SDimitry Andric #endif /* __PRFCHWINTRIN_H */ 61