1fe6060f1SDimitry Andric //===----------------------------------------------------------------------===// 2fe6060f1SDimitry Andric // 3fe6060f1SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4fe6060f1SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5fe6060f1SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6fe6060f1SDimitry Andric // 7fe6060f1SDimitry Andric //===----------------------------------------------------------------------===// 8fe6060f1SDimitry Andric // Automatically generated file, do not edit! 9fe6060f1SDimitry Andric //===----------------------------------------------------------------------===// 10fe6060f1SDimitry Andric 11fe6060f1SDimitry Andric 12fe6060f1SDimitry Andric #ifndef _HVX_HEXAGON_PROTOS_H_ 13fe6060f1SDimitry Andric #define _HVX_HEXAGON_PROTOS_H_ 1 14fe6060f1SDimitry Andric 15fe6060f1SDimitry Andric #ifdef __HVX__ 16fe6060f1SDimitry Andric #if __HVX_LENGTH__ == 128 17fe6060f1SDimitry Andric #define __BUILTIN_VECTOR_WRAP(a) a ## _128B 18fe6060f1SDimitry Andric #else 19fe6060f1SDimitry Andric #define __BUILTIN_VECTOR_WRAP(a) a 20fe6060f1SDimitry Andric #endif 21fe6060f1SDimitry Andric 22fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 23fe6060f1SDimitry Andric /* ========================================================================== 24fe6060f1SDimitry Andric Assembly Syntax: Rd32=vextract(Vu32,Rs32) 25fe6060f1SDimitry Andric C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs) 26fe6060f1SDimitry Andric Instruction Type: LD 27fe6060f1SDimitry Andric Execution Slots: SLOT0 28fe6060f1SDimitry Andric ========================================================================== */ 29fe6060f1SDimitry Andric 30*0eae32dcSDimitry Andric #define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs) 31fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 32fe6060f1SDimitry Andric 33fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 34fe6060f1SDimitry Andric /* ========================================================================== 35fe6060f1SDimitry Andric Assembly Syntax: Vd32=hi(Vss32) 36fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss) 37fe6060f1SDimitry Andric Instruction Type: CVI_VA 38fe6060f1SDimitry Andric Execution Slots: SLOT0123 39fe6060f1SDimitry Andric ========================================================================== */ 40fe6060f1SDimitry Andric 41*0eae32dcSDimitry Andric #define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss) 42fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 43fe6060f1SDimitry Andric 44fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 45fe6060f1SDimitry Andric /* ========================================================================== 46fe6060f1SDimitry Andric Assembly Syntax: Vd32=lo(Vss32) 47fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss) 48fe6060f1SDimitry Andric Instruction Type: CVI_VA 49fe6060f1SDimitry Andric Execution Slots: SLOT0123 50fe6060f1SDimitry Andric ========================================================================== */ 51fe6060f1SDimitry Andric 52*0eae32dcSDimitry Andric #define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss) 53fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 54fe6060f1SDimitry Andric 55fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 56fe6060f1SDimitry Andric /* ========================================================================== 57fe6060f1SDimitry Andric Assembly Syntax: Vd32=vsplat(Rt32) 58fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt) 59fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 60fe6060f1SDimitry Andric Execution Slots: SLOT23 61fe6060f1SDimitry Andric ========================================================================== */ 62fe6060f1SDimitry Andric 63*0eae32dcSDimitry Andric #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) 64fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 65fe6060f1SDimitry Andric 66fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 67fe6060f1SDimitry Andric /* ========================================================================== 68fe6060f1SDimitry Andric Assembly Syntax: Qd4=and(Qs4,Qt4) 69fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) 70fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 71fe6060f1SDimitry Andric Execution Slots: SLOT0123 72fe6060f1SDimitry Andric ========================================================================== */ 73fe6060f1SDimitry Andric 74*0eae32dcSDimitry Andric #define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) 75fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 76fe6060f1SDimitry Andric 77fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 78fe6060f1SDimitry Andric /* ========================================================================== 79fe6060f1SDimitry Andric Assembly Syntax: Qd4=and(Qs4,!Qt4) 80fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) 81fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 82fe6060f1SDimitry Andric Execution Slots: SLOT0123 83fe6060f1SDimitry Andric ========================================================================== */ 84fe6060f1SDimitry Andric 85*0eae32dcSDimitry Andric #define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) 86fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 87fe6060f1SDimitry Andric 88fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 89fe6060f1SDimitry Andric /* ========================================================================== 90fe6060f1SDimitry Andric Assembly Syntax: Qd4=not(Qs4) 91fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs) 92fe6060f1SDimitry Andric Instruction Type: CVI_VA 93fe6060f1SDimitry Andric Execution Slots: SLOT0123 94fe6060f1SDimitry Andric ========================================================================== */ 95fe6060f1SDimitry Andric 96*0eae32dcSDimitry Andric #define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1) 97fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 98fe6060f1SDimitry Andric 99fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 100fe6060f1SDimitry Andric /* ========================================================================== 101fe6060f1SDimitry Andric Assembly Syntax: Qd4=or(Qs4,Qt4) 102fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) 103fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 104fe6060f1SDimitry Andric Execution Slots: SLOT0123 105fe6060f1SDimitry Andric ========================================================================== */ 106fe6060f1SDimitry Andric 107*0eae32dcSDimitry Andric #define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) 108fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 109fe6060f1SDimitry Andric 110fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 111fe6060f1SDimitry Andric /* ========================================================================== 112fe6060f1SDimitry Andric Assembly Syntax: Qd4=or(Qs4,!Qt4) 113fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) 114fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 115fe6060f1SDimitry Andric Execution Slots: SLOT0123 116fe6060f1SDimitry Andric ========================================================================== */ 117fe6060f1SDimitry Andric 118*0eae32dcSDimitry Andric #define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) 119fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 120fe6060f1SDimitry Andric 121fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 122fe6060f1SDimitry Andric /* ========================================================================== 123fe6060f1SDimitry Andric Assembly Syntax: Qd4=vsetq(Rt32) 124fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt) 125fe6060f1SDimitry Andric Instruction Type: CVI_VP 126fe6060f1SDimitry Andric Execution Slots: SLOT0123 127fe6060f1SDimitry Andric ========================================================================== */ 128fe6060f1SDimitry Andric 129*0eae32dcSDimitry Andric #define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1) 130fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 131fe6060f1SDimitry Andric 132fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 133fe6060f1SDimitry Andric /* ========================================================================== 134fe6060f1SDimitry Andric Assembly Syntax: Qd4=xor(Qs4,Qt4) 135fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) 136fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 137fe6060f1SDimitry Andric Execution Slots: SLOT0123 138fe6060f1SDimitry Andric ========================================================================== */ 139fe6060f1SDimitry Andric 140*0eae32dcSDimitry Andric #define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) 141fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 142fe6060f1SDimitry Andric 143fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 144fe6060f1SDimitry Andric /* ========================================================================== 145fe6060f1SDimitry Andric Assembly Syntax: if (!Qv4) vmem(Rt32+#s4)=Vs32 146fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) 147fe6060f1SDimitry Andric Instruction Type: CVI_VM_ST 148fe6060f1SDimitry Andric Execution Slots: SLOT0 149fe6060f1SDimitry Andric ========================================================================== */ 150fe6060f1SDimitry Andric 151*0eae32dcSDimitry Andric #define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) 152fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 153fe6060f1SDimitry Andric 154fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 155fe6060f1SDimitry Andric /* ========================================================================== 156fe6060f1SDimitry Andric Assembly Syntax: if (!Qv4) vmem(Rt32+#s4):nt=Vs32 157fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) 158fe6060f1SDimitry Andric Instruction Type: CVI_VM_ST 159fe6060f1SDimitry Andric Execution Slots: SLOT0 160fe6060f1SDimitry Andric ========================================================================== */ 161fe6060f1SDimitry Andric 162*0eae32dcSDimitry Andric #define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) 163fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 164fe6060f1SDimitry Andric 165fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 166fe6060f1SDimitry Andric /* ========================================================================== 167fe6060f1SDimitry Andric Assembly Syntax: if (Qv4) vmem(Rt32+#s4):nt=Vs32 168fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) 169fe6060f1SDimitry Andric Instruction Type: CVI_VM_ST 170fe6060f1SDimitry Andric Execution Slots: SLOT0 171fe6060f1SDimitry Andric ========================================================================== */ 172fe6060f1SDimitry Andric 173*0eae32dcSDimitry Andric #define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) 174fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 175fe6060f1SDimitry Andric 176fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 177fe6060f1SDimitry Andric /* ========================================================================== 178fe6060f1SDimitry Andric Assembly Syntax: if (Qv4) vmem(Rt32+#s4)=Vs32 179fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) 180fe6060f1SDimitry Andric Instruction Type: CVI_VM_ST 181fe6060f1SDimitry Andric Execution Slots: SLOT0 182fe6060f1SDimitry Andric ========================================================================== */ 183fe6060f1SDimitry Andric 184*0eae32dcSDimitry Andric #define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) 185fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 186fe6060f1SDimitry Andric 187fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 188fe6060f1SDimitry Andric /* ========================================================================== 189fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vabsdiff(Vu32.h,Vv32.h) 190fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv) 191fe6060f1SDimitry Andric Instruction Type: CVI_VX 192fe6060f1SDimitry Andric Execution Slots: SLOT23 193fe6060f1SDimitry Andric ========================================================================== */ 194fe6060f1SDimitry Andric 195*0eae32dcSDimitry Andric #define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv) 196fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 197fe6060f1SDimitry Andric 198fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 199fe6060f1SDimitry Andric /* ========================================================================== 200fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub) 201fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv) 202fe6060f1SDimitry Andric Instruction Type: CVI_VX 203fe6060f1SDimitry Andric Execution Slots: SLOT23 204fe6060f1SDimitry Andric ========================================================================== */ 205fe6060f1SDimitry Andric 206*0eae32dcSDimitry Andric #define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv) 207fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 208fe6060f1SDimitry Andric 209fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 210fe6060f1SDimitry Andric /* ========================================================================== 211fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh) 212fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) 213fe6060f1SDimitry Andric Instruction Type: CVI_VX 214fe6060f1SDimitry Andric Execution Slots: SLOT23 215fe6060f1SDimitry Andric ========================================================================== */ 216fe6060f1SDimitry Andric 217*0eae32dcSDimitry Andric #define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv) 218fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 219fe6060f1SDimitry Andric 220fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 221fe6060f1SDimitry Andric /* ========================================================================== 222fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vabsdiff(Vu32.w,Vv32.w) 223fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv) 224fe6060f1SDimitry Andric Instruction Type: CVI_VX 225fe6060f1SDimitry Andric Execution Slots: SLOT23 226fe6060f1SDimitry Andric ========================================================================== */ 227fe6060f1SDimitry Andric 228*0eae32dcSDimitry Andric #define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv) 229fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 230fe6060f1SDimitry Andric 231fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 232fe6060f1SDimitry Andric /* ========================================================================== 233fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vabs(Vu32.h) 234fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu) 235fe6060f1SDimitry Andric Instruction Type: CVI_VA 236fe6060f1SDimitry Andric Execution Slots: SLOT0123 237fe6060f1SDimitry Andric ========================================================================== */ 238fe6060f1SDimitry Andric 239*0eae32dcSDimitry Andric #define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu) 240fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 241fe6060f1SDimitry Andric 242fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 243fe6060f1SDimitry Andric /* ========================================================================== 244fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vabs(Vu32.h):sat 245fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu) 246fe6060f1SDimitry Andric Instruction Type: CVI_VA 247fe6060f1SDimitry Andric Execution Slots: SLOT0123 248fe6060f1SDimitry Andric ========================================================================== */ 249fe6060f1SDimitry Andric 250*0eae32dcSDimitry Andric #define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu) 251fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 252fe6060f1SDimitry Andric 253fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 254fe6060f1SDimitry Andric /* ========================================================================== 255fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vabs(Vu32.w) 256fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu) 257fe6060f1SDimitry Andric Instruction Type: CVI_VA 258fe6060f1SDimitry Andric Execution Slots: SLOT0123 259fe6060f1SDimitry Andric ========================================================================== */ 260fe6060f1SDimitry Andric 261*0eae32dcSDimitry Andric #define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu) 262fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 263fe6060f1SDimitry Andric 264fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 265fe6060f1SDimitry Andric /* ========================================================================== 266fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vabs(Vu32.w):sat 267fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu) 268fe6060f1SDimitry Andric Instruction Type: CVI_VA 269fe6060f1SDimitry Andric Execution Slots: SLOT0123 270fe6060f1SDimitry Andric ========================================================================== */ 271fe6060f1SDimitry Andric 272*0eae32dcSDimitry Andric #define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu) 273fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 274fe6060f1SDimitry Andric 275fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 276fe6060f1SDimitry Andric /* ========================================================================== 277fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b) 278fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv) 279fe6060f1SDimitry Andric Instruction Type: CVI_VA 280fe6060f1SDimitry Andric Execution Slots: SLOT0123 281fe6060f1SDimitry Andric ========================================================================== */ 282fe6060f1SDimitry Andric 283*0eae32dcSDimitry Andric #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) 284fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 285fe6060f1SDimitry Andric 286fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 287fe6060f1SDimitry Andric /* ========================================================================== 288fe6060f1SDimitry Andric Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b) 289fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 290fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 291fe6060f1SDimitry Andric Execution Slots: SLOT0123 292fe6060f1SDimitry Andric ========================================================================== */ 293fe6060f1SDimitry Andric 294*0eae32dcSDimitry Andric #define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv) 295fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 296fe6060f1SDimitry Andric 297fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 298fe6060f1SDimitry Andric /* ========================================================================== 299fe6060f1SDimitry Andric Assembly Syntax: if (!Qv4) Vx32.b+=Vu32.b 300fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 301fe6060f1SDimitry Andric Instruction Type: CVI_VA 302fe6060f1SDimitry Andric Execution Slots: SLOT0123 303fe6060f1SDimitry Andric ========================================================================== */ 304fe6060f1SDimitry Andric 305*0eae32dcSDimitry Andric #define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 306fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 307fe6060f1SDimitry Andric 308fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 309fe6060f1SDimitry Andric /* ========================================================================== 310fe6060f1SDimitry Andric Assembly Syntax: if (Qv4) Vx32.b+=Vu32.b 311fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 312fe6060f1SDimitry Andric Instruction Type: CVI_VA 313fe6060f1SDimitry Andric Execution Slots: SLOT0123 314fe6060f1SDimitry Andric ========================================================================== */ 315fe6060f1SDimitry Andric 316*0eae32dcSDimitry Andric #define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 317fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 318fe6060f1SDimitry Andric 319fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 320fe6060f1SDimitry Andric /* ========================================================================== 321fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h) 322fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) 323fe6060f1SDimitry Andric Instruction Type: CVI_VA 324fe6060f1SDimitry Andric Execution Slots: SLOT0123 325fe6060f1SDimitry Andric ========================================================================== */ 326fe6060f1SDimitry Andric 327*0eae32dcSDimitry Andric #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) 328fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 329fe6060f1SDimitry Andric 330fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 331fe6060f1SDimitry Andric /* ========================================================================== 332fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h) 333fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 334fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 335fe6060f1SDimitry Andric Execution Slots: SLOT0123 336fe6060f1SDimitry Andric ========================================================================== */ 337fe6060f1SDimitry Andric 338*0eae32dcSDimitry Andric #define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv) 339fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 340fe6060f1SDimitry Andric 341fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 342fe6060f1SDimitry Andric /* ========================================================================== 343fe6060f1SDimitry Andric Assembly Syntax: if (!Qv4) Vx32.h+=Vu32.h 344fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 345fe6060f1SDimitry Andric Instruction Type: CVI_VA 346fe6060f1SDimitry Andric Execution Slots: SLOT0123 347fe6060f1SDimitry Andric ========================================================================== */ 348fe6060f1SDimitry Andric 349*0eae32dcSDimitry Andric #define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 350fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 351fe6060f1SDimitry Andric 352fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 353fe6060f1SDimitry Andric /* ========================================================================== 354fe6060f1SDimitry Andric Assembly Syntax: if (Qv4) Vx32.h+=Vu32.h 355fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 356fe6060f1SDimitry Andric Instruction Type: CVI_VA 357fe6060f1SDimitry Andric Execution Slots: SLOT0123 358fe6060f1SDimitry Andric ========================================================================== */ 359fe6060f1SDimitry Andric 360*0eae32dcSDimitry Andric #define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 361fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 362fe6060f1SDimitry Andric 363fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 364fe6060f1SDimitry Andric /* ========================================================================== 365fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h):sat 366fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) 367fe6060f1SDimitry Andric Instruction Type: CVI_VA 368fe6060f1SDimitry Andric Execution Slots: SLOT0123 369fe6060f1SDimitry Andric ========================================================================== */ 370fe6060f1SDimitry Andric 371*0eae32dcSDimitry Andric #define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv) 372fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 373fe6060f1SDimitry Andric 374fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 375fe6060f1SDimitry Andric /* ========================================================================== 376fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat 377fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 378fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 379fe6060f1SDimitry Andric Execution Slots: SLOT0123 380fe6060f1SDimitry Andric ========================================================================== */ 381fe6060f1SDimitry Andric 382*0eae32dcSDimitry Andric #define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv) 383fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 384fe6060f1SDimitry Andric 385fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 386fe6060f1SDimitry Andric /* ========================================================================== 387fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vadd(Vu32.h,Vv32.h) 388fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) 389fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 390fe6060f1SDimitry Andric Execution Slots: SLOT23 391fe6060f1SDimitry Andric ========================================================================== */ 392fe6060f1SDimitry Andric 393*0eae32dcSDimitry Andric #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) 394fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 395fe6060f1SDimitry Andric 396fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 397fe6060f1SDimitry Andric /* ========================================================================== 398fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vadd(Vu32.ub,Vv32.ub) 399fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv) 400fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 401fe6060f1SDimitry Andric Execution Slots: SLOT23 402fe6060f1SDimitry Andric ========================================================================== */ 403fe6060f1SDimitry Andric 404*0eae32dcSDimitry Andric #define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv) 405fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 406fe6060f1SDimitry Andric 407fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 408fe6060f1SDimitry Andric /* ========================================================================== 409fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat 410fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) 411fe6060f1SDimitry Andric Instruction Type: CVI_VA 412fe6060f1SDimitry Andric Execution Slots: SLOT0123 413fe6060f1SDimitry Andric ========================================================================== */ 414fe6060f1SDimitry Andric 415*0eae32dcSDimitry Andric #define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv) 416fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 417fe6060f1SDimitry Andric 418fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 419fe6060f1SDimitry Andric /* ========================================================================== 420fe6060f1SDimitry Andric Assembly Syntax: Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat 421fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 422fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 423fe6060f1SDimitry Andric Execution Slots: SLOT0123 424fe6060f1SDimitry Andric ========================================================================== */ 425fe6060f1SDimitry Andric 426*0eae32dcSDimitry Andric #define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv) 427fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 428fe6060f1SDimitry Andric 429fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 430fe6060f1SDimitry Andric /* ========================================================================== 431fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat 432fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) 433fe6060f1SDimitry Andric Instruction Type: CVI_VA 434fe6060f1SDimitry Andric Execution Slots: SLOT0123 435fe6060f1SDimitry Andric ========================================================================== */ 436fe6060f1SDimitry Andric 437*0eae32dcSDimitry Andric #define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv) 438fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 439fe6060f1SDimitry Andric 440fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 441fe6060f1SDimitry Andric /* ========================================================================== 442fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat 443fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 444fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 445fe6060f1SDimitry Andric Execution Slots: SLOT0123 446fe6060f1SDimitry Andric ========================================================================== */ 447fe6060f1SDimitry Andric 448*0eae32dcSDimitry Andric #define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv) 449fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 450fe6060f1SDimitry Andric 451fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 452fe6060f1SDimitry Andric /* ========================================================================== 453fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vadd(Vu32.uh,Vv32.uh) 454fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) 455fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 456fe6060f1SDimitry Andric Execution Slots: SLOT23 457fe6060f1SDimitry Andric ========================================================================== */ 458fe6060f1SDimitry Andric 459*0eae32dcSDimitry Andric #define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv) 460fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 461fe6060f1SDimitry Andric 462fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 463fe6060f1SDimitry Andric /* ========================================================================== 464fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w) 465fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv) 466fe6060f1SDimitry Andric Instruction Type: CVI_VA 467fe6060f1SDimitry Andric Execution Slots: SLOT0123 468fe6060f1SDimitry Andric ========================================================================== */ 469fe6060f1SDimitry Andric 470*0eae32dcSDimitry Andric #define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv) 471fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 472fe6060f1SDimitry Andric 473fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 474fe6060f1SDimitry Andric /* ========================================================================== 475fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w) 476fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 477fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 478fe6060f1SDimitry Andric Execution Slots: SLOT0123 479fe6060f1SDimitry Andric ========================================================================== */ 480fe6060f1SDimitry Andric 481*0eae32dcSDimitry Andric #define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv) 482fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 483fe6060f1SDimitry Andric 484fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 485fe6060f1SDimitry Andric /* ========================================================================== 486fe6060f1SDimitry Andric Assembly Syntax: if (!Qv4) Vx32.w+=Vu32.w 487fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 488fe6060f1SDimitry Andric Instruction Type: CVI_VA 489fe6060f1SDimitry Andric Execution Slots: SLOT0123 490fe6060f1SDimitry Andric ========================================================================== */ 491fe6060f1SDimitry Andric 492*0eae32dcSDimitry Andric #define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 493fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 494fe6060f1SDimitry Andric 495fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 496fe6060f1SDimitry Andric /* ========================================================================== 497fe6060f1SDimitry Andric Assembly Syntax: if (Qv4) Vx32.w+=Vu32.w 498fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 499fe6060f1SDimitry Andric Instruction Type: CVI_VA 500fe6060f1SDimitry Andric Execution Slots: SLOT0123 501fe6060f1SDimitry Andric ========================================================================== */ 502fe6060f1SDimitry Andric 503*0eae32dcSDimitry Andric #define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 504fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 505fe6060f1SDimitry Andric 506fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 507fe6060f1SDimitry Andric /* ========================================================================== 508fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w):sat 509fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) 510fe6060f1SDimitry Andric Instruction Type: CVI_VA 511fe6060f1SDimitry Andric Execution Slots: SLOT0123 512fe6060f1SDimitry Andric ========================================================================== */ 513fe6060f1SDimitry Andric 514*0eae32dcSDimitry Andric #define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv) 515fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 516fe6060f1SDimitry Andric 517fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 518fe6060f1SDimitry Andric /* ========================================================================== 519fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat 520fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 521fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 522fe6060f1SDimitry Andric Execution Slots: SLOT0123 523fe6060f1SDimitry Andric ========================================================================== */ 524fe6060f1SDimitry Andric 525*0eae32dcSDimitry Andric #define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv) 526fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 527fe6060f1SDimitry Andric 528fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 529fe6060f1SDimitry Andric /* ========================================================================== 530fe6060f1SDimitry Andric Assembly Syntax: Vd32=valign(Vu32,Vv32,Rt8) 531fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 532fe6060f1SDimitry Andric Instruction Type: CVI_VP 533fe6060f1SDimitry Andric Execution Slots: SLOT0123 534fe6060f1SDimitry Andric ========================================================================== */ 535fe6060f1SDimitry Andric 536*0eae32dcSDimitry Andric #define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) 537fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 538fe6060f1SDimitry Andric 539fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 540fe6060f1SDimitry Andric /* ========================================================================== 541fe6060f1SDimitry Andric Assembly Syntax: Vd32=valign(Vu32,Vv32,#u3) 542fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) 543fe6060f1SDimitry Andric Instruction Type: CVI_VP 544fe6060f1SDimitry Andric Execution Slots: SLOT0123 545fe6060f1SDimitry Andric ========================================================================== */ 546fe6060f1SDimitry Andric 547*0eae32dcSDimitry Andric #define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3) 548fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 549fe6060f1SDimitry Andric 550fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 551fe6060f1SDimitry Andric /* ========================================================================== 552fe6060f1SDimitry Andric Assembly Syntax: Vd32=vand(Vu32,Vv32) 553fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv) 554fe6060f1SDimitry Andric Instruction Type: CVI_VA 555fe6060f1SDimitry Andric Execution Slots: SLOT0123 556fe6060f1SDimitry Andric ========================================================================== */ 557fe6060f1SDimitry Andric 558*0eae32dcSDimitry Andric #define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv) 559fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 560fe6060f1SDimitry Andric 561fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 562fe6060f1SDimitry Andric /* ========================================================================== 563fe6060f1SDimitry Andric Assembly Syntax: Vd32=vand(Qu4,Rt32) 564fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt) 565fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 566fe6060f1SDimitry Andric Execution Slots: SLOT23 567fe6060f1SDimitry Andric ========================================================================== */ 568fe6060f1SDimitry Andric 569*0eae32dcSDimitry Andric #define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) 570fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 571fe6060f1SDimitry Andric 572fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 573fe6060f1SDimitry Andric /* ========================================================================== 574fe6060f1SDimitry Andric Assembly Syntax: Vx32|=vand(Qu4,Rt32) 575fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) 576fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 577fe6060f1SDimitry Andric Execution Slots: SLOT23 578fe6060f1SDimitry Andric ========================================================================== */ 579fe6060f1SDimitry Andric 580*0eae32dcSDimitry Andric #define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) 581fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 582fe6060f1SDimitry Andric 583fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 584fe6060f1SDimitry Andric /* ========================================================================== 585fe6060f1SDimitry Andric Assembly Syntax: Qd4=vand(Vu32,Rt32) 586fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt) 587fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 588fe6060f1SDimitry Andric Execution Slots: SLOT23 589fe6060f1SDimitry Andric ========================================================================== */ 590fe6060f1SDimitry Andric 591*0eae32dcSDimitry Andric #define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1) 592fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 593fe6060f1SDimitry Andric 594fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 595fe6060f1SDimitry Andric /* ========================================================================== 596fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vand(Vu32,Rt32) 597fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt) 598fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 599fe6060f1SDimitry Andric Execution Slots: SLOT23 600fe6060f1SDimitry Andric ========================================================================== */ 601fe6060f1SDimitry Andric 602*0eae32dcSDimitry Andric #define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1) 603fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 604fe6060f1SDimitry Andric 605fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 606fe6060f1SDimitry Andric /* ========================================================================== 607fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vasl(Vu32.h,Rt32) 608fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt) 609fe6060f1SDimitry Andric Instruction Type: CVI_VS 610fe6060f1SDimitry Andric Execution Slots: SLOT0123 611fe6060f1SDimitry Andric ========================================================================== */ 612fe6060f1SDimitry Andric 613*0eae32dcSDimitry Andric #define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt) 614fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 615fe6060f1SDimitry Andric 616fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 617fe6060f1SDimitry Andric /* ========================================================================== 618fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vasl(Vu32.h,Vv32.h) 619fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv) 620fe6060f1SDimitry Andric Instruction Type: CVI_VS 621fe6060f1SDimitry Andric Execution Slots: SLOT0123 622fe6060f1SDimitry Andric ========================================================================== */ 623fe6060f1SDimitry Andric 624*0eae32dcSDimitry Andric #define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv) 625fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 626fe6060f1SDimitry Andric 627fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 628fe6060f1SDimitry Andric /* ========================================================================== 629fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vasl(Vu32.w,Rt32) 630fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt) 631fe6060f1SDimitry Andric Instruction Type: CVI_VS 632fe6060f1SDimitry Andric Execution Slots: SLOT0123 633fe6060f1SDimitry Andric ========================================================================== */ 634fe6060f1SDimitry Andric 635*0eae32dcSDimitry Andric #define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt) 636fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 637fe6060f1SDimitry Andric 638fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 639fe6060f1SDimitry Andric /* ========================================================================== 640fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vasl(Vu32.w,Rt32) 641fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 642fe6060f1SDimitry Andric Instruction Type: CVI_VS 643fe6060f1SDimitry Andric Execution Slots: SLOT0123 644fe6060f1SDimitry Andric ========================================================================== */ 645fe6060f1SDimitry Andric 646*0eae32dcSDimitry Andric #define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt) 647fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 648fe6060f1SDimitry Andric 649fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 650fe6060f1SDimitry Andric /* ========================================================================== 651fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vasl(Vu32.w,Vv32.w) 652fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv) 653fe6060f1SDimitry Andric Instruction Type: CVI_VS 654fe6060f1SDimitry Andric Execution Slots: SLOT0123 655fe6060f1SDimitry Andric ========================================================================== */ 656fe6060f1SDimitry Andric 657*0eae32dcSDimitry Andric #define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv) 658fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 659fe6060f1SDimitry Andric 660fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 661fe6060f1SDimitry Andric /* ========================================================================== 662fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vasr(Vu32.h,Rt32) 663fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt) 664fe6060f1SDimitry Andric Instruction Type: CVI_VS 665fe6060f1SDimitry Andric Execution Slots: SLOT0123 666fe6060f1SDimitry Andric ========================================================================== */ 667fe6060f1SDimitry Andric 668*0eae32dcSDimitry Andric #define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt) 669fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 670fe6060f1SDimitry Andric 671fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 672fe6060f1SDimitry Andric /* ========================================================================== 673fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat 674fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 675fe6060f1SDimitry Andric Instruction Type: CVI_VS 676fe6060f1SDimitry Andric Execution Slots: SLOT0123 677fe6060f1SDimitry Andric ========================================================================== */ 678fe6060f1SDimitry Andric 679*0eae32dcSDimitry Andric #define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt) 680fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 681fe6060f1SDimitry Andric 682fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 683fe6060f1SDimitry Andric /* ========================================================================== 684fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat 685fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 686fe6060f1SDimitry Andric Instruction Type: CVI_VS 687fe6060f1SDimitry Andric Execution Slots: SLOT0123 688fe6060f1SDimitry Andric ========================================================================== */ 689fe6060f1SDimitry Andric 690*0eae32dcSDimitry Andric #define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt) 691fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 692fe6060f1SDimitry Andric 693fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 694fe6060f1SDimitry Andric /* ========================================================================== 695fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat 696fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 697fe6060f1SDimitry Andric Instruction Type: CVI_VS 698fe6060f1SDimitry Andric Execution Slots: SLOT0123 699fe6060f1SDimitry Andric ========================================================================== */ 700fe6060f1SDimitry Andric 701*0eae32dcSDimitry Andric #define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt) 702fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 703fe6060f1SDimitry Andric 704fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 705fe6060f1SDimitry Andric /* ========================================================================== 706fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vasr(Vu32.h,Vv32.h) 707fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv) 708fe6060f1SDimitry Andric Instruction Type: CVI_VS 709fe6060f1SDimitry Andric Execution Slots: SLOT0123 710fe6060f1SDimitry Andric ========================================================================== */ 711fe6060f1SDimitry Andric 712*0eae32dcSDimitry Andric #define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv) 713fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 714fe6060f1SDimitry Andric 715fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 716fe6060f1SDimitry Andric /* ========================================================================== 717fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vasr(Vu32.w,Rt32) 718fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt) 719fe6060f1SDimitry Andric Instruction Type: CVI_VS 720fe6060f1SDimitry Andric Execution Slots: SLOT0123 721fe6060f1SDimitry Andric ========================================================================== */ 722fe6060f1SDimitry Andric 723*0eae32dcSDimitry Andric #define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt) 724fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 725fe6060f1SDimitry Andric 726fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 727fe6060f1SDimitry Andric /* ========================================================================== 728fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vasr(Vu32.w,Rt32) 729fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 730fe6060f1SDimitry Andric Instruction Type: CVI_VS 731fe6060f1SDimitry Andric Execution Slots: SLOT0123 732fe6060f1SDimitry Andric ========================================================================== */ 733fe6060f1SDimitry Andric 734*0eae32dcSDimitry Andric #define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt) 735fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 736fe6060f1SDimitry Andric 737fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 738fe6060f1SDimitry Andric /* ========================================================================== 739fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8) 740fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 741fe6060f1SDimitry Andric Instruction Type: CVI_VS 742fe6060f1SDimitry Andric Execution Slots: SLOT0123 743fe6060f1SDimitry Andric ========================================================================== */ 744fe6060f1SDimitry Andric 745*0eae32dcSDimitry Andric #define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt) 746fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 747fe6060f1SDimitry Andric 748fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 749fe6060f1SDimitry Andric /* ========================================================================== 750fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat 751fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 752fe6060f1SDimitry Andric Instruction Type: CVI_VS 753fe6060f1SDimitry Andric Execution Slots: SLOT0123 754fe6060f1SDimitry Andric ========================================================================== */ 755fe6060f1SDimitry Andric 756*0eae32dcSDimitry Andric #define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt) 757fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 758fe6060f1SDimitry Andric 759fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 760fe6060f1SDimitry Andric /* ========================================================================== 761fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat 762fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 763fe6060f1SDimitry Andric Instruction Type: CVI_VS 764fe6060f1SDimitry Andric Execution Slots: SLOT0123 765fe6060f1SDimitry Andric ========================================================================== */ 766fe6060f1SDimitry Andric 767*0eae32dcSDimitry Andric #define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt) 768fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 769fe6060f1SDimitry Andric 770fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 771fe6060f1SDimitry Andric /* ========================================================================== 772fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat 773fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 774fe6060f1SDimitry Andric Instruction Type: CVI_VS 775fe6060f1SDimitry Andric Execution Slots: SLOT0123 776fe6060f1SDimitry Andric ========================================================================== */ 777fe6060f1SDimitry Andric 778*0eae32dcSDimitry Andric #define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt) 779fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 780fe6060f1SDimitry Andric 781fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 782fe6060f1SDimitry Andric /* ========================================================================== 783fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vasr(Vu32.w,Vv32.w) 784fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv) 785fe6060f1SDimitry Andric Instruction Type: CVI_VS 786fe6060f1SDimitry Andric Execution Slots: SLOT0123 787fe6060f1SDimitry Andric ========================================================================== */ 788fe6060f1SDimitry Andric 789*0eae32dcSDimitry Andric #define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv) 790fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 791fe6060f1SDimitry Andric 792fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 793fe6060f1SDimitry Andric /* ========================================================================== 794fe6060f1SDimitry Andric Assembly Syntax: Vd32=Vu32 795fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu) 796fe6060f1SDimitry Andric Instruction Type: CVI_VA 797fe6060f1SDimitry Andric Execution Slots: SLOT0123 798fe6060f1SDimitry Andric ========================================================================== */ 799fe6060f1SDimitry Andric 800*0eae32dcSDimitry Andric #define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu) 801fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 802fe6060f1SDimitry Andric 803fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 804fe6060f1SDimitry Andric /* ========================================================================== 805fe6060f1SDimitry Andric Assembly Syntax: Vdd32=Vuu32 806fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu) 807fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 808fe6060f1SDimitry Andric Execution Slots: SLOT0123 809fe6060f1SDimitry Andric ========================================================================== */ 810fe6060f1SDimitry Andric 811*0eae32dcSDimitry Andric #define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu) 812fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 813fe6060f1SDimitry Andric 814fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 815fe6060f1SDimitry Andric /* ========================================================================== 816fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h) 817fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) 818fe6060f1SDimitry Andric Instruction Type: CVI_VA 819fe6060f1SDimitry Andric Execution Slots: SLOT0123 820fe6060f1SDimitry Andric ========================================================================== */ 821fe6060f1SDimitry Andric 822*0eae32dcSDimitry Andric #define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv) 823fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 824fe6060f1SDimitry Andric 825fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 826fe6060f1SDimitry Andric /* ========================================================================== 827fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h):rnd 828fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv) 829fe6060f1SDimitry Andric Instruction Type: CVI_VA 830fe6060f1SDimitry Andric Execution Slots: SLOT0123 831fe6060f1SDimitry Andric ========================================================================== */ 832fe6060f1SDimitry Andric 833*0eae32dcSDimitry Andric #define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv) 834fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 835fe6060f1SDimitry Andric 836fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 837fe6060f1SDimitry Andric /* ========================================================================== 838fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub) 839fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) 840fe6060f1SDimitry Andric Instruction Type: CVI_VA 841fe6060f1SDimitry Andric Execution Slots: SLOT0123 842fe6060f1SDimitry Andric ========================================================================== */ 843fe6060f1SDimitry Andric 844*0eae32dcSDimitry Andric #define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv) 845fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 846fe6060f1SDimitry Andric 847fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 848fe6060f1SDimitry Andric /* ========================================================================== 849fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd 850fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv) 851fe6060f1SDimitry Andric Instruction Type: CVI_VA 852fe6060f1SDimitry Andric Execution Slots: SLOT0123 853fe6060f1SDimitry Andric ========================================================================== */ 854fe6060f1SDimitry Andric 855*0eae32dcSDimitry Andric #define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv) 856fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 857fe6060f1SDimitry Andric 858fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 859fe6060f1SDimitry Andric /* ========================================================================== 860fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh) 861fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) 862fe6060f1SDimitry Andric Instruction Type: CVI_VA 863fe6060f1SDimitry Andric Execution Slots: SLOT0123 864fe6060f1SDimitry Andric ========================================================================== */ 865fe6060f1SDimitry Andric 866*0eae32dcSDimitry Andric #define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv) 867fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 868fe6060f1SDimitry Andric 869fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 870fe6060f1SDimitry Andric /* ========================================================================== 871fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd 872fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv) 873fe6060f1SDimitry Andric Instruction Type: CVI_VA 874fe6060f1SDimitry Andric Execution Slots: SLOT0123 875fe6060f1SDimitry Andric ========================================================================== */ 876fe6060f1SDimitry Andric 877*0eae32dcSDimitry Andric #define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv) 878fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 879fe6060f1SDimitry Andric 880fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 881fe6060f1SDimitry Andric /* ========================================================================== 882fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w) 883fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) 884fe6060f1SDimitry Andric Instruction Type: CVI_VA 885fe6060f1SDimitry Andric Execution Slots: SLOT0123 886fe6060f1SDimitry Andric ========================================================================== */ 887fe6060f1SDimitry Andric 888*0eae32dcSDimitry Andric #define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv) 889fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 890fe6060f1SDimitry Andric 891fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 892fe6060f1SDimitry Andric /* ========================================================================== 893fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w):rnd 894fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv) 895fe6060f1SDimitry Andric Instruction Type: CVI_VA 896fe6060f1SDimitry Andric Execution Slots: SLOT0123 897fe6060f1SDimitry Andric ========================================================================== */ 898fe6060f1SDimitry Andric 899*0eae32dcSDimitry Andric #define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv) 900fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 901fe6060f1SDimitry Andric 902fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 903fe6060f1SDimitry Andric /* ========================================================================== 904fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vcl0(Vu32.uh) 905fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu) 906fe6060f1SDimitry Andric Instruction Type: CVI_VS 907fe6060f1SDimitry Andric Execution Slots: SLOT0123 908fe6060f1SDimitry Andric ========================================================================== */ 909fe6060f1SDimitry Andric 910*0eae32dcSDimitry Andric #define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu) 911fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 912fe6060f1SDimitry Andric 913fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 914fe6060f1SDimitry Andric /* ========================================================================== 915fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vcl0(Vu32.uw) 916fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu) 917fe6060f1SDimitry Andric Instruction Type: CVI_VS 918fe6060f1SDimitry Andric Execution Slots: SLOT0123 919fe6060f1SDimitry Andric ========================================================================== */ 920fe6060f1SDimitry Andric 921*0eae32dcSDimitry Andric #define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu) 922fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 923fe6060f1SDimitry Andric 924fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 925fe6060f1SDimitry Andric /* ========================================================================== 926fe6060f1SDimitry Andric Assembly Syntax: Vdd32=vcombine(Vu32,Vv32) 927fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv) 928fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 929fe6060f1SDimitry Andric Execution Slots: SLOT0123 930fe6060f1SDimitry Andric ========================================================================== */ 931fe6060f1SDimitry Andric 932*0eae32dcSDimitry Andric #define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv) 933fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 934fe6060f1SDimitry Andric 935fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 936fe6060f1SDimitry Andric /* ========================================================================== 937fe6060f1SDimitry Andric Assembly Syntax: Vd32=#0 938fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vzero() 939fe6060f1SDimitry Andric Instruction Type: CVI_VA 940fe6060f1SDimitry Andric Execution Slots: SLOT0123 941fe6060f1SDimitry Andric ========================================================================== */ 942fe6060f1SDimitry Andric 943*0eae32dcSDimitry Andric #define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)() 944fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 945fe6060f1SDimitry Andric 946fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 947fe6060f1SDimitry Andric /* ========================================================================== 948fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vdeal(Vu32.b) 949fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu) 950fe6060f1SDimitry Andric Instruction Type: CVI_VP 951fe6060f1SDimitry Andric Execution Slots: SLOT0123 952fe6060f1SDimitry Andric ========================================================================== */ 953fe6060f1SDimitry Andric 954*0eae32dcSDimitry Andric #define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu) 955fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 956fe6060f1SDimitry Andric 957fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 958fe6060f1SDimitry Andric /* ========================================================================== 959fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vdeale(Vu32.b,Vv32.b) 960fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv) 961fe6060f1SDimitry Andric Instruction Type: CVI_VP 962fe6060f1SDimitry Andric Execution Slots: SLOT0123 963fe6060f1SDimitry Andric ========================================================================== */ 964fe6060f1SDimitry Andric 965*0eae32dcSDimitry Andric #define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv) 966fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 967fe6060f1SDimitry Andric 968fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 969fe6060f1SDimitry Andric /* ========================================================================== 970fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vdeal(Vu32.h) 971fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu) 972fe6060f1SDimitry Andric Instruction Type: CVI_VP 973fe6060f1SDimitry Andric Execution Slots: SLOT0123 974fe6060f1SDimitry Andric ========================================================================== */ 975fe6060f1SDimitry Andric 976*0eae32dcSDimitry Andric #define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu) 977fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 978fe6060f1SDimitry Andric 979fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 980fe6060f1SDimitry Andric /* ========================================================================== 981fe6060f1SDimitry Andric Assembly Syntax: Vdd32=vdeal(Vu32,Vv32,Rt8) 982fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 983fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 984fe6060f1SDimitry Andric Execution Slots: SLOT0123 985fe6060f1SDimitry Andric ========================================================================== */ 986fe6060f1SDimitry Andric 987*0eae32dcSDimitry Andric #define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt) 988fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 989fe6060f1SDimitry Andric 990fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 991fe6060f1SDimitry Andric /* ========================================================================== 992fe6060f1SDimitry Andric Assembly Syntax: Vd32=vdelta(Vu32,Vv32) 993fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv) 994fe6060f1SDimitry Andric Instruction Type: CVI_VP 995fe6060f1SDimitry Andric Execution Slots: SLOT0123 996fe6060f1SDimitry Andric ========================================================================== */ 997fe6060f1SDimitry Andric 998*0eae32dcSDimitry Andric #define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv) 999fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1000fe6060f1SDimitry Andric 1001fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1002fe6060f1SDimitry Andric /* ========================================================================== 1003fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vdmpy(Vu32.ub,Rt32.b) 1004fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt) 1005fe6060f1SDimitry Andric Instruction Type: CVI_VX 1006fe6060f1SDimitry Andric Execution Slots: SLOT23 1007fe6060f1SDimitry Andric ========================================================================== */ 1008fe6060f1SDimitry Andric 1009*0eae32dcSDimitry Andric #define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt) 1010fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1011fe6060f1SDimitry Andric 1012fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1013fe6060f1SDimitry Andric /* ========================================================================== 1014fe6060f1SDimitry Andric Assembly Syntax: Vx32.h+=vdmpy(Vu32.ub,Rt32.b) 1015fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 1016fe6060f1SDimitry Andric Instruction Type: CVI_VX 1017fe6060f1SDimitry Andric Execution Slots: SLOT23 1018fe6060f1SDimitry Andric ========================================================================== */ 1019fe6060f1SDimitry Andric 1020*0eae32dcSDimitry Andric #define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt) 1021fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1022fe6060f1SDimitry Andric 1023fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1024fe6060f1SDimitry Andric /* ========================================================================== 1025fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vdmpy(Vuu32.ub,Rt32.b) 1026fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) 1027fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1028fe6060f1SDimitry Andric Execution Slots: SLOT23 1029fe6060f1SDimitry Andric ========================================================================== */ 1030fe6060f1SDimitry Andric 1031*0eae32dcSDimitry Andric #define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt) 1032fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1033fe6060f1SDimitry Andric 1034fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1035fe6060f1SDimitry Andric /* ========================================================================== 1036fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b) 1037fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 1038fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1039fe6060f1SDimitry Andric Execution Slots: SLOT23 1040fe6060f1SDimitry Andric ========================================================================== */ 1041fe6060f1SDimitry Andric 1042*0eae32dcSDimitry Andric #define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt) 1043fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1044fe6060f1SDimitry Andric 1045fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1046fe6060f1SDimitry Andric /* ========================================================================== 1047fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.b) 1048fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt) 1049fe6060f1SDimitry Andric Instruction Type: CVI_VX 1050fe6060f1SDimitry Andric Execution Slots: SLOT23 1051fe6060f1SDimitry Andric ========================================================================== */ 1052fe6060f1SDimitry Andric 1053*0eae32dcSDimitry Andric #define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt) 1054fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1055fe6060f1SDimitry Andric 1056fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1057fe6060f1SDimitry Andric /* ========================================================================== 1058fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.b) 1059fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 1060fe6060f1SDimitry Andric Instruction Type: CVI_VX 1061fe6060f1SDimitry Andric Execution Slots: SLOT23 1062fe6060f1SDimitry Andric ========================================================================== */ 1063fe6060f1SDimitry Andric 1064*0eae32dcSDimitry Andric #define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt) 1065fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1066fe6060f1SDimitry Andric 1067fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1068fe6060f1SDimitry Andric /* ========================================================================== 1069fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vdmpy(Vuu32.h,Rt32.b) 1070fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) 1071fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1072fe6060f1SDimitry Andric Execution Slots: SLOT23 1073fe6060f1SDimitry Andric ========================================================================== */ 1074fe6060f1SDimitry Andric 1075*0eae32dcSDimitry Andric #define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt) 1076fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1077fe6060f1SDimitry Andric 1078fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1079fe6060f1SDimitry Andric /* ========================================================================== 1080fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vdmpy(Vuu32.h,Rt32.b) 1081fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 1082fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1083fe6060f1SDimitry Andric Execution Slots: SLOT23 1084fe6060f1SDimitry Andric ========================================================================== */ 1085fe6060f1SDimitry Andric 1086*0eae32dcSDimitry Andric #define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt) 1087fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1088fe6060f1SDimitry Andric 1089fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1090fe6060f1SDimitry Andric /* ========================================================================== 1091fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat 1092fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt) 1093fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1094fe6060f1SDimitry Andric Execution Slots: SLOT23 1095fe6060f1SDimitry Andric ========================================================================== */ 1096fe6060f1SDimitry Andric 1097*0eae32dcSDimitry Andric #define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt) 1098fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1099fe6060f1SDimitry Andric 1100fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1101fe6060f1SDimitry Andric /* ========================================================================== 1102fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat 1103fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) 1104fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1105fe6060f1SDimitry Andric Execution Slots: SLOT23 1106fe6060f1SDimitry Andric ========================================================================== */ 1107fe6060f1SDimitry Andric 1108*0eae32dcSDimitry Andric #define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt) 1109fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1110fe6060f1SDimitry Andric 1111fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1112fe6060f1SDimitry Andric /* ========================================================================== 1113fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat 1114fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt) 1115*0eae32dcSDimitry Andric Instruction Type: CVI_VX 1116fe6060f1SDimitry Andric Execution Slots: SLOT23 1117fe6060f1SDimitry Andric ========================================================================== */ 1118fe6060f1SDimitry Andric 1119*0eae32dcSDimitry Andric #define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt) 1120fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1121fe6060f1SDimitry Andric 1122fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1123fe6060f1SDimitry Andric /* ========================================================================== 1124fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat 1125fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 1126*0eae32dcSDimitry Andric Instruction Type: CVI_VX 1127fe6060f1SDimitry Andric Execution Slots: SLOT23 1128fe6060f1SDimitry Andric ========================================================================== */ 1129fe6060f1SDimitry Andric 1130*0eae32dcSDimitry Andric #define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt) 1131fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1132fe6060f1SDimitry Andric 1133fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1134fe6060f1SDimitry Andric /* ========================================================================== 1135fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat 1136fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt) 1137fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1138fe6060f1SDimitry Andric Execution Slots: SLOT23 1139fe6060f1SDimitry Andric ========================================================================== */ 1140fe6060f1SDimitry Andric 1141*0eae32dcSDimitry Andric #define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt) 1142fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1143fe6060f1SDimitry Andric 1144fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1145fe6060f1SDimitry Andric /* ========================================================================== 1146fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat 1147fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) 1148fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1149fe6060f1SDimitry Andric Execution Slots: SLOT23 1150fe6060f1SDimitry Andric ========================================================================== */ 1151fe6060f1SDimitry Andric 1152*0eae32dcSDimitry Andric #define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt) 1153fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1154fe6060f1SDimitry Andric 1155fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1156fe6060f1SDimitry Andric /* ========================================================================== 1157fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat 1158fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt) 1159*0eae32dcSDimitry Andric Instruction Type: CVI_VX 1160fe6060f1SDimitry Andric Execution Slots: SLOT23 1161fe6060f1SDimitry Andric ========================================================================== */ 1162fe6060f1SDimitry Andric 1163*0eae32dcSDimitry Andric #define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt) 1164fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1165fe6060f1SDimitry Andric 1166fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1167fe6060f1SDimitry Andric /* ========================================================================== 1168fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat 1169fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 1170*0eae32dcSDimitry Andric Instruction Type: CVI_VX 1171fe6060f1SDimitry Andric Execution Slots: SLOT23 1172fe6060f1SDimitry Andric ========================================================================== */ 1173fe6060f1SDimitry Andric 1174*0eae32dcSDimitry Andric #define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt) 1175fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1176fe6060f1SDimitry Andric 1177fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1178fe6060f1SDimitry Andric /* ========================================================================== 1179fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat 1180fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) 1181*0eae32dcSDimitry Andric Instruction Type: CVI_VX 1182fe6060f1SDimitry Andric Execution Slots: SLOT23 1183fe6060f1SDimitry Andric ========================================================================== */ 1184fe6060f1SDimitry Andric 1185*0eae32dcSDimitry Andric #define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv) 1186fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1187fe6060f1SDimitry Andric 1188fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1189fe6060f1SDimitry Andric /* ========================================================================== 1190fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat 1191fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 1192fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1193fe6060f1SDimitry Andric Execution Slots: SLOT23 1194fe6060f1SDimitry Andric ========================================================================== */ 1195fe6060f1SDimitry Andric 1196*0eae32dcSDimitry Andric #define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv) 1197fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1198fe6060f1SDimitry Andric 1199fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1200fe6060f1SDimitry Andric /* ========================================================================== 1201fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh) 1202fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt) 1203fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1204fe6060f1SDimitry Andric Execution Slots: SLOT23 1205fe6060f1SDimitry Andric ========================================================================== */ 1206fe6060f1SDimitry Andric 1207*0eae32dcSDimitry Andric #define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt) 1208fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1209fe6060f1SDimitry Andric 1210fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1211fe6060f1SDimitry Andric /* ========================================================================== 1212fe6060f1SDimitry Andric Assembly Syntax: Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh) 1213fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 1214fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1215fe6060f1SDimitry Andric Execution Slots: SLOT23 1216fe6060f1SDimitry Andric ========================================================================== */ 1217fe6060f1SDimitry Andric 1218*0eae32dcSDimitry Andric #define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt) 1219fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1220fe6060f1SDimitry Andric 1221fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1222fe6060f1SDimitry Andric /* ========================================================================== 1223fe6060f1SDimitry Andric Assembly Syntax: Qd4=vcmp.eq(Vu32.b,Vv32.b) 1224fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv) 1225fe6060f1SDimitry Andric Instruction Type: CVI_VA 1226fe6060f1SDimitry Andric Execution Slots: SLOT0123 1227fe6060f1SDimitry Andric ========================================================================== */ 1228fe6060f1SDimitry Andric 1229*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1) 1230fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1231fe6060f1SDimitry Andric 1232fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1233fe6060f1SDimitry Andric /* ========================================================================== 1234fe6060f1SDimitry Andric Assembly Syntax: Qx4&=vcmp.eq(Vu32.b,Vv32.b) 1235fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1236fe6060f1SDimitry Andric Instruction Type: CVI_VA 1237fe6060f1SDimitry Andric Execution Slots: SLOT0123 1238fe6060f1SDimitry Andric ========================================================================== */ 1239fe6060f1SDimitry Andric 1240*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1241fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1242fe6060f1SDimitry Andric 1243fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1244fe6060f1SDimitry Andric /* ========================================================================== 1245fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vcmp.eq(Vu32.b,Vv32.b) 1246fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1247fe6060f1SDimitry Andric Instruction Type: CVI_VA 1248fe6060f1SDimitry Andric Execution Slots: SLOT0123 1249fe6060f1SDimitry Andric ========================================================================== */ 1250fe6060f1SDimitry Andric 1251*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1252fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1253fe6060f1SDimitry Andric 1254fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1255fe6060f1SDimitry Andric /* ========================================================================== 1256fe6060f1SDimitry Andric Assembly Syntax: Qx4^=vcmp.eq(Vu32.b,Vv32.b) 1257fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1258fe6060f1SDimitry Andric Instruction Type: CVI_VA 1259fe6060f1SDimitry Andric Execution Slots: SLOT0123 1260fe6060f1SDimitry Andric ========================================================================== */ 1261fe6060f1SDimitry Andric 1262*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1263fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1264fe6060f1SDimitry Andric 1265fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1266fe6060f1SDimitry Andric /* ========================================================================== 1267fe6060f1SDimitry Andric Assembly Syntax: Qd4=vcmp.eq(Vu32.h,Vv32.h) 1268fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv) 1269fe6060f1SDimitry Andric Instruction Type: CVI_VA 1270fe6060f1SDimitry Andric Execution Slots: SLOT0123 1271fe6060f1SDimitry Andric ========================================================================== */ 1272fe6060f1SDimitry Andric 1273*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1) 1274fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1275fe6060f1SDimitry Andric 1276fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1277fe6060f1SDimitry Andric /* ========================================================================== 1278fe6060f1SDimitry Andric Assembly Syntax: Qx4&=vcmp.eq(Vu32.h,Vv32.h) 1279fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1280fe6060f1SDimitry Andric Instruction Type: CVI_VA 1281fe6060f1SDimitry Andric Execution Slots: SLOT0123 1282fe6060f1SDimitry Andric ========================================================================== */ 1283fe6060f1SDimitry Andric 1284*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1285fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1286fe6060f1SDimitry Andric 1287fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1288fe6060f1SDimitry Andric /* ========================================================================== 1289fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vcmp.eq(Vu32.h,Vv32.h) 1290fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1291fe6060f1SDimitry Andric Instruction Type: CVI_VA 1292fe6060f1SDimitry Andric Execution Slots: SLOT0123 1293fe6060f1SDimitry Andric ========================================================================== */ 1294fe6060f1SDimitry Andric 1295*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1296fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1297fe6060f1SDimitry Andric 1298fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1299fe6060f1SDimitry Andric /* ========================================================================== 1300fe6060f1SDimitry Andric Assembly Syntax: Qx4^=vcmp.eq(Vu32.h,Vv32.h) 1301fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1302fe6060f1SDimitry Andric Instruction Type: CVI_VA 1303fe6060f1SDimitry Andric Execution Slots: SLOT0123 1304fe6060f1SDimitry Andric ========================================================================== */ 1305fe6060f1SDimitry Andric 1306*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1307fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1308fe6060f1SDimitry Andric 1309fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1310fe6060f1SDimitry Andric /* ========================================================================== 1311fe6060f1SDimitry Andric Assembly Syntax: Qd4=vcmp.eq(Vu32.w,Vv32.w) 1312fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv) 1313fe6060f1SDimitry Andric Instruction Type: CVI_VA 1314fe6060f1SDimitry Andric Execution Slots: SLOT0123 1315fe6060f1SDimitry Andric ========================================================================== */ 1316fe6060f1SDimitry Andric 1317*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1) 1318fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1319fe6060f1SDimitry Andric 1320fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1321fe6060f1SDimitry Andric /* ========================================================================== 1322fe6060f1SDimitry Andric Assembly Syntax: Qx4&=vcmp.eq(Vu32.w,Vv32.w) 1323fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1324fe6060f1SDimitry Andric Instruction Type: CVI_VA 1325fe6060f1SDimitry Andric Execution Slots: SLOT0123 1326fe6060f1SDimitry Andric ========================================================================== */ 1327fe6060f1SDimitry Andric 1328*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1329fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1330fe6060f1SDimitry Andric 1331fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1332fe6060f1SDimitry Andric /* ========================================================================== 1333fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vcmp.eq(Vu32.w,Vv32.w) 1334fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1335fe6060f1SDimitry Andric Instruction Type: CVI_VA 1336fe6060f1SDimitry Andric Execution Slots: SLOT0123 1337fe6060f1SDimitry Andric ========================================================================== */ 1338fe6060f1SDimitry Andric 1339*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1340fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1341fe6060f1SDimitry Andric 1342fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1343fe6060f1SDimitry Andric /* ========================================================================== 1344fe6060f1SDimitry Andric Assembly Syntax: Qx4^=vcmp.eq(Vu32.w,Vv32.w) 1345fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1346fe6060f1SDimitry Andric Instruction Type: CVI_VA 1347fe6060f1SDimitry Andric Execution Slots: SLOT0123 1348fe6060f1SDimitry Andric ========================================================================== */ 1349fe6060f1SDimitry Andric 1350*0eae32dcSDimitry Andric #define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1351fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1352fe6060f1SDimitry Andric 1353fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1354fe6060f1SDimitry Andric /* ========================================================================== 1355fe6060f1SDimitry Andric Assembly Syntax: Qd4=vcmp.gt(Vu32.b,Vv32.b) 1356fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv) 1357fe6060f1SDimitry Andric Instruction Type: CVI_VA 1358fe6060f1SDimitry Andric Execution Slots: SLOT0123 1359fe6060f1SDimitry Andric ========================================================================== */ 1360fe6060f1SDimitry Andric 1361*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1) 1362fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1363fe6060f1SDimitry Andric 1364fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1365fe6060f1SDimitry Andric /* ========================================================================== 1366fe6060f1SDimitry Andric Assembly Syntax: Qx4&=vcmp.gt(Vu32.b,Vv32.b) 1367fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1368fe6060f1SDimitry Andric Instruction Type: CVI_VA 1369fe6060f1SDimitry Andric Execution Slots: SLOT0123 1370fe6060f1SDimitry Andric ========================================================================== */ 1371fe6060f1SDimitry Andric 1372*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1373fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1374fe6060f1SDimitry Andric 1375fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1376fe6060f1SDimitry Andric /* ========================================================================== 1377fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vcmp.gt(Vu32.b,Vv32.b) 1378fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1379fe6060f1SDimitry Andric Instruction Type: CVI_VA 1380fe6060f1SDimitry Andric Execution Slots: SLOT0123 1381fe6060f1SDimitry Andric ========================================================================== */ 1382fe6060f1SDimitry Andric 1383*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1384fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1385fe6060f1SDimitry Andric 1386fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1387fe6060f1SDimitry Andric /* ========================================================================== 1388fe6060f1SDimitry Andric Assembly Syntax: Qx4^=vcmp.gt(Vu32.b,Vv32.b) 1389fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1390fe6060f1SDimitry Andric Instruction Type: CVI_VA 1391fe6060f1SDimitry Andric Execution Slots: SLOT0123 1392fe6060f1SDimitry Andric ========================================================================== */ 1393fe6060f1SDimitry Andric 1394*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1395fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1396fe6060f1SDimitry Andric 1397fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1398fe6060f1SDimitry Andric /* ========================================================================== 1399fe6060f1SDimitry Andric Assembly Syntax: Qd4=vcmp.gt(Vu32.h,Vv32.h) 1400fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv) 1401fe6060f1SDimitry Andric Instruction Type: CVI_VA 1402fe6060f1SDimitry Andric Execution Slots: SLOT0123 1403fe6060f1SDimitry Andric ========================================================================== */ 1404fe6060f1SDimitry Andric 1405*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1) 1406fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1407fe6060f1SDimitry Andric 1408fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1409fe6060f1SDimitry Andric /* ========================================================================== 1410fe6060f1SDimitry Andric Assembly Syntax: Qx4&=vcmp.gt(Vu32.h,Vv32.h) 1411fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1412fe6060f1SDimitry Andric Instruction Type: CVI_VA 1413fe6060f1SDimitry Andric Execution Slots: SLOT0123 1414fe6060f1SDimitry Andric ========================================================================== */ 1415fe6060f1SDimitry Andric 1416*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1417fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1418fe6060f1SDimitry Andric 1419fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1420fe6060f1SDimitry Andric /* ========================================================================== 1421fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vcmp.gt(Vu32.h,Vv32.h) 1422fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1423fe6060f1SDimitry Andric Instruction Type: CVI_VA 1424fe6060f1SDimitry Andric Execution Slots: SLOT0123 1425fe6060f1SDimitry Andric ========================================================================== */ 1426fe6060f1SDimitry Andric 1427*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1428fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1429fe6060f1SDimitry Andric 1430fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1431fe6060f1SDimitry Andric /* ========================================================================== 1432fe6060f1SDimitry Andric Assembly Syntax: Qx4^=vcmp.gt(Vu32.h,Vv32.h) 1433fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1434fe6060f1SDimitry Andric Instruction Type: CVI_VA 1435fe6060f1SDimitry Andric Execution Slots: SLOT0123 1436fe6060f1SDimitry Andric ========================================================================== */ 1437fe6060f1SDimitry Andric 1438*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1439fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1440fe6060f1SDimitry Andric 1441fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1442fe6060f1SDimitry Andric /* ========================================================================== 1443fe6060f1SDimitry Andric Assembly Syntax: Qd4=vcmp.gt(Vu32.ub,Vv32.ub) 1444fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv) 1445fe6060f1SDimitry Andric Instruction Type: CVI_VA 1446fe6060f1SDimitry Andric Execution Slots: SLOT0123 1447fe6060f1SDimitry Andric ========================================================================== */ 1448fe6060f1SDimitry Andric 1449*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1) 1450fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1451fe6060f1SDimitry Andric 1452fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1453fe6060f1SDimitry Andric /* ========================================================================== 1454fe6060f1SDimitry Andric Assembly Syntax: Qx4&=vcmp.gt(Vu32.ub,Vv32.ub) 1455fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1456fe6060f1SDimitry Andric Instruction Type: CVI_VA 1457fe6060f1SDimitry Andric Execution Slots: SLOT0123 1458fe6060f1SDimitry Andric ========================================================================== */ 1459fe6060f1SDimitry Andric 1460*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1461fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1462fe6060f1SDimitry Andric 1463fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1464fe6060f1SDimitry Andric /* ========================================================================== 1465fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vcmp.gt(Vu32.ub,Vv32.ub) 1466fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1467fe6060f1SDimitry Andric Instruction Type: CVI_VA 1468fe6060f1SDimitry Andric Execution Slots: SLOT0123 1469fe6060f1SDimitry Andric ========================================================================== */ 1470fe6060f1SDimitry Andric 1471*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1472fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1473fe6060f1SDimitry Andric 1474fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1475fe6060f1SDimitry Andric /* ========================================================================== 1476fe6060f1SDimitry Andric Assembly Syntax: Qx4^=vcmp.gt(Vu32.ub,Vv32.ub) 1477fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1478fe6060f1SDimitry Andric Instruction Type: CVI_VA 1479fe6060f1SDimitry Andric Execution Slots: SLOT0123 1480fe6060f1SDimitry Andric ========================================================================== */ 1481fe6060f1SDimitry Andric 1482*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1483fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1484fe6060f1SDimitry Andric 1485fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1486fe6060f1SDimitry Andric /* ========================================================================== 1487fe6060f1SDimitry Andric Assembly Syntax: Qd4=vcmp.gt(Vu32.uh,Vv32.uh) 1488fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) 1489fe6060f1SDimitry Andric Instruction Type: CVI_VA 1490fe6060f1SDimitry Andric Execution Slots: SLOT0123 1491fe6060f1SDimitry Andric ========================================================================== */ 1492fe6060f1SDimitry Andric 1493*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1) 1494fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1495fe6060f1SDimitry Andric 1496fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1497fe6060f1SDimitry Andric /* ========================================================================== 1498fe6060f1SDimitry Andric Assembly Syntax: Qx4&=vcmp.gt(Vu32.uh,Vv32.uh) 1499fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1500fe6060f1SDimitry Andric Instruction Type: CVI_VA 1501fe6060f1SDimitry Andric Execution Slots: SLOT0123 1502fe6060f1SDimitry Andric ========================================================================== */ 1503fe6060f1SDimitry Andric 1504*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1505fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1506fe6060f1SDimitry Andric 1507fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1508fe6060f1SDimitry Andric /* ========================================================================== 1509fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vcmp.gt(Vu32.uh,Vv32.uh) 1510fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1511fe6060f1SDimitry Andric Instruction Type: CVI_VA 1512fe6060f1SDimitry Andric Execution Slots: SLOT0123 1513fe6060f1SDimitry Andric ========================================================================== */ 1514fe6060f1SDimitry Andric 1515*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1516fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1517fe6060f1SDimitry Andric 1518fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1519fe6060f1SDimitry Andric /* ========================================================================== 1520fe6060f1SDimitry Andric Assembly Syntax: Qx4^=vcmp.gt(Vu32.uh,Vv32.uh) 1521fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1522fe6060f1SDimitry Andric Instruction Type: CVI_VA 1523fe6060f1SDimitry Andric Execution Slots: SLOT0123 1524fe6060f1SDimitry Andric ========================================================================== */ 1525fe6060f1SDimitry Andric 1526*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1527fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1528fe6060f1SDimitry Andric 1529fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1530fe6060f1SDimitry Andric /* ========================================================================== 1531fe6060f1SDimitry Andric Assembly Syntax: Qd4=vcmp.gt(Vu32.uw,Vv32.uw) 1532fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) 1533fe6060f1SDimitry Andric Instruction Type: CVI_VA 1534fe6060f1SDimitry Andric Execution Slots: SLOT0123 1535fe6060f1SDimitry Andric ========================================================================== */ 1536fe6060f1SDimitry Andric 1537*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1) 1538fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1539fe6060f1SDimitry Andric 1540fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1541fe6060f1SDimitry Andric /* ========================================================================== 1542fe6060f1SDimitry Andric Assembly Syntax: Qx4&=vcmp.gt(Vu32.uw,Vv32.uw) 1543fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1544fe6060f1SDimitry Andric Instruction Type: CVI_VA 1545fe6060f1SDimitry Andric Execution Slots: SLOT0123 1546fe6060f1SDimitry Andric ========================================================================== */ 1547fe6060f1SDimitry Andric 1548*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1549fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1550fe6060f1SDimitry Andric 1551fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1552fe6060f1SDimitry Andric /* ========================================================================== 1553fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vcmp.gt(Vu32.uw,Vv32.uw) 1554fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1555fe6060f1SDimitry Andric Instruction Type: CVI_VA 1556fe6060f1SDimitry Andric Execution Slots: SLOT0123 1557fe6060f1SDimitry Andric ========================================================================== */ 1558fe6060f1SDimitry Andric 1559*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1560fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1561fe6060f1SDimitry Andric 1562fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1563fe6060f1SDimitry Andric /* ========================================================================== 1564fe6060f1SDimitry Andric Assembly Syntax: Qx4^=vcmp.gt(Vu32.uw,Vv32.uw) 1565fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1566fe6060f1SDimitry Andric Instruction Type: CVI_VA 1567fe6060f1SDimitry Andric Execution Slots: SLOT0123 1568fe6060f1SDimitry Andric ========================================================================== */ 1569fe6060f1SDimitry Andric 1570*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1571fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1572fe6060f1SDimitry Andric 1573fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1574fe6060f1SDimitry Andric /* ========================================================================== 1575fe6060f1SDimitry Andric Assembly Syntax: Qd4=vcmp.gt(Vu32.w,Vv32.w) 1576fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv) 1577fe6060f1SDimitry Andric Instruction Type: CVI_VA 1578fe6060f1SDimitry Andric Execution Slots: SLOT0123 1579fe6060f1SDimitry Andric ========================================================================== */ 1580fe6060f1SDimitry Andric 1581*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1) 1582fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1583fe6060f1SDimitry Andric 1584fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1585fe6060f1SDimitry Andric /* ========================================================================== 1586fe6060f1SDimitry Andric Assembly Syntax: Qx4&=vcmp.gt(Vu32.w,Vv32.w) 1587fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1588fe6060f1SDimitry Andric Instruction Type: CVI_VA 1589fe6060f1SDimitry Andric Execution Slots: SLOT0123 1590fe6060f1SDimitry Andric ========================================================================== */ 1591fe6060f1SDimitry Andric 1592*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1593fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1594fe6060f1SDimitry Andric 1595fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1596fe6060f1SDimitry Andric /* ========================================================================== 1597fe6060f1SDimitry Andric Assembly Syntax: Qx4|=vcmp.gt(Vu32.w,Vv32.w) 1598fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1599fe6060f1SDimitry Andric Instruction Type: CVI_VA 1600fe6060f1SDimitry Andric Execution Slots: SLOT0123 1601fe6060f1SDimitry Andric ========================================================================== */ 1602fe6060f1SDimitry Andric 1603*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1604fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1605fe6060f1SDimitry Andric 1606fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1607fe6060f1SDimitry Andric /* ========================================================================== 1608fe6060f1SDimitry Andric Assembly Syntax: Qx4^=vcmp.gt(Vu32.w,Vv32.w) 1609fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 1610fe6060f1SDimitry Andric Instruction Type: CVI_VA 1611fe6060f1SDimitry Andric Execution Slots: SLOT0123 1612fe6060f1SDimitry Andric ========================================================================== */ 1613fe6060f1SDimitry Andric 1614*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 1615fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1616fe6060f1SDimitry Andric 1617fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1618fe6060f1SDimitry Andric /* ========================================================================== 1619fe6060f1SDimitry Andric Assembly Syntax: Vx32.w=vinsert(Rt32) 1620fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt) 1621fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 1622fe6060f1SDimitry Andric Execution Slots: SLOT23 1623fe6060f1SDimitry Andric ========================================================================== */ 1624fe6060f1SDimitry Andric 1625*0eae32dcSDimitry Andric #define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt) 1626fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1627fe6060f1SDimitry Andric 1628fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1629fe6060f1SDimitry Andric /* ========================================================================== 1630fe6060f1SDimitry Andric Assembly Syntax: Vd32=vlalign(Vu32,Vv32,Rt8) 1631fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 1632fe6060f1SDimitry Andric Instruction Type: CVI_VP 1633fe6060f1SDimitry Andric Execution Slots: SLOT0123 1634fe6060f1SDimitry Andric ========================================================================== */ 1635fe6060f1SDimitry Andric 1636*0eae32dcSDimitry Andric #define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt) 1637fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1638fe6060f1SDimitry Andric 1639fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1640fe6060f1SDimitry Andric /* ========================================================================== 1641fe6060f1SDimitry Andric Assembly Syntax: Vd32=vlalign(Vu32,Vv32,#u3) 1642fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) 1643fe6060f1SDimitry Andric Instruction Type: CVI_VP 1644fe6060f1SDimitry Andric Execution Slots: SLOT0123 1645fe6060f1SDimitry Andric ========================================================================== */ 1646fe6060f1SDimitry Andric 1647*0eae32dcSDimitry Andric #define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3) 1648fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1649fe6060f1SDimitry Andric 1650fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1651fe6060f1SDimitry Andric /* ========================================================================== 1652fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vlsr(Vu32.uh,Rt32) 1653fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt) 1654fe6060f1SDimitry Andric Instruction Type: CVI_VS 1655fe6060f1SDimitry Andric Execution Slots: SLOT0123 1656fe6060f1SDimitry Andric ========================================================================== */ 1657fe6060f1SDimitry Andric 1658*0eae32dcSDimitry Andric #define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt) 1659fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1660fe6060f1SDimitry Andric 1661fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1662fe6060f1SDimitry Andric /* ========================================================================== 1663fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vlsr(Vu32.h,Vv32.h) 1664fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv) 1665fe6060f1SDimitry Andric Instruction Type: CVI_VS 1666fe6060f1SDimitry Andric Execution Slots: SLOT0123 1667fe6060f1SDimitry Andric ========================================================================== */ 1668fe6060f1SDimitry Andric 1669*0eae32dcSDimitry Andric #define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv) 1670fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1671fe6060f1SDimitry Andric 1672fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1673fe6060f1SDimitry Andric /* ========================================================================== 1674fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vlsr(Vu32.uw,Rt32) 1675fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt) 1676fe6060f1SDimitry Andric Instruction Type: CVI_VS 1677fe6060f1SDimitry Andric Execution Slots: SLOT0123 1678fe6060f1SDimitry Andric ========================================================================== */ 1679fe6060f1SDimitry Andric 1680*0eae32dcSDimitry Andric #define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt) 1681fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1682fe6060f1SDimitry Andric 1683fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1684fe6060f1SDimitry Andric /* ========================================================================== 1685fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vlsr(Vu32.w,Vv32.w) 1686fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv) 1687fe6060f1SDimitry Andric Instruction Type: CVI_VS 1688fe6060f1SDimitry Andric Execution Slots: SLOT0123 1689fe6060f1SDimitry Andric ========================================================================== */ 1690fe6060f1SDimitry Andric 1691*0eae32dcSDimitry Andric #define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv) 1692fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1693fe6060f1SDimitry Andric 1694fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1695fe6060f1SDimitry Andric /* ========================================================================== 1696fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8) 1697fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 1698fe6060f1SDimitry Andric Instruction Type: CVI_VP 1699fe6060f1SDimitry Andric Execution Slots: SLOT0123 1700fe6060f1SDimitry Andric ========================================================================== */ 1701fe6060f1SDimitry Andric 1702*0eae32dcSDimitry Andric #define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt) 1703fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1704fe6060f1SDimitry Andric 1705fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1706fe6060f1SDimitry Andric /* ========================================================================== 1707fe6060f1SDimitry Andric Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8) 1708fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 1709fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 1710fe6060f1SDimitry Andric Execution Slots: SLOT0123 1711fe6060f1SDimitry Andric ========================================================================== */ 1712fe6060f1SDimitry Andric 1713*0eae32dcSDimitry Andric #define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt) 1714fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1715fe6060f1SDimitry Andric 1716fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1717fe6060f1SDimitry Andric /* ========================================================================== 1718fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8) 1719fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 1720fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 1721fe6060f1SDimitry Andric Execution Slots: SLOT0123 1722fe6060f1SDimitry Andric ========================================================================== */ 1723fe6060f1SDimitry Andric 1724*0eae32dcSDimitry Andric #define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt) 1725fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1726fe6060f1SDimitry Andric 1727fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1728fe6060f1SDimitry Andric /* ========================================================================== 1729fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8) 1730fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 1731fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 1732fe6060f1SDimitry Andric Execution Slots: SLOT0123 1733fe6060f1SDimitry Andric ========================================================================== */ 1734fe6060f1SDimitry Andric 1735*0eae32dcSDimitry Andric #define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt) 1736fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1737fe6060f1SDimitry Andric 1738fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1739fe6060f1SDimitry Andric /* ========================================================================== 1740fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vmax(Vu32.h,Vv32.h) 1741fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv) 1742fe6060f1SDimitry Andric Instruction Type: CVI_VA 1743fe6060f1SDimitry Andric Execution Slots: SLOT0123 1744fe6060f1SDimitry Andric ========================================================================== */ 1745fe6060f1SDimitry Andric 1746*0eae32dcSDimitry Andric #define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv) 1747fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1748fe6060f1SDimitry Andric 1749fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1750fe6060f1SDimitry Andric /* ========================================================================== 1751fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vmax(Vu32.ub,Vv32.ub) 1752fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv) 1753fe6060f1SDimitry Andric Instruction Type: CVI_VA 1754fe6060f1SDimitry Andric Execution Slots: SLOT0123 1755fe6060f1SDimitry Andric ========================================================================== */ 1756fe6060f1SDimitry Andric 1757*0eae32dcSDimitry Andric #define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv) 1758fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1759fe6060f1SDimitry Andric 1760fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1761fe6060f1SDimitry Andric /* ========================================================================== 1762fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vmax(Vu32.uh,Vv32.uh) 1763fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) 1764fe6060f1SDimitry Andric Instruction Type: CVI_VA 1765fe6060f1SDimitry Andric Execution Slots: SLOT0123 1766fe6060f1SDimitry Andric ========================================================================== */ 1767fe6060f1SDimitry Andric 1768*0eae32dcSDimitry Andric #define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv) 1769fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1770fe6060f1SDimitry Andric 1771fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1772fe6060f1SDimitry Andric /* ========================================================================== 1773fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmax(Vu32.w,Vv32.w) 1774fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv) 1775fe6060f1SDimitry Andric Instruction Type: CVI_VA 1776fe6060f1SDimitry Andric Execution Slots: SLOT0123 1777fe6060f1SDimitry Andric ========================================================================== */ 1778fe6060f1SDimitry Andric 1779*0eae32dcSDimitry Andric #define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv) 1780fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1781fe6060f1SDimitry Andric 1782fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1783fe6060f1SDimitry Andric /* ========================================================================== 1784fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vmin(Vu32.h,Vv32.h) 1785fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv) 1786fe6060f1SDimitry Andric Instruction Type: CVI_VA 1787fe6060f1SDimitry Andric Execution Slots: SLOT0123 1788fe6060f1SDimitry Andric ========================================================================== */ 1789fe6060f1SDimitry Andric 1790*0eae32dcSDimitry Andric #define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv) 1791fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1792fe6060f1SDimitry Andric 1793fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1794fe6060f1SDimitry Andric /* ========================================================================== 1795fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vmin(Vu32.ub,Vv32.ub) 1796fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv) 1797fe6060f1SDimitry Andric Instruction Type: CVI_VA 1798fe6060f1SDimitry Andric Execution Slots: SLOT0123 1799fe6060f1SDimitry Andric ========================================================================== */ 1800fe6060f1SDimitry Andric 1801*0eae32dcSDimitry Andric #define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv) 1802fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1803fe6060f1SDimitry Andric 1804fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1805fe6060f1SDimitry Andric /* ========================================================================== 1806fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vmin(Vu32.uh,Vv32.uh) 1807fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) 1808fe6060f1SDimitry Andric Instruction Type: CVI_VA 1809fe6060f1SDimitry Andric Execution Slots: SLOT0123 1810fe6060f1SDimitry Andric ========================================================================== */ 1811fe6060f1SDimitry Andric 1812*0eae32dcSDimitry Andric #define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv) 1813fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1814fe6060f1SDimitry Andric 1815fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1816fe6060f1SDimitry Andric /* ========================================================================== 1817fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmin(Vu32.w,Vv32.w) 1818fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv) 1819fe6060f1SDimitry Andric Instruction Type: CVI_VA 1820fe6060f1SDimitry Andric Execution Slots: SLOT0123 1821fe6060f1SDimitry Andric ========================================================================== */ 1822fe6060f1SDimitry Andric 1823*0eae32dcSDimitry Andric #define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv) 1824fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1825fe6060f1SDimitry Andric 1826fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1827fe6060f1SDimitry Andric /* ========================================================================== 1828fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.b) 1829fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt) 1830fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1831fe6060f1SDimitry Andric Execution Slots: SLOT23 1832fe6060f1SDimitry Andric ========================================================================== */ 1833fe6060f1SDimitry Andric 1834*0eae32dcSDimitry Andric #define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt) 1835fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1836fe6060f1SDimitry Andric 1837fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1838fe6060f1SDimitry Andric /* ========================================================================== 1839fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.b) 1840fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 1841fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1842fe6060f1SDimitry Andric Execution Slots: SLOT23 1843fe6060f1SDimitry Andric ========================================================================== */ 1844fe6060f1SDimitry Andric 1845*0eae32dcSDimitry Andric #define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt) 1846fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1847fe6060f1SDimitry Andric 1848fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1849fe6060f1SDimitry Andric /* ========================================================================== 1850fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.b) 1851fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 1852fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1853fe6060f1SDimitry Andric Execution Slots: SLOT23 1854fe6060f1SDimitry Andric ========================================================================== */ 1855fe6060f1SDimitry Andric 1856*0eae32dcSDimitry Andric #define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv) 1857fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1858fe6060f1SDimitry Andric 1859fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1860fe6060f1SDimitry Andric /* ========================================================================== 1861fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub) 1862fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 1863fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1864fe6060f1SDimitry Andric Execution Slots: SLOT23 1865fe6060f1SDimitry Andric ========================================================================== */ 1866fe6060f1SDimitry Andric 1867*0eae32dcSDimitry Andric #define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv) 1868fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1869fe6060f1SDimitry Andric 1870fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1871fe6060f1SDimitry Andric /* ========================================================================== 1872fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vmpa(Vuu32.h,Rt32.b) 1873fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt) 1874fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1875fe6060f1SDimitry Andric Execution Slots: SLOT23 1876fe6060f1SDimitry Andric ========================================================================== */ 1877fe6060f1SDimitry Andric 1878*0eae32dcSDimitry Andric #define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt) 1879fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1880fe6060f1SDimitry Andric 1881fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1882fe6060f1SDimitry Andric /* ========================================================================== 1883fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vmpa(Vuu32.h,Rt32.b) 1884fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 1885fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1886fe6060f1SDimitry Andric Execution Slots: SLOT23 1887fe6060f1SDimitry Andric ========================================================================== */ 1888fe6060f1SDimitry Andric 1889*0eae32dcSDimitry Andric #define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt) 1890fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1891fe6060f1SDimitry Andric 1892fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1893fe6060f1SDimitry Andric /* ========================================================================== 1894fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Rt32.b) 1895fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt) 1896fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1897fe6060f1SDimitry Andric Execution Slots: SLOT23 1898fe6060f1SDimitry Andric ========================================================================== */ 1899fe6060f1SDimitry Andric 1900*0eae32dcSDimitry Andric #define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt) 1901fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1902fe6060f1SDimitry Andric 1903fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1904fe6060f1SDimitry Andric /* ========================================================================== 1905fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Rt32.b) 1906fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) 1907fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1908fe6060f1SDimitry Andric Execution Slots: SLOT23 1909fe6060f1SDimitry Andric ========================================================================== */ 1910fe6060f1SDimitry Andric 1911*0eae32dcSDimitry Andric #define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt) 1912fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1913fe6060f1SDimitry Andric 1914fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1915fe6060f1SDimitry Andric /* ========================================================================== 1916fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Vv32.b) 1917fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) 1918fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1919fe6060f1SDimitry Andric Execution Slots: SLOT23 1920fe6060f1SDimitry Andric ========================================================================== */ 1921fe6060f1SDimitry Andric 1922*0eae32dcSDimitry Andric #define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv) 1923fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1924fe6060f1SDimitry Andric 1925fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1926fe6060f1SDimitry Andric /* ========================================================================== 1927fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Vv32.b) 1928fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 1929fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1930fe6060f1SDimitry Andric Execution Slots: SLOT23 1931fe6060f1SDimitry Andric ========================================================================== */ 1932fe6060f1SDimitry Andric 1933*0eae32dcSDimitry Andric #define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv) 1934fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1935fe6060f1SDimitry Andric 1936fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1937fe6060f1SDimitry Andric /* ========================================================================== 1938fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vmpy(Vu32.b,Vv32.b) 1939fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) 1940fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1941fe6060f1SDimitry Andric Execution Slots: SLOT23 1942fe6060f1SDimitry Andric ========================================================================== */ 1943fe6060f1SDimitry Andric 1944*0eae32dcSDimitry Andric #define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv) 1945fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1946fe6060f1SDimitry Andric 1947fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1948fe6060f1SDimitry Andric /* ========================================================================== 1949fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h+=vmpy(Vu32.b,Vv32.b) 1950fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 1951fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1952fe6060f1SDimitry Andric Execution Slots: SLOT23 1953fe6060f1SDimitry Andric ========================================================================== */ 1954fe6060f1SDimitry Andric 1955*0eae32dcSDimitry Andric #define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv) 1956fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1957fe6060f1SDimitry Andric 1958fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1959fe6060f1SDimitry Andric /* ========================================================================== 1960fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmpye(Vu32.w,Vv32.uh) 1961fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) 1962fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1963fe6060f1SDimitry Andric Execution Slots: SLOT23 1964fe6060f1SDimitry Andric ========================================================================== */ 1965fe6060f1SDimitry Andric 1966*0eae32dcSDimitry Andric #define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv) 1967fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1968fe6060f1SDimitry Andric 1969fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1970fe6060f1SDimitry Andric /* ========================================================================== 1971fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Rt32.h) 1972fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt) 1973fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1974fe6060f1SDimitry Andric Execution Slots: SLOT23 1975fe6060f1SDimitry Andric ========================================================================== */ 1976fe6060f1SDimitry Andric 1977*0eae32dcSDimitry Andric #define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt) 1978fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1979fe6060f1SDimitry Andric 1980fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1981fe6060f1SDimitry Andric /* ========================================================================== 1982fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat 1983fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) 1984fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 1985fe6060f1SDimitry Andric Execution Slots: SLOT23 1986fe6060f1SDimitry Andric ========================================================================== */ 1987fe6060f1SDimitry Andric 1988*0eae32dcSDimitry Andric #define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt) 1989fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 1990fe6060f1SDimitry Andric 1991fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 1992fe6060f1SDimitry Andric /* ========================================================================== 1993fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat 1994fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt) 1995*0eae32dcSDimitry Andric Instruction Type: CVI_VX 1996fe6060f1SDimitry Andric Execution Slots: SLOT23 1997fe6060f1SDimitry Andric ========================================================================== */ 1998fe6060f1SDimitry Andric 1999*0eae32dcSDimitry Andric #define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt) 2000fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2001fe6060f1SDimitry Andric 2002fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2003fe6060f1SDimitry Andric /* ========================================================================== 2004fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat 2005fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt) 2006*0eae32dcSDimitry Andric Instruction Type: CVI_VX 2007fe6060f1SDimitry Andric Execution Slots: SLOT23 2008fe6060f1SDimitry Andric ========================================================================== */ 2009fe6060f1SDimitry Andric 2010*0eae32dcSDimitry Andric #define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt) 2011fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2012fe6060f1SDimitry Andric 2013fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2014fe6060f1SDimitry Andric /* ========================================================================== 2015fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.uh) 2016fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv) 2017fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2018fe6060f1SDimitry Andric Execution Slots: SLOT23 2019fe6060f1SDimitry Andric ========================================================================== */ 2020fe6060f1SDimitry Andric 2021*0eae32dcSDimitry Andric #define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv) 2022fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2023fe6060f1SDimitry Andric 2024fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2025fe6060f1SDimitry Andric /* ========================================================================== 2026fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.uh) 2027fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 2028fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2029fe6060f1SDimitry Andric Execution Slots: SLOT23 2030fe6060f1SDimitry Andric ========================================================================== */ 2031fe6060f1SDimitry Andric 2032*0eae32dcSDimitry Andric #define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv) 2033fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2034fe6060f1SDimitry Andric 2035fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2036fe6060f1SDimitry Andric /* ========================================================================== 2037fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.h) 2038fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2039fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2040fe6060f1SDimitry Andric Execution Slots: SLOT23 2041fe6060f1SDimitry Andric ========================================================================== */ 2042fe6060f1SDimitry Andric 2043*0eae32dcSDimitry Andric #define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv) 2044fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2045fe6060f1SDimitry Andric 2046fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2047fe6060f1SDimitry Andric /* ========================================================================== 2048fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.h) 2049fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 2050fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2051fe6060f1SDimitry Andric Execution Slots: SLOT23 2052fe6060f1SDimitry Andric ========================================================================== */ 2053fe6060f1SDimitry Andric 2054*0eae32dcSDimitry Andric #define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv) 2055fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2056fe6060f1SDimitry Andric 2057fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2058fe6060f1SDimitry Andric /* ========================================================================== 2059fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat 2060fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) 2061*0eae32dcSDimitry Andric Instruction Type: CVI_VX 2062fe6060f1SDimitry Andric Execution Slots: SLOT23 2063fe6060f1SDimitry Andric ========================================================================== */ 2064fe6060f1SDimitry Andric 2065*0eae32dcSDimitry Andric #define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv) 2066fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2067fe6060f1SDimitry Andric 2068fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2069fe6060f1SDimitry Andric /* ========================================================================== 2070fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmpyieo(Vu32.h,Vv32.h) 2071fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2072fe6060f1SDimitry Andric Instruction Type: CVI_VX 2073fe6060f1SDimitry Andric Execution Slots: SLOT23 2074fe6060f1SDimitry Andric ========================================================================== */ 2075fe6060f1SDimitry Andric 2076*0eae32dcSDimitry Andric #define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv) 2077fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2078fe6060f1SDimitry Andric 2079fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2080fe6060f1SDimitry Andric /* ========================================================================== 2081fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.h) 2082fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 2083fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2084fe6060f1SDimitry Andric Execution Slots: SLOT23 2085fe6060f1SDimitry Andric ========================================================================== */ 2086fe6060f1SDimitry Andric 2087*0eae32dcSDimitry Andric #define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv) 2088fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2089fe6060f1SDimitry Andric 2090fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2091fe6060f1SDimitry Andric /* ========================================================================== 2092fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmpyie(Vu32.w,Vv32.uh) 2093fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv) 2094fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2095fe6060f1SDimitry Andric Execution Slots: SLOT23 2096fe6060f1SDimitry Andric ========================================================================== */ 2097fe6060f1SDimitry Andric 2098*0eae32dcSDimitry Andric #define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv) 2099fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2100fe6060f1SDimitry Andric 2101fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2102fe6060f1SDimitry Andric /* ========================================================================== 2103fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.uh) 2104fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 2105fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2106fe6060f1SDimitry Andric Execution Slots: SLOT23 2107fe6060f1SDimitry Andric ========================================================================== */ 2108fe6060f1SDimitry Andric 2109*0eae32dcSDimitry Andric #define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv) 2110fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2111fe6060f1SDimitry Andric 2112fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2113fe6060f1SDimitry Andric /* ========================================================================== 2114fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Vv32.h) 2115fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2116fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2117fe6060f1SDimitry Andric Execution Slots: SLOT23 2118fe6060f1SDimitry Andric ========================================================================== */ 2119fe6060f1SDimitry Andric 2120*0eae32dcSDimitry Andric #define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv) 2121fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2122fe6060f1SDimitry Andric 2123fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2124fe6060f1SDimitry Andric /* ========================================================================== 2125fe6060f1SDimitry Andric Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Vv32.h) 2126fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 2127fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2128fe6060f1SDimitry Andric Execution Slots: SLOT23 2129fe6060f1SDimitry Andric ========================================================================== */ 2130fe6060f1SDimitry Andric 2131*0eae32dcSDimitry Andric #define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv) 2132fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2133fe6060f1SDimitry Andric 2134fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2135fe6060f1SDimitry Andric /* ========================================================================== 2136fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Rt32.b) 2137fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt) 2138fe6060f1SDimitry Andric Instruction Type: CVI_VX 2139fe6060f1SDimitry Andric Execution Slots: SLOT23 2140fe6060f1SDimitry Andric ========================================================================== */ 2141fe6060f1SDimitry Andric 2142*0eae32dcSDimitry Andric #define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt) 2143fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2144fe6060f1SDimitry Andric 2145fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2146fe6060f1SDimitry Andric /* ========================================================================== 2147fe6060f1SDimitry Andric Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Rt32.b) 2148fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 2149fe6060f1SDimitry Andric Instruction Type: CVI_VX 2150fe6060f1SDimitry Andric Execution Slots: SLOT23 2151fe6060f1SDimitry Andric ========================================================================== */ 2152fe6060f1SDimitry Andric 2153*0eae32dcSDimitry Andric #define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt) 2154fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2155fe6060f1SDimitry Andric 2156fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2157fe6060f1SDimitry Andric /* ========================================================================== 2158fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmpyio(Vu32.w,Vv32.h) 2159fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv) 2160fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2161fe6060f1SDimitry Andric Execution Slots: SLOT23 2162fe6060f1SDimitry Andric ========================================================================== */ 2163fe6060f1SDimitry Andric 2164*0eae32dcSDimitry Andric #define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv) 2165fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2166fe6060f1SDimitry Andric 2167fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2168fe6060f1SDimitry Andric /* ========================================================================== 2169fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.b) 2170fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt) 2171fe6060f1SDimitry Andric Instruction Type: CVI_VX 2172fe6060f1SDimitry Andric Execution Slots: SLOT23 2173fe6060f1SDimitry Andric ========================================================================== */ 2174fe6060f1SDimitry Andric 2175*0eae32dcSDimitry Andric #define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt) 2176fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2177fe6060f1SDimitry Andric 2178fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2179fe6060f1SDimitry Andric /* ========================================================================== 2180fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.b) 2181fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 2182fe6060f1SDimitry Andric Instruction Type: CVI_VX 2183fe6060f1SDimitry Andric Execution Slots: SLOT23 2184fe6060f1SDimitry Andric ========================================================================== */ 2185fe6060f1SDimitry Andric 2186*0eae32dcSDimitry Andric #define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt) 2187fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2188fe6060f1SDimitry Andric 2189fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2190fe6060f1SDimitry Andric /* ========================================================================== 2191fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.h) 2192fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt) 2193fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2194fe6060f1SDimitry Andric Execution Slots: SLOT23 2195fe6060f1SDimitry Andric ========================================================================== */ 2196fe6060f1SDimitry Andric 2197*0eae32dcSDimitry Andric #define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt) 2198fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2199fe6060f1SDimitry Andric 2200fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2201fe6060f1SDimitry Andric /* ========================================================================== 2202fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.h) 2203fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 2204fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2205fe6060f1SDimitry Andric Execution Slots: SLOT23 2206fe6060f1SDimitry Andric ========================================================================== */ 2207fe6060f1SDimitry Andric 2208*0eae32dcSDimitry Andric #define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt) 2209fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2210fe6060f1SDimitry Andric 2211fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2212fe6060f1SDimitry Andric /* ========================================================================== 2213fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat 2214fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv) 2215fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2216fe6060f1SDimitry Andric Execution Slots: SLOT23 2217fe6060f1SDimitry Andric ========================================================================== */ 2218fe6060f1SDimitry Andric 2219*0eae32dcSDimitry Andric #define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv) 2220fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2221fe6060f1SDimitry Andric 2222fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2223fe6060f1SDimitry Andric /* ========================================================================== 2224fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat 2225fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) 2226fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2227fe6060f1SDimitry Andric Execution Slots: SLOT23 2228fe6060f1SDimitry Andric ========================================================================== */ 2229fe6060f1SDimitry Andric 2230*0eae32dcSDimitry Andric #define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv) 2231fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2232fe6060f1SDimitry Andric 2233fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2234fe6060f1SDimitry Andric /* ========================================================================== 2235fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift 2236fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 2237fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2238fe6060f1SDimitry Andric Execution Slots: SLOT23 2239fe6060f1SDimitry Andric ========================================================================== */ 2240fe6060f1SDimitry Andric 2241*0eae32dcSDimitry Andric #define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv) 2242fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2243fe6060f1SDimitry Andric 2244fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2245fe6060f1SDimitry Andric /* ========================================================================== 2246fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift 2247fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 2248fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2249fe6060f1SDimitry Andric Execution Slots: SLOT23 2250fe6060f1SDimitry Andric ========================================================================== */ 2251fe6060f1SDimitry Andric 2252*0eae32dcSDimitry Andric #define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv) 2253fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2254fe6060f1SDimitry Andric 2255fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2256fe6060f1SDimitry Andric /* ========================================================================== 2257fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Rt32.ub) 2258fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt) 2259fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2260fe6060f1SDimitry Andric Execution Slots: SLOT23 2261fe6060f1SDimitry Andric ========================================================================== */ 2262fe6060f1SDimitry Andric 2263*0eae32dcSDimitry Andric #define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt) 2264fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2265fe6060f1SDimitry Andric 2266fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2267fe6060f1SDimitry Andric /* ========================================================================== 2268fe6060f1SDimitry Andric Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub) 2269fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) 2270fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2271fe6060f1SDimitry Andric Execution Slots: SLOT23 2272fe6060f1SDimitry Andric ========================================================================== */ 2273fe6060f1SDimitry Andric 2274*0eae32dcSDimitry Andric #define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt) 2275fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2276fe6060f1SDimitry Andric 2277fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2278fe6060f1SDimitry Andric /* ========================================================================== 2279fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Vv32.ub) 2280fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) 2281fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2282fe6060f1SDimitry Andric Execution Slots: SLOT23 2283fe6060f1SDimitry Andric ========================================================================== */ 2284fe6060f1SDimitry Andric 2285*0eae32dcSDimitry Andric #define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv) 2286fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2287fe6060f1SDimitry Andric 2288fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2289fe6060f1SDimitry Andric /* ========================================================================== 2290fe6060f1SDimitry Andric Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub) 2291fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 2292fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2293fe6060f1SDimitry Andric Execution Slots: SLOT23 2294fe6060f1SDimitry Andric ========================================================================== */ 2295fe6060f1SDimitry Andric 2296*0eae32dcSDimitry Andric #define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv) 2297fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2298fe6060f1SDimitry Andric 2299fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2300fe6060f1SDimitry Andric /* ========================================================================== 2301fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Rt32.uh) 2302fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt) 2303fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2304fe6060f1SDimitry Andric Execution Slots: SLOT23 2305fe6060f1SDimitry Andric ========================================================================== */ 2306fe6060f1SDimitry Andric 2307*0eae32dcSDimitry Andric #define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt) 2308fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2309fe6060f1SDimitry Andric 2310fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2311fe6060f1SDimitry Andric /* ========================================================================== 2312fe6060f1SDimitry Andric Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh) 2313fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) 2314fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2315fe6060f1SDimitry Andric Execution Slots: SLOT23 2316fe6060f1SDimitry Andric ========================================================================== */ 2317fe6060f1SDimitry Andric 2318*0eae32dcSDimitry Andric #define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt) 2319fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2320fe6060f1SDimitry Andric 2321fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2322fe6060f1SDimitry Andric /* ========================================================================== 2323fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Vv32.uh) 2324fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) 2325fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2326fe6060f1SDimitry Andric Execution Slots: SLOT23 2327fe6060f1SDimitry Andric ========================================================================== */ 2328fe6060f1SDimitry Andric 2329*0eae32dcSDimitry Andric #define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv) 2330fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2331fe6060f1SDimitry Andric 2332fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2333fe6060f1SDimitry Andric /* ========================================================================== 2334fe6060f1SDimitry Andric Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh) 2335fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 2336fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2337fe6060f1SDimitry Andric Execution Slots: SLOT23 2338fe6060f1SDimitry Andric ========================================================================== */ 2339fe6060f1SDimitry Andric 2340*0eae32dcSDimitry Andric #define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv) 2341fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2342fe6060f1SDimitry Andric 2343fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2344fe6060f1SDimitry Andric /* ========================================================================== 2345fe6060f1SDimitry Andric Assembly Syntax: Vd32=vmux(Qt4,Vu32,Vv32) 2346fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) 2347fe6060f1SDimitry Andric Instruction Type: CVI_VA 2348fe6060f1SDimitry Andric Execution Slots: SLOT0123 2349fe6060f1SDimitry Andric ========================================================================== */ 2350fe6060f1SDimitry Andric 2351*0eae32dcSDimitry Andric #define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) 2352fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2353fe6060f1SDimitry Andric 2354fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2355fe6060f1SDimitry Andric /* ========================================================================== 2356fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vnavg(Vu32.h,Vv32.h) 2357fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2358fe6060f1SDimitry Andric Instruction Type: CVI_VA 2359fe6060f1SDimitry Andric Execution Slots: SLOT0123 2360fe6060f1SDimitry Andric ========================================================================== */ 2361fe6060f1SDimitry Andric 2362*0eae32dcSDimitry Andric #define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv) 2363fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2364fe6060f1SDimitry Andric 2365fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2366fe6060f1SDimitry Andric /* ========================================================================== 2367fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vnavg(Vu32.ub,Vv32.ub) 2368fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) 2369fe6060f1SDimitry Andric Instruction Type: CVI_VA 2370fe6060f1SDimitry Andric Execution Slots: SLOT0123 2371fe6060f1SDimitry Andric ========================================================================== */ 2372fe6060f1SDimitry Andric 2373*0eae32dcSDimitry Andric #define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv) 2374fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2375fe6060f1SDimitry Andric 2376fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2377fe6060f1SDimitry Andric /* ========================================================================== 2378fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vnavg(Vu32.w,Vv32.w) 2379fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) 2380fe6060f1SDimitry Andric Instruction Type: CVI_VA 2381fe6060f1SDimitry Andric Execution Slots: SLOT0123 2382fe6060f1SDimitry Andric ========================================================================== */ 2383fe6060f1SDimitry Andric 2384*0eae32dcSDimitry Andric #define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv) 2385fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2386fe6060f1SDimitry Andric 2387fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2388fe6060f1SDimitry Andric /* ========================================================================== 2389fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vnormamt(Vu32.h) 2390fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu) 2391fe6060f1SDimitry Andric Instruction Type: CVI_VS 2392fe6060f1SDimitry Andric Execution Slots: SLOT0123 2393fe6060f1SDimitry Andric ========================================================================== */ 2394fe6060f1SDimitry Andric 2395*0eae32dcSDimitry Andric #define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu) 2396fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2397fe6060f1SDimitry Andric 2398fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2399fe6060f1SDimitry Andric /* ========================================================================== 2400fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vnormamt(Vu32.w) 2401fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu) 2402fe6060f1SDimitry Andric Instruction Type: CVI_VS 2403fe6060f1SDimitry Andric Execution Slots: SLOT0123 2404fe6060f1SDimitry Andric ========================================================================== */ 2405fe6060f1SDimitry Andric 2406*0eae32dcSDimitry Andric #define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu) 2407fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2408fe6060f1SDimitry Andric 2409fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2410fe6060f1SDimitry Andric /* ========================================================================== 2411fe6060f1SDimitry Andric Assembly Syntax: Vd32=vnot(Vu32) 2412fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu) 2413fe6060f1SDimitry Andric Instruction Type: CVI_VA 2414fe6060f1SDimitry Andric Execution Slots: SLOT0123 2415fe6060f1SDimitry Andric ========================================================================== */ 2416fe6060f1SDimitry Andric 2417*0eae32dcSDimitry Andric #define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu) 2418fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2419fe6060f1SDimitry Andric 2420fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2421fe6060f1SDimitry Andric /* ========================================================================== 2422fe6060f1SDimitry Andric Assembly Syntax: Vd32=vor(Vu32,Vv32) 2423fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv) 2424fe6060f1SDimitry Andric Instruction Type: CVI_VA 2425fe6060f1SDimitry Andric Execution Slots: SLOT0123 2426fe6060f1SDimitry Andric ========================================================================== */ 2427fe6060f1SDimitry Andric 2428*0eae32dcSDimitry Andric #define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv) 2429fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2430fe6060f1SDimitry Andric 2431fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2432fe6060f1SDimitry Andric /* ========================================================================== 2433fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vpacke(Vu32.h,Vv32.h) 2434fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2435fe6060f1SDimitry Andric Instruction Type: CVI_VP 2436fe6060f1SDimitry Andric Execution Slots: SLOT0123 2437fe6060f1SDimitry Andric ========================================================================== */ 2438fe6060f1SDimitry Andric 2439*0eae32dcSDimitry Andric #define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv) 2440fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2441fe6060f1SDimitry Andric 2442fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2443fe6060f1SDimitry Andric /* ========================================================================== 2444fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vpacke(Vu32.w,Vv32.w) 2445fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv) 2446fe6060f1SDimitry Andric Instruction Type: CVI_VP 2447fe6060f1SDimitry Andric Execution Slots: SLOT0123 2448fe6060f1SDimitry Andric ========================================================================== */ 2449fe6060f1SDimitry Andric 2450*0eae32dcSDimitry Andric #define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv) 2451fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2452fe6060f1SDimitry Andric 2453fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2454fe6060f1SDimitry Andric /* ========================================================================== 2455fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vpack(Vu32.h,Vv32.h):sat 2456fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) 2457fe6060f1SDimitry Andric Instruction Type: CVI_VP 2458fe6060f1SDimitry Andric Execution Slots: SLOT0123 2459fe6060f1SDimitry Andric ========================================================================== */ 2460fe6060f1SDimitry Andric 2461*0eae32dcSDimitry Andric #define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv) 2462fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2463fe6060f1SDimitry Andric 2464fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2465fe6060f1SDimitry Andric /* ========================================================================== 2466fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vpack(Vu32.h,Vv32.h):sat 2467fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) 2468fe6060f1SDimitry Andric Instruction Type: CVI_VP 2469fe6060f1SDimitry Andric Execution Slots: SLOT0123 2470fe6060f1SDimitry Andric ========================================================================== */ 2471fe6060f1SDimitry Andric 2472*0eae32dcSDimitry Andric #define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv) 2473fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2474fe6060f1SDimitry Andric 2475fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2476fe6060f1SDimitry Andric /* ========================================================================== 2477fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vpacko(Vu32.h,Vv32.h) 2478fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2479fe6060f1SDimitry Andric Instruction Type: CVI_VP 2480fe6060f1SDimitry Andric Execution Slots: SLOT0123 2481fe6060f1SDimitry Andric ========================================================================== */ 2482fe6060f1SDimitry Andric 2483*0eae32dcSDimitry Andric #define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv) 2484fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2485fe6060f1SDimitry Andric 2486fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2487fe6060f1SDimitry Andric /* ========================================================================== 2488fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vpacko(Vu32.w,Vv32.w) 2489fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv) 2490fe6060f1SDimitry Andric Instruction Type: CVI_VP 2491fe6060f1SDimitry Andric Execution Slots: SLOT0123 2492fe6060f1SDimitry Andric ========================================================================== */ 2493fe6060f1SDimitry Andric 2494*0eae32dcSDimitry Andric #define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv) 2495fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2496fe6060f1SDimitry Andric 2497fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2498fe6060f1SDimitry Andric /* ========================================================================== 2499fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vpack(Vu32.w,Vv32.w):sat 2500fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) 2501fe6060f1SDimitry Andric Instruction Type: CVI_VP 2502fe6060f1SDimitry Andric Execution Slots: SLOT0123 2503fe6060f1SDimitry Andric ========================================================================== */ 2504fe6060f1SDimitry Andric 2505*0eae32dcSDimitry Andric #define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv) 2506fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2507fe6060f1SDimitry Andric 2508fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2509fe6060f1SDimitry Andric /* ========================================================================== 2510fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vpack(Vu32.w,Vv32.w):sat 2511fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) 2512fe6060f1SDimitry Andric Instruction Type: CVI_VP 2513fe6060f1SDimitry Andric Execution Slots: SLOT0123 2514fe6060f1SDimitry Andric ========================================================================== */ 2515fe6060f1SDimitry Andric 2516*0eae32dcSDimitry Andric #define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv) 2517fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2518fe6060f1SDimitry Andric 2519fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2520fe6060f1SDimitry Andric /* ========================================================================== 2521fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vpopcount(Vu32.h) 2522fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu) 2523fe6060f1SDimitry Andric Instruction Type: CVI_VS 2524fe6060f1SDimitry Andric Execution Slots: SLOT0123 2525fe6060f1SDimitry Andric ========================================================================== */ 2526fe6060f1SDimitry Andric 2527*0eae32dcSDimitry Andric #define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu) 2528fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2529fe6060f1SDimitry Andric 2530fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2531fe6060f1SDimitry Andric /* ========================================================================== 2532fe6060f1SDimitry Andric Assembly Syntax: Vd32=vrdelta(Vu32,Vv32) 2533fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv) 2534fe6060f1SDimitry Andric Instruction Type: CVI_VP 2535fe6060f1SDimitry Andric Execution Slots: SLOT0123 2536fe6060f1SDimitry Andric ========================================================================== */ 2537fe6060f1SDimitry Andric 2538*0eae32dcSDimitry Andric #define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv) 2539fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2540fe6060f1SDimitry Andric 2541fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2542fe6060f1SDimitry Andric /* ========================================================================== 2543fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Rt32.b) 2544fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt) 2545fe6060f1SDimitry Andric Instruction Type: CVI_VX 2546fe6060f1SDimitry Andric Execution Slots: SLOT23 2547fe6060f1SDimitry Andric ========================================================================== */ 2548fe6060f1SDimitry Andric 2549*0eae32dcSDimitry Andric #define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt) 2550fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2551fe6060f1SDimitry Andric 2552fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2553fe6060f1SDimitry Andric /* ========================================================================== 2554fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Rt32.b) 2555fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 2556fe6060f1SDimitry Andric Instruction Type: CVI_VX 2557fe6060f1SDimitry Andric Execution Slots: SLOT23 2558fe6060f1SDimitry Andric ========================================================================== */ 2559fe6060f1SDimitry Andric 2560*0eae32dcSDimitry Andric #define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt) 2561fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2562fe6060f1SDimitry Andric 2563fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2564fe6060f1SDimitry Andric /* ========================================================================== 2565fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1) 2566fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) 2567fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2568fe6060f1SDimitry Andric Execution Slots: SLOT23 2569fe6060f1SDimitry Andric ========================================================================== */ 2570fe6060f1SDimitry Andric 2571*0eae32dcSDimitry Andric #define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1) 2572fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2573fe6060f1SDimitry Andric 2574fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2575fe6060f1SDimitry Andric /* ========================================================================== 2576fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1) 2577fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) 2578fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2579fe6060f1SDimitry Andric Execution Slots: SLOT23 2580fe6060f1SDimitry Andric ========================================================================== */ 2581fe6060f1SDimitry Andric 2582*0eae32dcSDimitry Andric #define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1) 2583fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2584fe6060f1SDimitry Andric 2585fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2586fe6060f1SDimitry Andric /* ========================================================================== 2587fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Vv32.b) 2588fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) 2589fe6060f1SDimitry Andric Instruction Type: CVI_VX 2590fe6060f1SDimitry Andric Execution Slots: SLOT23 2591fe6060f1SDimitry Andric ========================================================================== */ 2592fe6060f1SDimitry Andric 2593*0eae32dcSDimitry Andric #define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv) 2594fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2595fe6060f1SDimitry Andric 2596fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2597fe6060f1SDimitry Andric /* ========================================================================== 2598fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b) 2599fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 2600*0eae32dcSDimitry Andric Instruction Type: CVI_VX 2601fe6060f1SDimitry Andric Execution Slots: SLOT23 2602fe6060f1SDimitry Andric ========================================================================== */ 2603fe6060f1SDimitry Andric 2604*0eae32dcSDimitry Andric #define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv) 2605fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2606fe6060f1SDimitry Andric 2607fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2608fe6060f1SDimitry Andric /* ========================================================================== 2609fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vrmpy(Vu32.b,Vv32.b) 2610fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) 2611fe6060f1SDimitry Andric Instruction Type: CVI_VX 2612fe6060f1SDimitry Andric Execution Slots: SLOT23 2613fe6060f1SDimitry Andric ========================================================================== */ 2614fe6060f1SDimitry Andric 2615*0eae32dcSDimitry Andric #define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv) 2616fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2617fe6060f1SDimitry Andric 2618fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2619fe6060f1SDimitry Andric /* ========================================================================== 2620fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b) 2621fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 2622*0eae32dcSDimitry Andric Instruction Type: CVI_VX 2623fe6060f1SDimitry Andric Execution Slots: SLOT23 2624fe6060f1SDimitry Andric ========================================================================== */ 2625fe6060f1SDimitry Andric 2626*0eae32dcSDimitry Andric #define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv) 2627fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2628fe6060f1SDimitry Andric 2629fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2630fe6060f1SDimitry Andric /* ========================================================================== 2631fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Rt32.ub) 2632fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt) 2633fe6060f1SDimitry Andric Instruction Type: CVI_VX 2634fe6060f1SDimitry Andric Execution Slots: SLOT23 2635fe6060f1SDimitry Andric ========================================================================== */ 2636fe6060f1SDimitry Andric 2637*0eae32dcSDimitry Andric #define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt) 2638fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2639fe6060f1SDimitry Andric 2640fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2641fe6060f1SDimitry Andric /* ========================================================================== 2642fe6060f1SDimitry Andric Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub) 2643fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 2644fe6060f1SDimitry Andric Instruction Type: CVI_VX 2645fe6060f1SDimitry Andric Execution Slots: SLOT23 2646fe6060f1SDimitry Andric ========================================================================== */ 2647fe6060f1SDimitry Andric 2648*0eae32dcSDimitry Andric #define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt) 2649fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2650fe6060f1SDimitry Andric 2651fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2652fe6060f1SDimitry Andric /* ========================================================================== 2653fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1) 2654fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) 2655fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2656fe6060f1SDimitry Andric Execution Slots: SLOT23 2657fe6060f1SDimitry Andric ========================================================================== */ 2658fe6060f1SDimitry Andric 2659*0eae32dcSDimitry Andric #define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1) 2660fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2661fe6060f1SDimitry Andric 2662fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2663fe6060f1SDimitry Andric /* ========================================================================== 2664fe6060f1SDimitry Andric Assembly Syntax: Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1) 2665fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) 2666fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2667fe6060f1SDimitry Andric Execution Slots: SLOT23 2668fe6060f1SDimitry Andric ========================================================================== */ 2669fe6060f1SDimitry Andric 2670*0eae32dcSDimitry Andric #define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1) 2671fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2672fe6060f1SDimitry Andric 2673fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2674fe6060f1SDimitry Andric /* ========================================================================== 2675fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Vv32.ub) 2676fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) 2677fe6060f1SDimitry Andric Instruction Type: CVI_VX 2678fe6060f1SDimitry Andric Execution Slots: SLOT23 2679fe6060f1SDimitry Andric ========================================================================== */ 2680fe6060f1SDimitry Andric 2681*0eae32dcSDimitry Andric #define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv) 2682fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2683fe6060f1SDimitry Andric 2684fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2685fe6060f1SDimitry Andric /* ========================================================================== 2686fe6060f1SDimitry Andric Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub) 2687fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 2688*0eae32dcSDimitry Andric Instruction Type: CVI_VX 2689fe6060f1SDimitry Andric Execution Slots: SLOT23 2690fe6060f1SDimitry Andric ========================================================================== */ 2691fe6060f1SDimitry Andric 2692*0eae32dcSDimitry Andric #define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv) 2693fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2694fe6060f1SDimitry Andric 2695fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2696fe6060f1SDimitry Andric /* ========================================================================== 2697fe6060f1SDimitry Andric Assembly Syntax: Vd32=vror(Vu32,Rt32) 2698fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt) 2699fe6060f1SDimitry Andric Instruction Type: CVI_VP 2700fe6060f1SDimitry Andric Execution Slots: SLOT0123 2701fe6060f1SDimitry Andric ========================================================================== */ 2702fe6060f1SDimitry Andric 2703*0eae32dcSDimitry Andric #define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt) 2704fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2705fe6060f1SDimitry Andric 2706fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2707fe6060f1SDimitry Andric /* ========================================================================== 2708fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vround(Vu32.h,Vv32.h):sat 2709fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) 2710fe6060f1SDimitry Andric Instruction Type: CVI_VS 2711fe6060f1SDimitry Andric Execution Slots: SLOT0123 2712fe6060f1SDimitry Andric ========================================================================== */ 2713fe6060f1SDimitry Andric 2714*0eae32dcSDimitry Andric #define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv) 2715fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2716fe6060f1SDimitry Andric 2717fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2718fe6060f1SDimitry Andric /* ========================================================================== 2719fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vround(Vu32.h,Vv32.h):sat 2720fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) 2721fe6060f1SDimitry Andric Instruction Type: CVI_VS 2722fe6060f1SDimitry Andric Execution Slots: SLOT0123 2723fe6060f1SDimitry Andric ========================================================================== */ 2724fe6060f1SDimitry Andric 2725*0eae32dcSDimitry Andric #define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv) 2726fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2727fe6060f1SDimitry Andric 2728fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2729fe6060f1SDimitry Andric /* ========================================================================== 2730fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vround(Vu32.w,Vv32.w):sat 2731fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) 2732fe6060f1SDimitry Andric Instruction Type: CVI_VS 2733fe6060f1SDimitry Andric Execution Slots: SLOT0123 2734fe6060f1SDimitry Andric ========================================================================== */ 2735fe6060f1SDimitry Andric 2736*0eae32dcSDimitry Andric #define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv) 2737fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2738fe6060f1SDimitry Andric 2739fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2740fe6060f1SDimitry Andric /* ========================================================================== 2741fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vround(Vu32.w,Vv32.w):sat 2742fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) 2743fe6060f1SDimitry Andric Instruction Type: CVI_VS 2744fe6060f1SDimitry Andric Execution Slots: SLOT0123 2745fe6060f1SDimitry Andric ========================================================================== */ 2746fe6060f1SDimitry Andric 2747*0eae32dcSDimitry Andric #define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv) 2748fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2749fe6060f1SDimitry Andric 2750fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2751fe6060f1SDimitry Andric /* ========================================================================== 2752fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1) 2753fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) 2754fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2755fe6060f1SDimitry Andric Execution Slots: SLOT23 2756fe6060f1SDimitry Andric ========================================================================== */ 2757fe6060f1SDimitry Andric 2758*0eae32dcSDimitry Andric #define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1) 2759fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2760fe6060f1SDimitry Andric 2761fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2762fe6060f1SDimitry Andric /* ========================================================================== 2763fe6060f1SDimitry Andric Assembly Syntax: Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1) 2764fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) 2765fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 2766fe6060f1SDimitry Andric Execution Slots: SLOT23 2767fe6060f1SDimitry Andric ========================================================================== */ 2768fe6060f1SDimitry Andric 2769*0eae32dcSDimitry Andric #define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1) 2770fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2771fe6060f1SDimitry Andric 2772fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2773fe6060f1SDimitry Andric /* ========================================================================== 2774fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vsat(Vu32.h,Vv32.h) 2775fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2776fe6060f1SDimitry Andric Instruction Type: CVI_VA 2777fe6060f1SDimitry Andric Execution Slots: SLOT0123 2778fe6060f1SDimitry Andric ========================================================================== */ 2779fe6060f1SDimitry Andric 2780*0eae32dcSDimitry Andric #define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv) 2781fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2782fe6060f1SDimitry Andric 2783fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2784fe6060f1SDimitry Andric /* ========================================================================== 2785fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vsat(Vu32.w,Vv32.w) 2786fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv) 2787fe6060f1SDimitry Andric Instruction Type: CVI_VA 2788fe6060f1SDimitry Andric Execution Slots: SLOT0123 2789fe6060f1SDimitry Andric ========================================================================== */ 2790fe6060f1SDimitry Andric 2791*0eae32dcSDimitry Andric #define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv) 2792fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2793fe6060f1SDimitry Andric 2794fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2795fe6060f1SDimitry Andric /* ========================================================================== 2796fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vsxt(Vu32.b) 2797fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu) 2798fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 2799fe6060f1SDimitry Andric Execution Slots: SLOT0123 2800fe6060f1SDimitry Andric ========================================================================== */ 2801fe6060f1SDimitry Andric 2802*0eae32dcSDimitry Andric #define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu) 2803fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2804fe6060f1SDimitry Andric 2805fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2806fe6060f1SDimitry Andric /* ========================================================================== 2807fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vsxt(Vu32.h) 2808fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu) 2809fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 2810fe6060f1SDimitry Andric Execution Slots: SLOT0123 2811fe6060f1SDimitry Andric ========================================================================== */ 2812fe6060f1SDimitry Andric 2813*0eae32dcSDimitry Andric #define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu) 2814fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2815fe6060f1SDimitry Andric 2816fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2817fe6060f1SDimitry Andric /* ========================================================================== 2818fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vshuffe(Vu32.h,Vv32.h) 2819fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2820fe6060f1SDimitry Andric Instruction Type: CVI_VA 2821fe6060f1SDimitry Andric Execution Slots: SLOT0123 2822fe6060f1SDimitry Andric ========================================================================== */ 2823fe6060f1SDimitry Andric 2824*0eae32dcSDimitry Andric #define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv) 2825fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2826fe6060f1SDimitry Andric 2827fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2828fe6060f1SDimitry Andric /* ========================================================================== 2829fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vshuff(Vu32.b) 2830fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu) 2831fe6060f1SDimitry Andric Instruction Type: CVI_VP 2832fe6060f1SDimitry Andric Execution Slots: SLOT0123 2833fe6060f1SDimitry Andric ========================================================================== */ 2834fe6060f1SDimitry Andric 2835*0eae32dcSDimitry Andric #define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu) 2836fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2837fe6060f1SDimitry Andric 2838fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2839fe6060f1SDimitry Andric /* ========================================================================== 2840fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vshuffe(Vu32.b,Vv32.b) 2841fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv) 2842fe6060f1SDimitry Andric Instruction Type: CVI_VA 2843fe6060f1SDimitry Andric Execution Slots: SLOT0123 2844fe6060f1SDimitry Andric ========================================================================== */ 2845fe6060f1SDimitry Andric 2846*0eae32dcSDimitry Andric #define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv) 2847fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2848fe6060f1SDimitry Andric 2849fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2850fe6060f1SDimitry Andric /* ========================================================================== 2851fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vshuff(Vu32.h) 2852fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu) 2853fe6060f1SDimitry Andric Instruction Type: CVI_VP 2854fe6060f1SDimitry Andric Execution Slots: SLOT0123 2855fe6060f1SDimitry Andric ========================================================================== */ 2856fe6060f1SDimitry Andric 2857*0eae32dcSDimitry Andric #define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu) 2858fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2859fe6060f1SDimitry Andric 2860fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2861fe6060f1SDimitry Andric /* ========================================================================== 2862fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vshuffo(Vu32.b,Vv32.b) 2863fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv) 2864fe6060f1SDimitry Andric Instruction Type: CVI_VA 2865fe6060f1SDimitry Andric Execution Slots: SLOT0123 2866fe6060f1SDimitry Andric ========================================================================== */ 2867fe6060f1SDimitry Andric 2868*0eae32dcSDimitry Andric #define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv) 2869fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2870fe6060f1SDimitry Andric 2871fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2872fe6060f1SDimitry Andric /* ========================================================================== 2873fe6060f1SDimitry Andric Assembly Syntax: Vdd32=vshuff(Vu32,Vv32,Rt8) 2874fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 2875fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 2876fe6060f1SDimitry Andric Execution Slots: SLOT0123 2877fe6060f1SDimitry Andric ========================================================================== */ 2878fe6060f1SDimitry Andric 2879*0eae32dcSDimitry Andric #define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt) 2880fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2881fe6060f1SDimitry Andric 2882fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2883fe6060f1SDimitry Andric /* ========================================================================== 2884fe6060f1SDimitry Andric Assembly Syntax: Vdd32.b=vshuffoe(Vu32.b,Vv32.b) 2885fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv) 2886fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 2887fe6060f1SDimitry Andric Execution Slots: SLOT0123 2888fe6060f1SDimitry Andric ========================================================================== */ 2889fe6060f1SDimitry Andric 2890*0eae32dcSDimitry Andric #define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv) 2891fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2892fe6060f1SDimitry Andric 2893fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2894fe6060f1SDimitry Andric /* ========================================================================== 2895fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vshuffoe(Vu32.h,Vv32.h) 2896fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2897fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 2898fe6060f1SDimitry Andric Execution Slots: SLOT0123 2899fe6060f1SDimitry Andric ========================================================================== */ 2900fe6060f1SDimitry Andric 2901*0eae32dcSDimitry Andric #define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv) 2902fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2903fe6060f1SDimitry Andric 2904fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2905fe6060f1SDimitry Andric /* ========================================================================== 2906fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vshuffo(Vu32.h,Vv32.h) 2907fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2908fe6060f1SDimitry Andric Instruction Type: CVI_VA 2909fe6060f1SDimitry Andric Execution Slots: SLOT0123 2910fe6060f1SDimitry Andric ========================================================================== */ 2911fe6060f1SDimitry Andric 2912*0eae32dcSDimitry Andric #define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv) 2913fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2914fe6060f1SDimitry Andric 2915fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2916fe6060f1SDimitry Andric /* ========================================================================== 2917fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b) 2918fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv) 2919fe6060f1SDimitry Andric Instruction Type: CVI_VA 2920fe6060f1SDimitry Andric Execution Slots: SLOT0123 2921fe6060f1SDimitry Andric ========================================================================== */ 2922fe6060f1SDimitry Andric 2923*0eae32dcSDimitry Andric #define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv) 2924fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2925fe6060f1SDimitry Andric 2926fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2927fe6060f1SDimitry Andric /* ========================================================================== 2928fe6060f1SDimitry Andric Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b) 2929fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 2930fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 2931fe6060f1SDimitry Andric Execution Slots: SLOT0123 2932fe6060f1SDimitry Andric ========================================================================== */ 2933fe6060f1SDimitry Andric 2934*0eae32dcSDimitry Andric #define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv) 2935fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2936fe6060f1SDimitry Andric 2937fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2938fe6060f1SDimitry Andric /* ========================================================================== 2939fe6060f1SDimitry Andric Assembly Syntax: if (!Qv4) Vx32.b-=Vu32.b 2940fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 2941fe6060f1SDimitry Andric Instruction Type: CVI_VA 2942fe6060f1SDimitry Andric Execution Slots: SLOT0123 2943fe6060f1SDimitry Andric ========================================================================== */ 2944fe6060f1SDimitry Andric 2945*0eae32dcSDimitry Andric #define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 2946fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2947fe6060f1SDimitry Andric 2948fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2949fe6060f1SDimitry Andric /* ========================================================================== 2950fe6060f1SDimitry Andric Assembly Syntax: if (Qv4) Vx32.b-=Vu32.b 2951fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 2952fe6060f1SDimitry Andric Instruction Type: CVI_VA 2953fe6060f1SDimitry Andric Execution Slots: SLOT0123 2954fe6060f1SDimitry Andric ========================================================================== */ 2955fe6060f1SDimitry Andric 2956*0eae32dcSDimitry Andric #define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 2957fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2958fe6060f1SDimitry Andric 2959fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2960fe6060f1SDimitry Andric /* ========================================================================== 2961fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h) 2962fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) 2963fe6060f1SDimitry Andric Instruction Type: CVI_VA 2964fe6060f1SDimitry Andric Execution Slots: SLOT0123 2965fe6060f1SDimitry Andric ========================================================================== */ 2966fe6060f1SDimitry Andric 2967*0eae32dcSDimitry Andric #define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv) 2968fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2969fe6060f1SDimitry Andric 2970fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2971fe6060f1SDimitry Andric /* ========================================================================== 2972fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h) 2973fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 2974fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 2975fe6060f1SDimitry Andric Execution Slots: SLOT0123 2976fe6060f1SDimitry Andric ========================================================================== */ 2977fe6060f1SDimitry Andric 2978*0eae32dcSDimitry Andric #define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv) 2979fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2980fe6060f1SDimitry Andric 2981fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2982fe6060f1SDimitry Andric /* ========================================================================== 2983fe6060f1SDimitry Andric Assembly Syntax: if (!Qv4) Vx32.h-=Vu32.h 2984fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 2985fe6060f1SDimitry Andric Instruction Type: CVI_VA 2986fe6060f1SDimitry Andric Execution Slots: SLOT0123 2987fe6060f1SDimitry Andric ========================================================================== */ 2988fe6060f1SDimitry Andric 2989*0eae32dcSDimitry Andric #define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 2990fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 2991fe6060f1SDimitry Andric 2992fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 2993fe6060f1SDimitry Andric /* ========================================================================== 2994fe6060f1SDimitry Andric Assembly Syntax: if (Qv4) Vx32.h-=Vu32.h 2995fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 2996fe6060f1SDimitry Andric Instruction Type: CVI_VA 2997fe6060f1SDimitry Andric Execution Slots: SLOT0123 2998fe6060f1SDimitry Andric ========================================================================== */ 2999fe6060f1SDimitry Andric 3000*0eae32dcSDimitry Andric #define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 3001fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3002fe6060f1SDimitry Andric 3003fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3004fe6060f1SDimitry Andric /* ========================================================================== 3005fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h):sat 3006fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) 3007fe6060f1SDimitry Andric Instruction Type: CVI_VA 3008fe6060f1SDimitry Andric Execution Slots: SLOT0123 3009fe6060f1SDimitry Andric ========================================================================== */ 3010fe6060f1SDimitry Andric 3011*0eae32dcSDimitry Andric #define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv) 3012fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3013fe6060f1SDimitry Andric 3014fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3015fe6060f1SDimitry Andric /* ========================================================================== 3016fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat 3017fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 3018fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3019fe6060f1SDimitry Andric Execution Slots: SLOT0123 3020fe6060f1SDimitry Andric ========================================================================== */ 3021fe6060f1SDimitry Andric 3022*0eae32dcSDimitry Andric #define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv) 3023fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3024fe6060f1SDimitry Andric 3025fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3026fe6060f1SDimitry Andric /* ========================================================================== 3027fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vsub(Vu32.h,Vv32.h) 3028fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) 3029fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3030fe6060f1SDimitry Andric Execution Slots: SLOT23 3031fe6060f1SDimitry Andric ========================================================================== */ 3032fe6060f1SDimitry Andric 3033*0eae32dcSDimitry Andric #define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv) 3034fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3035fe6060f1SDimitry Andric 3036fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3037fe6060f1SDimitry Andric /* ========================================================================== 3038fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vsub(Vu32.ub,Vv32.ub) 3039fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv) 3040fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3041fe6060f1SDimitry Andric Execution Slots: SLOT23 3042fe6060f1SDimitry Andric ========================================================================== */ 3043fe6060f1SDimitry Andric 3044*0eae32dcSDimitry Andric #define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv) 3045fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3046fe6060f1SDimitry Andric 3047fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3048fe6060f1SDimitry Andric /* ========================================================================== 3049fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat 3050fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) 3051fe6060f1SDimitry Andric Instruction Type: CVI_VA 3052fe6060f1SDimitry Andric Execution Slots: SLOT0123 3053fe6060f1SDimitry Andric ========================================================================== */ 3054fe6060f1SDimitry Andric 3055*0eae32dcSDimitry Andric #define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv) 3056fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3057fe6060f1SDimitry Andric 3058fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3059fe6060f1SDimitry Andric /* ========================================================================== 3060fe6060f1SDimitry Andric Assembly Syntax: Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat 3061fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 3062fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3063fe6060f1SDimitry Andric Execution Slots: SLOT0123 3064fe6060f1SDimitry Andric ========================================================================== */ 3065fe6060f1SDimitry Andric 3066*0eae32dcSDimitry Andric #define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv) 3067fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3068fe6060f1SDimitry Andric 3069fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3070fe6060f1SDimitry Andric /* ========================================================================== 3071fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat 3072fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) 3073fe6060f1SDimitry Andric Instruction Type: CVI_VA 3074fe6060f1SDimitry Andric Execution Slots: SLOT0123 3075fe6060f1SDimitry Andric ========================================================================== */ 3076fe6060f1SDimitry Andric 3077*0eae32dcSDimitry Andric #define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv) 3078fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3079fe6060f1SDimitry Andric 3080fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3081fe6060f1SDimitry Andric /* ========================================================================== 3082fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat 3083fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 3084fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3085fe6060f1SDimitry Andric Execution Slots: SLOT0123 3086fe6060f1SDimitry Andric ========================================================================== */ 3087fe6060f1SDimitry Andric 3088*0eae32dcSDimitry Andric #define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv) 3089fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3090fe6060f1SDimitry Andric 3091fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3092fe6060f1SDimitry Andric /* ========================================================================== 3093fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vsub(Vu32.uh,Vv32.uh) 3094fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) 3095fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3096fe6060f1SDimitry Andric Execution Slots: SLOT23 3097fe6060f1SDimitry Andric ========================================================================== */ 3098fe6060f1SDimitry Andric 3099*0eae32dcSDimitry Andric #define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv) 3100fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3101fe6060f1SDimitry Andric 3102fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3103fe6060f1SDimitry Andric /* ========================================================================== 3104fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w) 3105fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv) 3106fe6060f1SDimitry Andric Instruction Type: CVI_VA 3107fe6060f1SDimitry Andric Execution Slots: SLOT0123 3108fe6060f1SDimitry Andric ========================================================================== */ 3109fe6060f1SDimitry Andric 3110*0eae32dcSDimitry Andric #define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv) 3111fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3112fe6060f1SDimitry Andric 3113fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3114fe6060f1SDimitry Andric /* ========================================================================== 3115fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w) 3116fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 3117fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3118fe6060f1SDimitry Andric Execution Slots: SLOT0123 3119fe6060f1SDimitry Andric ========================================================================== */ 3120fe6060f1SDimitry Andric 3121*0eae32dcSDimitry Andric #define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv) 3122fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3123fe6060f1SDimitry Andric 3124fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3125fe6060f1SDimitry Andric /* ========================================================================== 3126fe6060f1SDimitry Andric Assembly Syntax: if (!Qv4) Vx32.w-=Vu32.w 3127fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 3128fe6060f1SDimitry Andric Instruction Type: CVI_VA 3129fe6060f1SDimitry Andric Execution Slots: SLOT0123 3130fe6060f1SDimitry Andric ========================================================================== */ 3131fe6060f1SDimitry Andric 3132*0eae32dcSDimitry Andric #define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 3133fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3134fe6060f1SDimitry Andric 3135fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3136fe6060f1SDimitry Andric /* ========================================================================== 3137fe6060f1SDimitry Andric Assembly Syntax: if (Qv4) Vx32.w-=Vu32.w 3138fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) 3139fe6060f1SDimitry Andric Instruction Type: CVI_VA 3140fe6060f1SDimitry Andric Execution Slots: SLOT0123 3141fe6060f1SDimitry Andric ========================================================================== */ 3142fe6060f1SDimitry Andric 3143*0eae32dcSDimitry Andric #define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) 3144fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3145fe6060f1SDimitry Andric 3146fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3147fe6060f1SDimitry Andric /* ========================================================================== 3148fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w):sat 3149fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) 3150fe6060f1SDimitry Andric Instruction Type: CVI_VA 3151fe6060f1SDimitry Andric Execution Slots: SLOT0123 3152fe6060f1SDimitry Andric ========================================================================== */ 3153fe6060f1SDimitry Andric 3154*0eae32dcSDimitry Andric #define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv) 3155fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3156fe6060f1SDimitry Andric 3157fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3158fe6060f1SDimitry Andric /* ========================================================================== 3159fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat 3160fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 3161fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3162fe6060f1SDimitry Andric Execution Slots: SLOT0123 3163fe6060f1SDimitry Andric ========================================================================== */ 3164fe6060f1SDimitry Andric 3165*0eae32dcSDimitry Andric #define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv) 3166fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3167fe6060f1SDimitry Andric 3168fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3169fe6060f1SDimitry Andric /* ========================================================================== 3170fe6060f1SDimitry Andric Assembly Syntax: Vdd32=vswap(Qt4,Vu32,Vv32) 3171fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) 3172fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3173fe6060f1SDimitry Andric Execution Slots: SLOT0123 3174fe6060f1SDimitry Andric ========================================================================== */ 3175fe6060f1SDimitry Andric 3176*0eae32dcSDimitry Andric #define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) 3177fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3178fe6060f1SDimitry Andric 3179fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3180fe6060f1SDimitry Andric /* ========================================================================== 3181fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vtmpy(Vuu32.b,Rt32.b) 3182fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt) 3183fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3184fe6060f1SDimitry Andric Execution Slots: SLOT23 3185fe6060f1SDimitry Andric ========================================================================== */ 3186fe6060f1SDimitry Andric 3187*0eae32dcSDimitry Andric #define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt) 3188fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3189fe6060f1SDimitry Andric 3190fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3191fe6060f1SDimitry Andric /* ========================================================================== 3192fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.b,Rt32.b) 3193fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 3194fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3195fe6060f1SDimitry Andric Execution Slots: SLOT23 3196fe6060f1SDimitry Andric ========================================================================== */ 3197fe6060f1SDimitry Andric 3198*0eae32dcSDimitry Andric #define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt) 3199fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3200fe6060f1SDimitry Andric 3201fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3202fe6060f1SDimitry Andric /* ========================================================================== 3203fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vtmpy(Vuu32.ub,Rt32.b) 3204fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) 3205fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3206fe6060f1SDimitry Andric Execution Slots: SLOT23 3207fe6060f1SDimitry Andric ========================================================================== */ 3208fe6060f1SDimitry Andric 3209*0eae32dcSDimitry Andric #define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt) 3210fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3211fe6060f1SDimitry Andric 3212fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3213fe6060f1SDimitry Andric /* ========================================================================== 3214fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b) 3215fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 3216fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3217fe6060f1SDimitry Andric Execution Slots: SLOT23 3218fe6060f1SDimitry Andric ========================================================================== */ 3219fe6060f1SDimitry Andric 3220*0eae32dcSDimitry Andric #define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt) 3221fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3222fe6060f1SDimitry Andric 3223fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3224fe6060f1SDimitry Andric /* ========================================================================== 3225fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vtmpy(Vuu32.h,Rt32.b) 3226fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) 3227fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3228fe6060f1SDimitry Andric Execution Slots: SLOT23 3229fe6060f1SDimitry Andric ========================================================================== */ 3230fe6060f1SDimitry Andric 3231*0eae32dcSDimitry Andric #define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt) 3232fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3233fe6060f1SDimitry Andric 3234fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3235fe6060f1SDimitry Andric /* ========================================================================== 3236fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vtmpy(Vuu32.h,Rt32.b) 3237fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 3238fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3239fe6060f1SDimitry Andric Execution Slots: SLOT23 3240fe6060f1SDimitry Andric ========================================================================== */ 3241fe6060f1SDimitry Andric 3242*0eae32dcSDimitry Andric #define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt) 3243fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3244fe6060f1SDimitry Andric 3245fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3246fe6060f1SDimitry Andric /* ========================================================================== 3247fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vunpack(Vu32.b) 3248fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu) 3249fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3250fe6060f1SDimitry Andric Execution Slots: SLOT0123 3251fe6060f1SDimitry Andric ========================================================================== */ 3252fe6060f1SDimitry Andric 3253*0eae32dcSDimitry Andric #define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu) 3254fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3255fe6060f1SDimitry Andric 3256fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3257fe6060f1SDimitry Andric /* ========================================================================== 3258fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vunpack(Vu32.h) 3259fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu) 3260fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3261fe6060f1SDimitry Andric Execution Slots: SLOT0123 3262fe6060f1SDimitry Andric ========================================================================== */ 3263fe6060f1SDimitry Andric 3264*0eae32dcSDimitry Andric #define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu) 3265fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3266fe6060f1SDimitry Andric 3267fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3268fe6060f1SDimitry Andric /* ========================================================================== 3269fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h|=vunpacko(Vu32.b) 3270fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu) 3271fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3272fe6060f1SDimitry Andric Execution Slots: SLOT0123 3273fe6060f1SDimitry Andric ========================================================================== */ 3274fe6060f1SDimitry Andric 3275*0eae32dcSDimitry Andric #define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu) 3276fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3277fe6060f1SDimitry Andric 3278fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3279fe6060f1SDimitry Andric /* ========================================================================== 3280fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w|=vunpacko(Vu32.h) 3281fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu) 3282fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3283fe6060f1SDimitry Andric Execution Slots: SLOT0123 3284fe6060f1SDimitry Andric ========================================================================== */ 3285fe6060f1SDimitry Andric 3286*0eae32dcSDimitry Andric #define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu) 3287fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3288fe6060f1SDimitry Andric 3289fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3290fe6060f1SDimitry Andric /* ========================================================================== 3291fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uh=vunpack(Vu32.ub) 3292fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu) 3293fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3294fe6060f1SDimitry Andric Execution Slots: SLOT0123 3295fe6060f1SDimitry Andric ========================================================================== */ 3296fe6060f1SDimitry Andric 3297*0eae32dcSDimitry Andric #define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu) 3298fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3299fe6060f1SDimitry Andric 3300fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3301fe6060f1SDimitry Andric /* ========================================================================== 3302fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uw=vunpack(Vu32.uh) 3303fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu) 3304fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3305fe6060f1SDimitry Andric Execution Slots: SLOT0123 3306fe6060f1SDimitry Andric ========================================================================== */ 3307fe6060f1SDimitry Andric 3308*0eae32dcSDimitry Andric #define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu) 3309fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3310fe6060f1SDimitry Andric 3311fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3312fe6060f1SDimitry Andric /* ========================================================================== 3313fe6060f1SDimitry Andric Assembly Syntax: Vd32=vxor(Vu32,Vv32) 3314fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv) 3315fe6060f1SDimitry Andric Instruction Type: CVI_VA 3316fe6060f1SDimitry Andric Execution Slots: SLOT0123 3317fe6060f1SDimitry Andric ========================================================================== */ 3318fe6060f1SDimitry Andric 3319*0eae32dcSDimitry Andric #define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv) 3320fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3321fe6060f1SDimitry Andric 3322fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3323fe6060f1SDimitry Andric /* ========================================================================== 3324fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uh=vzxt(Vu32.ub) 3325fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu) 3326fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3327fe6060f1SDimitry Andric Execution Slots: SLOT0123 3328fe6060f1SDimitry Andric ========================================================================== */ 3329fe6060f1SDimitry Andric 3330*0eae32dcSDimitry Andric #define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu) 3331fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3332fe6060f1SDimitry Andric 3333fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 60 3334fe6060f1SDimitry Andric /* ========================================================================== 3335fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uw=vzxt(Vu32.uh) 3336fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu) 3337fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3338fe6060f1SDimitry Andric Execution Slots: SLOT0123 3339fe6060f1SDimitry Andric ========================================================================== */ 3340fe6060f1SDimitry Andric 3341*0eae32dcSDimitry Andric #define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu) 3342fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 60 */ 3343fe6060f1SDimitry Andric 3344fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3345fe6060f1SDimitry Andric /* ========================================================================== 3346fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vsplat(Rt32) 3347fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt) 3348fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 3349fe6060f1SDimitry Andric Execution Slots: SLOT23 3350fe6060f1SDimitry Andric ========================================================================== */ 3351fe6060f1SDimitry Andric 3352*0eae32dcSDimitry Andric #define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt) 3353fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3354fe6060f1SDimitry Andric 3355fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3356fe6060f1SDimitry Andric /* ========================================================================== 3357fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vsplat(Rt32) 3358fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt) 3359fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 3360fe6060f1SDimitry Andric Execution Slots: SLOT23 3361fe6060f1SDimitry Andric ========================================================================== */ 3362fe6060f1SDimitry Andric 3363*0eae32dcSDimitry Andric #define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt) 3364fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3365fe6060f1SDimitry Andric 3366fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3367fe6060f1SDimitry Andric /* ========================================================================== 3368fe6060f1SDimitry Andric Assembly Syntax: Qd4=vsetq2(Rt32) 3369fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt) 3370fe6060f1SDimitry Andric Instruction Type: CVI_VP 3371fe6060f1SDimitry Andric Execution Slots: SLOT0123 3372fe6060f1SDimitry Andric ========================================================================== */ 3373fe6060f1SDimitry Andric 3374*0eae32dcSDimitry Andric #define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1) 3375fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3376fe6060f1SDimitry Andric 3377fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3378fe6060f1SDimitry Andric /* ========================================================================== 3379fe6060f1SDimitry Andric Assembly Syntax: Qd4.b=vshuffe(Qs4.h,Qt4.h) 3380fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt) 3381fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3382fe6060f1SDimitry Andric Execution Slots: SLOT0123 3383fe6060f1SDimitry Andric ========================================================================== */ 3384fe6060f1SDimitry Andric 3385*0eae32dcSDimitry Andric #define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) 3386fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3387fe6060f1SDimitry Andric 3388fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3389fe6060f1SDimitry Andric /* ========================================================================== 3390fe6060f1SDimitry Andric Assembly Syntax: Qd4.h=vshuffe(Qs4.w,Qt4.w) 3391fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt) 3392fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3393fe6060f1SDimitry Andric Execution Slots: SLOT0123 3394fe6060f1SDimitry Andric ========================================================================== */ 3395fe6060f1SDimitry Andric 3396*0eae32dcSDimitry Andric #define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) 3397fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3398fe6060f1SDimitry Andric 3399fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3400fe6060f1SDimitry Andric /* ========================================================================== 3401fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b):sat 3402fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) 3403fe6060f1SDimitry Andric Instruction Type: CVI_VA 3404fe6060f1SDimitry Andric Execution Slots: SLOT0123 3405fe6060f1SDimitry Andric ========================================================================== */ 3406fe6060f1SDimitry Andric 3407*0eae32dcSDimitry Andric #define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv) 3408fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3409fe6060f1SDimitry Andric 3410fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3411fe6060f1SDimitry Andric /* ========================================================================== 3412fe6060f1SDimitry Andric Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat 3413fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 3414fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3415fe6060f1SDimitry Andric Execution Slots: SLOT0123 3416fe6060f1SDimitry Andric ========================================================================== */ 3417fe6060f1SDimitry Andric 3418*0eae32dcSDimitry Andric #define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv) 3419fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3420fe6060f1SDimitry Andric 3421fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3422fe6060f1SDimitry Andric /* ========================================================================== 3423fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry 3424fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) 3425fe6060f1SDimitry Andric Instruction Type: CVI_VA 3426fe6060f1SDimitry Andric Execution Slots: SLOT0123 3427fe6060f1SDimitry Andric ========================================================================== */ 3428fe6060f1SDimitry Andric 3429*0eae32dcSDimitry Andric #define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx) 3430fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3431fe6060f1SDimitry Andric 3432fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3433fe6060f1SDimitry Andric /* ========================================================================== 3434fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vadd(vclb(Vu32.h),Vv32.h) 3435fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv) 3436fe6060f1SDimitry Andric Instruction Type: CVI_VS 3437fe6060f1SDimitry Andric Execution Slots: SLOT0123 3438fe6060f1SDimitry Andric ========================================================================== */ 3439fe6060f1SDimitry Andric 3440*0eae32dcSDimitry Andric #define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv) 3441fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3442fe6060f1SDimitry Andric 3443fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3444fe6060f1SDimitry Andric /* ========================================================================== 3445fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vadd(vclb(Vu32.w),Vv32.w) 3446fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv) 3447fe6060f1SDimitry Andric Instruction Type: CVI_VS 3448fe6060f1SDimitry Andric Execution Slots: SLOT0123 3449fe6060f1SDimitry Andric ========================================================================== */ 3450fe6060f1SDimitry Andric 3451*0eae32dcSDimitry Andric #define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv) 3452fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3453fe6060f1SDimitry Andric 3454fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3455fe6060f1SDimitry Andric /* ========================================================================== 3456fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vadd(Vu32.h,Vv32.h) 3457fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 3458fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3459fe6060f1SDimitry Andric Execution Slots: SLOT23 3460fe6060f1SDimitry Andric ========================================================================== */ 3461fe6060f1SDimitry Andric 3462*0eae32dcSDimitry Andric #define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv) 3463fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3464fe6060f1SDimitry Andric 3465fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3466fe6060f1SDimitry Andric /* ========================================================================== 3467fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h+=vadd(Vu32.ub,Vv32.ub) 3468fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 3469fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3470fe6060f1SDimitry Andric Execution Slots: SLOT23 3471fe6060f1SDimitry Andric ========================================================================== */ 3472fe6060f1SDimitry Andric 3473*0eae32dcSDimitry Andric #define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv) 3474fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3475fe6060f1SDimitry Andric 3476fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3477fe6060f1SDimitry Andric /* ========================================================================== 3478fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.b):sat 3479fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) 3480fe6060f1SDimitry Andric Instruction Type: CVI_VA 3481fe6060f1SDimitry Andric Execution Slots: SLOT0123 3482fe6060f1SDimitry Andric ========================================================================== */ 3483fe6060f1SDimitry Andric 3484*0eae32dcSDimitry Andric #define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv) 3485fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3486fe6060f1SDimitry Andric 3487fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3488fe6060f1SDimitry Andric /* ========================================================================== 3489fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vadd(Vu32.uh,Vv32.uh) 3490fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 3491fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3492fe6060f1SDimitry Andric Execution Slots: SLOT23 3493fe6060f1SDimitry Andric ========================================================================== */ 3494fe6060f1SDimitry Andric 3495*0eae32dcSDimitry Andric #define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv) 3496fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3497fe6060f1SDimitry Andric 3498fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3499fe6060f1SDimitry Andric /* ========================================================================== 3500fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat 3501fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) 3502fe6060f1SDimitry Andric Instruction Type: CVI_VA 3503fe6060f1SDimitry Andric Execution Slots: SLOT0123 3504fe6060f1SDimitry Andric ========================================================================== */ 3505fe6060f1SDimitry Andric 3506*0eae32dcSDimitry Andric #define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv) 3507fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3508fe6060f1SDimitry Andric 3509fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3510fe6060f1SDimitry Andric /* ========================================================================== 3511fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat 3512fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 3513fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3514fe6060f1SDimitry Andric Execution Slots: SLOT0123 3515fe6060f1SDimitry Andric ========================================================================== */ 3516fe6060f1SDimitry Andric 3517*0eae32dcSDimitry Andric #define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv) 3518fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3519fe6060f1SDimitry Andric 3520fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3521fe6060f1SDimitry Andric /* ========================================================================== 3522fe6060f1SDimitry Andric Assembly Syntax: Vd32=vand(!Qu4,Rt32) 3523fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt) 3524fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 3525fe6060f1SDimitry Andric Execution Slots: SLOT23 3526fe6060f1SDimitry Andric ========================================================================== */ 3527fe6060f1SDimitry Andric 3528*0eae32dcSDimitry Andric #define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) 3529fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3530fe6060f1SDimitry Andric 3531fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3532fe6060f1SDimitry Andric /* ========================================================================== 3533fe6060f1SDimitry Andric Assembly Syntax: Vx32|=vand(!Qu4,Rt32) 3534fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) 3535fe6060f1SDimitry Andric Instruction Type: CVI_VX_LATE 3536fe6060f1SDimitry Andric Execution Slots: SLOT23 3537fe6060f1SDimitry Andric ========================================================================== */ 3538fe6060f1SDimitry Andric 3539*0eae32dcSDimitry Andric #define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) 3540fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3541fe6060f1SDimitry Andric 3542fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3543fe6060f1SDimitry Andric /* ========================================================================== 3544fe6060f1SDimitry Andric Assembly Syntax: Vd32=vand(!Qv4,Vu32) 3545fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu) 3546fe6060f1SDimitry Andric Instruction Type: CVI_VA 3547fe6060f1SDimitry Andric Execution Slots: SLOT0123 3548fe6060f1SDimitry Andric ========================================================================== */ 3549fe6060f1SDimitry Andric 3550*0eae32dcSDimitry Andric #define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) 3551fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3552fe6060f1SDimitry Andric 3553fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3554fe6060f1SDimitry Andric /* ========================================================================== 3555fe6060f1SDimitry Andric Assembly Syntax: Vd32=vand(Qv4,Vu32) 3556fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu) 3557fe6060f1SDimitry Andric Instruction Type: CVI_VA 3558fe6060f1SDimitry Andric Execution Slots: SLOT0123 3559fe6060f1SDimitry Andric ========================================================================== */ 3560fe6060f1SDimitry Andric 3561*0eae32dcSDimitry Andric #define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) 3562fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3563fe6060f1SDimitry Andric 3564fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3565fe6060f1SDimitry Andric /* ========================================================================== 3566fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat 3567fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 3568fe6060f1SDimitry Andric Instruction Type: CVI_VS 3569fe6060f1SDimitry Andric Execution Slots: SLOT0123 3570fe6060f1SDimitry Andric ========================================================================== */ 3571fe6060f1SDimitry Andric 3572*0eae32dcSDimitry Andric #define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt) 3573fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3574fe6060f1SDimitry Andric 3575fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3576fe6060f1SDimitry Andric /* ========================================================================== 3577fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat 3578fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 3579fe6060f1SDimitry Andric Instruction Type: CVI_VS 3580fe6060f1SDimitry Andric Execution Slots: SLOT0123 3581fe6060f1SDimitry Andric ========================================================================== */ 3582fe6060f1SDimitry Andric 3583*0eae32dcSDimitry Andric #define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt) 3584fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3585fe6060f1SDimitry Andric 3586fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3587fe6060f1SDimitry Andric /* ========================================================================== 3588fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat 3589fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 3590fe6060f1SDimitry Andric Instruction Type: CVI_VS 3591fe6060f1SDimitry Andric Execution Slots: SLOT0123 3592fe6060f1SDimitry Andric ========================================================================== */ 3593fe6060f1SDimitry Andric 3594*0eae32dcSDimitry Andric #define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt) 3595fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3596fe6060f1SDimitry Andric 3597fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3598fe6060f1SDimitry Andric /* ========================================================================== 3599fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vlsr(Vu32.ub,Rt32) 3600fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt) 3601fe6060f1SDimitry Andric Instruction Type: CVI_VS 3602fe6060f1SDimitry Andric Execution Slots: SLOT0123 3603fe6060f1SDimitry Andric ========================================================================== */ 3604fe6060f1SDimitry Andric 3605*0eae32dcSDimitry Andric #define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt) 3606fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3607fe6060f1SDimitry Andric 3608fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3609fe6060f1SDimitry Andric /* ========================================================================== 3610fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch 3611fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 3612fe6060f1SDimitry Andric Instruction Type: CVI_VP 3613fe6060f1SDimitry Andric Execution Slots: SLOT0123 3614fe6060f1SDimitry Andric ========================================================================== */ 3615fe6060f1SDimitry Andric 3616*0eae32dcSDimitry Andric #define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt) 3617fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3618fe6060f1SDimitry Andric 3619fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3620fe6060f1SDimitry Andric /* ========================================================================== 3621fe6060f1SDimitry Andric Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3) 3622fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) 3623fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3624fe6060f1SDimitry Andric Execution Slots: SLOT0123 3625fe6060f1SDimitry Andric ========================================================================== */ 3626fe6060f1SDimitry Andric 3627*0eae32dcSDimitry Andric #define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3) 3628fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3629fe6060f1SDimitry Andric 3630fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3631fe6060f1SDimitry Andric /* ========================================================================== 3632fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,#u3) 3633fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) 3634fe6060f1SDimitry Andric Instruction Type: CVI_VP 3635fe6060f1SDimitry Andric Execution Slots: SLOT0123 3636fe6060f1SDimitry Andric ========================================================================== */ 3637fe6060f1SDimitry Andric 3638*0eae32dcSDimitry Andric #define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3) 3639fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3640fe6060f1SDimitry Andric 3641fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3642fe6060f1SDimitry Andric /* ========================================================================== 3643fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch 3644fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 3645fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3646fe6060f1SDimitry Andric Execution Slots: SLOT0123 3647fe6060f1SDimitry Andric ========================================================================== */ 3648fe6060f1SDimitry Andric 3649*0eae32dcSDimitry Andric #define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt) 3650fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3651fe6060f1SDimitry Andric 3652fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3653fe6060f1SDimitry Andric /* ========================================================================== 3654fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3) 3655fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) 3656fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3657fe6060f1SDimitry Andric Execution Slots: SLOT0123 3658fe6060f1SDimitry Andric ========================================================================== */ 3659fe6060f1SDimitry Andric 3660*0eae32dcSDimitry Andric #define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3) 3661fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3662fe6060f1SDimitry Andric 3663fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3664fe6060f1SDimitry Andric /* ========================================================================== 3665fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3) 3666fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) 3667fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 3668fe6060f1SDimitry Andric Execution Slots: SLOT0123 3669fe6060f1SDimitry Andric ========================================================================== */ 3670fe6060f1SDimitry Andric 3671*0eae32dcSDimitry Andric #define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3) 3672fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3673fe6060f1SDimitry Andric 3674fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3675fe6060f1SDimitry Andric /* ========================================================================== 3676fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vmax(Vu32.b,Vv32.b) 3677fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv) 3678fe6060f1SDimitry Andric Instruction Type: CVI_VA 3679fe6060f1SDimitry Andric Execution Slots: SLOT0123 3680fe6060f1SDimitry Andric ========================================================================== */ 3681fe6060f1SDimitry Andric 3682*0eae32dcSDimitry Andric #define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv) 3683fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3684fe6060f1SDimitry Andric 3685fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3686fe6060f1SDimitry Andric /* ========================================================================== 3687fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vmin(Vu32.b,Vv32.b) 3688fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv) 3689fe6060f1SDimitry Andric Instruction Type: CVI_VA 3690fe6060f1SDimitry Andric Execution Slots: SLOT0123 3691fe6060f1SDimitry Andric ========================================================================== */ 3692fe6060f1SDimitry Andric 3693*0eae32dcSDimitry Andric #define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv) 3694fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3695fe6060f1SDimitry Andric 3696fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3697fe6060f1SDimitry Andric /* ========================================================================== 3698fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=vmpa(Vuu32.uh,Rt32.b) 3699fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt) 3700fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3701fe6060f1SDimitry Andric Execution Slots: SLOT23 3702fe6060f1SDimitry Andric ========================================================================== */ 3703fe6060f1SDimitry Andric 3704*0eae32dcSDimitry Andric #define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt) 3705fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3706fe6060f1SDimitry Andric 3707fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3708fe6060f1SDimitry Andric /* ========================================================================== 3709fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vmpa(Vuu32.uh,Rt32.b) 3710fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 3711fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3712fe6060f1SDimitry Andric Execution Slots: SLOT23 3713fe6060f1SDimitry Andric ========================================================================== */ 3714fe6060f1SDimitry Andric 3715*0eae32dcSDimitry Andric #define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt) 3716fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3717fe6060f1SDimitry Andric 3718fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3719fe6060f1SDimitry Andric /* ========================================================================== 3720fe6060f1SDimitry Andric Assembly Syntax: Vdd32=vmpye(Vu32.w,Vv32.uh) 3721fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) 3722fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3723fe6060f1SDimitry Andric Execution Slots: SLOT23 3724fe6060f1SDimitry Andric ========================================================================== */ 3725fe6060f1SDimitry Andric 3726*0eae32dcSDimitry Andric #define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv) 3727fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3728fe6060f1SDimitry Andric 3729fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3730fe6060f1SDimitry Andric /* ========================================================================== 3731fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.ub) 3732fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt) 3733fe6060f1SDimitry Andric Instruction Type: CVI_VX 3734fe6060f1SDimitry Andric Execution Slots: SLOT23 3735fe6060f1SDimitry Andric ========================================================================== */ 3736fe6060f1SDimitry Andric 3737*0eae32dcSDimitry Andric #define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt) 3738fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3739fe6060f1SDimitry Andric 3740fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3741fe6060f1SDimitry Andric /* ========================================================================== 3742fe6060f1SDimitry Andric Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.ub) 3743fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 3744fe6060f1SDimitry Andric Instruction Type: CVI_VX 3745fe6060f1SDimitry Andric Execution Slots: SLOT23 3746fe6060f1SDimitry Andric ========================================================================== */ 3747fe6060f1SDimitry Andric 3748*0eae32dcSDimitry Andric #define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt) 3749fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3750fe6060f1SDimitry Andric 3751fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3752fe6060f1SDimitry Andric /* ========================================================================== 3753fe6060f1SDimitry Andric Assembly Syntax: Vxx32+=vmpyo(Vu32.w,Vv32.h) 3754fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 3755fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 3756fe6060f1SDimitry Andric Execution Slots: SLOT23 3757fe6060f1SDimitry Andric ========================================================================== */ 3758fe6060f1SDimitry Andric 3759*0eae32dcSDimitry Andric #define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv) 3760fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3761fe6060f1SDimitry Andric 3762fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3763fe6060f1SDimitry Andric /* ========================================================================== 3764fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vround(Vu32.uh,Vv32.uh):sat 3765fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) 3766fe6060f1SDimitry Andric Instruction Type: CVI_VS 3767fe6060f1SDimitry Andric Execution Slots: SLOT0123 3768fe6060f1SDimitry Andric ========================================================================== */ 3769fe6060f1SDimitry Andric 3770*0eae32dcSDimitry Andric #define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv) 3771fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3772fe6060f1SDimitry Andric 3773fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3774fe6060f1SDimitry Andric /* ========================================================================== 3775fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vround(Vu32.uw,Vv32.uw):sat 3776fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) 3777fe6060f1SDimitry Andric Instruction Type: CVI_VS 3778fe6060f1SDimitry Andric Execution Slots: SLOT0123 3779fe6060f1SDimitry Andric ========================================================================== */ 3780fe6060f1SDimitry Andric 3781*0eae32dcSDimitry Andric #define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv) 3782fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3783fe6060f1SDimitry Andric 3784fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3785fe6060f1SDimitry Andric /* ========================================================================== 3786fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vsat(Vu32.uw,Vv32.uw) 3787fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) 3788fe6060f1SDimitry Andric Instruction Type: CVI_VA 3789fe6060f1SDimitry Andric Execution Slots: SLOT0123 3790fe6060f1SDimitry Andric ========================================================================== */ 3791fe6060f1SDimitry Andric 3792*0eae32dcSDimitry Andric #define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv) 3793fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3794fe6060f1SDimitry Andric 3795fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3796fe6060f1SDimitry Andric /* ========================================================================== 3797fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b):sat 3798fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) 3799fe6060f1SDimitry Andric Instruction Type: CVI_VA 3800fe6060f1SDimitry Andric Execution Slots: SLOT0123 3801fe6060f1SDimitry Andric ========================================================================== */ 3802fe6060f1SDimitry Andric 3803*0eae32dcSDimitry Andric #define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv) 3804fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3805fe6060f1SDimitry Andric 3806fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3807fe6060f1SDimitry Andric /* ========================================================================== 3808fe6060f1SDimitry Andric Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat 3809fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 3810fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3811fe6060f1SDimitry Andric Execution Slots: SLOT0123 3812fe6060f1SDimitry Andric ========================================================================== */ 3813fe6060f1SDimitry Andric 3814*0eae32dcSDimitry Andric #define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv) 3815fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3816fe6060f1SDimitry Andric 3817fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3818fe6060f1SDimitry Andric /* ========================================================================== 3819fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry 3820fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) 3821fe6060f1SDimitry Andric Instruction Type: CVI_VA 3822fe6060f1SDimitry Andric Execution Slots: SLOT0123 3823fe6060f1SDimitry Andric ========================================================================== */ 3824fe6060f1SDimitry Andric 3825*0eae32dcSDimitry Andric #define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx) 3826fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3827fe6060f1SDimitry Andric 3828fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3829fe6060f1SDimitry Andric /* ========================================================================== 3830fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.b):sat 3831fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) 3832fe6060f1SDimitry Andric Instruction Type: CVI_VA 3833fe6060f1SDimitry Andric Execution Slots: SLOT0123 3834fe6060f1SDimitry Andric ========================================================================== */ 3835fe6060f1SDimitry Andric 3836*0eae32dcSDimitry Andric #define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv) 3837fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3838fe6060f1SDimitry Andric 3839fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3840fe6060f1SDimitry Andric /* ========================================================================== 3841fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat 3842fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) 3843fe6060f1SDimitry Andric Instruction Type: CVI_VA 3844fe6060f1SDimitry Andric Execution Slots: SLOT0123 3845fe6060f1SDimitry Andric ========================================================================== */ 3846fe6060f1SDimitry Andric 3847*0eae32dcSDimitry Andric #define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv) 3848fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3849fe6060f1SDimitry Andric 3850fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 62 3851fe6060f1SDimitry Andric /* ========================================================================== 3852fe6060f1SDimitry Andric Assembly Syntax: Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat 3853fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) 3854fe6060f1SDimitry Andric Instruction Type: CVI_VA_DV 3855fe6060f1SDimitry Andric Execution Slots: SLOT0123 3856fe6060f1SDimitry Andric ========================================================================== */ 3857fe6060f1SDimitry Andric 3858*0eae32dcSDimitry Andric #define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv) 3859fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 62 */ 3860fe6060f1SDimitry Andric 3861fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3862fe6060f1SDimitry Andric /* ========================================================================== 3863fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vabs(Vu32.b) 3864fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu) 3865fe6060f1SDimitry Andric Instruction Type: CVI_VA 3866fe6060f1SDimitry Andric Execution Slots: SLOT0123 3867fe6060f1SDimitry Andric ========================================================================== */ 3868fe6060f1SDimitry Andric 3869*0eae32dcSDimitry Andric #define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu) 3870fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3871fe6060f1SDimitry Andric 3872fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3873fe6060f1SDimitry Andric /* ========================================================================== 3874fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vabs(Vu32.b):sat 3875fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu) 3876fe6060f1SDimitry Andric Instruction Type: CVI_VA 3877fe6060f1SDimitry Andric Execution Slots: SLOT0123 3878fe6060f1SDimitry Andric ========================================================================== */ 3879fe6060f1SDimitry Andric 3880*0eae32dcSDimitry Andric #define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu) 3881fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3882fe6060f1SDimitry Andric 3883fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3884fe6060f1SDimitry Andric /* ========================================================================== 3885fe6060f1SDimitry Andric Assembly Syntax: Vx32.h+=vasl(Vu32.h,Rt32) 3886fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 3887fe6060f1SDimitry Andric Instruction Type: CVI_VS 3888fe6060f1SDimitry Andric Execution Slots: SLOT0123 3889fe6060f1SDimitry Andric ========================================================================== */ 3890fe6060f1SDimitry Andric 3891*0eae32dcSDimitry Andric #define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt) 3892fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3893fe6060f1SDimitry Andric 3894fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3895fe6060f1SDimitry Andric /* ========================================================================== 3896fe6060f1SDimitry Andric Assembly Syntax: Vx32.h+=vasr(Vu32.h,Rt32) 3897fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 3898fe6060f1SDimitry Andric Instruction Type: CVI_VS 3899fe6060f1SDimitry Andric Execution Slots: SLOT0123 3900fe6060f1SDimitry Andric ========================================================================== */ 3901fe6060f1SDimitry Andric 3902*0eae32dcSDimitry Andric #define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt) 3903fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3904fe6060f1SDimitry Andric 3905fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3906fe6060f1SDimitry Andric /* ========================================================================== 3907fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat 3908fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 3909fe6060f1SDimitry Andric Instruction Type: CVI_VS 3910fe6060f1SDimitry Andric Execution Slots: SLOT0123 3911fe6060f1SDimitry Andric ========================================================================== */ 3912fe6060f1SDimitry Andric 3913*0eae32dcSDimitry Andric #define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt) 3914fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3915fe6060f1SDimitry Andric 3916fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3917fe6060f1SDimitry Andric /* ========================================================================== 3918fe6060f1SDimitry Andric Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat 3919fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 3920fe6060f1SDimitry Andric Instruction Type: CVI_VS 3921fe6060f1SDimitry Andric Execution Slots: SLOT0123 3922fe6060f1SDimitry Andric ========================================================================== */ 3923fe6060f1SDimitry Andric 3924*0eae32dcSDimitry Andric #define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt) 3925fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3926fe6060f1SDimitry Andric 3927fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3928fe6060f1SDimitry Andric /* ========================================================================== 3929fe6060f1SDimitry Andric Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat 3930fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) 3931fe6060f1SDimitry Andric Instruction Type: CVI_VS 3932fe6060f1SDimitry Andric Execution Slots: SLOT0123 3933fe6060f1SDimitry Andric ========================================================================== */ 3934fe6060f1SDimitry Andric 3935*0eae32dcSDimitry Andric #define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt) 3936fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3937fe6060f1SDimitry Andric 3938fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3939fe6060f1SDimitry Andric /* ========================================================================== 3940fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b) 3941fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) 3942fe6060f1SDimitry Andric Instruction Type: CVI_VA 3943fe6060f1SDimitry Andric Execution Slots: SLOT0123 3944fe6060f1SDimitry Andric ========================================================================== */ 3945fe6060f1SDimitry Andric 3946*0eae32dcSDimitry Andric #define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv) 3947fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3948fe6060f1SDimitry Andric 3949fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3950fe6060f1SDimitry Andric /* ========================================================================== 3951fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b):rnd 3952fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv) 3953fe6060f1SDimitry Andric Instruction Type: CVI_VA 3954fe6060f1SDimitry Andric Execution Slots: SLOT0123 3955fe6060f1SDimitry Andric ========================================================================== */ 3956fe6060f1SDimitry Andric 3957*0eae32dcSDimitry Andric #define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv) 3958fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3959fe6060f1SDimitry Andric 3960fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3961fe6060f1SDimitry Andric /* ========================================================================== 3962fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw) 3963fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) 3964fe6060f1SDimitry Andric Instruction Type: CVI_VA 3965fe6060f1SDimitry Andric Execution Slots: SLOT0123 3966fe6060f1SDimitry Andric ========================================================================== */ 3967fe6060f1SDimitry Andric 3968*0eae32dcSDimitry Andric #define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv) 3969fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3970fe6060f1SDimitry Andric 3971fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3972fe6060f1SDimitry Andric /* ========================================================================== 3973fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd 3974fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv) 3975fe6060f1SDimitry Andric Instruction Type: CVI_VA 3976fe6060f1SDimitry Andric Execution Slots: SLOT0123 3977fe6060f1SDimitry Andric ========================================================================== */ 3978fe6060f1SDimitry Andric 3979*0eae32dcSDimitry Andric #define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv) 3980fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3981fe6060f1SDimitry Andric 3982fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3983fe6060f1SDimitry Andric /* ========================================================================== 3984fe6060f1SDimitry Andric Assembly Syntax: Vdd32=#0 3985fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero() 3986fe6060f1SDimitry Andric Instruction Type: MAPPING 3987fe6060f1SDimitry Andric Execution Slots: SLOT0123 3988fe6060f1SDimitry Andric ========================================================================== */ 3989fe6060f1SDimitry Andric 3990*0eae32dcSDimitry Andric #define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)() 3991fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 3992fe6060f1SDimitry Andric 3993fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 3994fe6060f1SDimitry Andric /* ========================================================================== 3995fe6060f1SDimitry Andric Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vv32.h).h 3996fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) 3997fe6060f1SDimitry Andric Instruction Type: CVI_GATHER 3998fe6060f1SDimitry Andric Execution Slots: SLOT01 3999fe6060f1SDimitry Andric ========================================================================== */ 4000fe6060f1SDimitry Andric 4001*0eae32dcSDimitry Andric #define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv) 4002fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4003fe6060f1SDimitry Andric 4004fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4005fe6060f1SDimitry Andric /* ========================================================================== 4006fe6060f1SDimitry Andric Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h 4007fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) 4008fe6060f1SDimitry Andric Instruction Type: CVI_GATHER 4009fe6060f1SDimitry Andric Execution Slots: SLOT01 4010fe6060f1SDimitry Andric ========================================================================== */ 4011fe6060f1SDimitry Andric 4012*0eae32dcSDimitry Andric #define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) 4013fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4014fe6060f1SDimitry Andric 4015fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4016fe6060f1SDimitry Andric /* ========================================================================== 4017fe6060f1SDimitry Andric Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h 4018fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) 4019fe6060f1SDimitry Andric Instruction Type: CVI_GATHER_DV 4020fe6060f1SDimitry Andric Execution Slots: SLOT01 4021fe6060f1SDimitry Andric ========================================================================== */ 4022fe6060f1SDimitry Andric 4023*0eae32dcSDimitry Andric #define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv) 4024fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4025fe6060f1SDimitry Andric 4026fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4027fe6060f1SDimitry Andric /* ========================================================================== 4028fe6060f1SDimitry Andric Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h 4029fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) 4030fe6060f1SDimitry Andric Instruction Type: CVI_GATHER_DV 4031fe6060f1SDimitry Andric Execution Slots: SLOT01 4032fe6060f1SDimitry Andric ========================================================================== */ 4033fe6060f1SDimitry Andric 4034*0eae32dcSDimitry Andric #define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv) 4035fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4036fe6060f1SDimitry Andric 4037fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4038fe6060f1SDimitry Andric /* ========================================================================== 4039fe6060f1SDimitry Andric Assembly Syntax: vtmp.w=vgather(Rt32,Mu2,Vv32.w).w 4040fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) 4041fe6060f1SDimitry Andric Instruction Type: CVI_GATHER 4042fe6060f1SDimitry Andric Execution Slots: SLOT01 4043fe6060f1SDimitry Andric ========================================================================== */ 4044fe6060f1SDimitry Andric 4045*0eae32dcSDimitry Andric #define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv) 4046fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4047fe6060f1SDimitry Andric 4048fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4049fe6060f1SDimitry Andric /* ========================================================================== 4050fe6060f1SDimitry Andric Assembly Syntax: if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w 4051fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) 4052fe6060f1SDimitry Andric Instruction Type: CVI_GATHER 4053fe6060f1SDimitry Andric Execution Slots: SLOT01 4054fe6060f1SDimitry Andric ========================================================================== */ 4055fe6060f1SDimitry Andric 4056*0eae32dcSDimitry Andric #define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) 4057fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4058fe6060f1SDimitry Andric 4059fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4060fe6060f1SDimitry Andric /* ========================================================================== 4061fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=vlut4(Vu32.uh,Rtt32.h) 4062fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt) 4063fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4064fe6060f1SDimitry Andric Execution Slots: SLOT2 4065fe6060f1SDimitry Andric ========================================================================== */ 4066fe6060f1SDimitry Andric 4067*0eae32dcSDimitry Andric #define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt) 4068fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4069fe6060f1SDimitry Andric 4070fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4071fe6060f1SDimitry Andric /* ========================================================================== 4072fe6060f1SDimitry Andric Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.ub) 4073fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt) 4074fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4075fe6060f1SDimitry Andric Execution Slots: SLOT23 4076fe6060f1SDimitry Andric ========================================================================== */ 4077fe6060f1SDimitry Andric 4078*0eae32dcSDimitry Andric #define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt) 4079fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4080fe6060f1SDimitry Andric 4081fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4082fe6060f1SDimitry Andric /* ========================================================================== 4083fe6060f1SDimitry Andric Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub) 4084fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) 4085fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4086fe6060f1SDimitry Andric Execution Slots: SLOT23 4087fe6060f1SDimitry Andric ========================================================================== */ 4088fe6060f1SDimitry Andric 4089*0eae32dcSDimitry Andric #define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt) 4090fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4091fe6060f1SDimitry Andric 4092fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4093fe6060f1SDimitry Andric /* ========================================================================== 4094fe6060f1SDimitry Andric Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat 4095fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) 4096fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4097fe6060f1SDimitry Andric Execution Slots: SLOT2 4098fe6060f1SDimitry Andric ========================================================================== */ 4099fe6060f1SDimitry Andric 4100*0eae32dcSDimitry Andric #define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt) 4101fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4102fe6060f1SDimitry Andric 4103fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4104fe6060f1SDimitry Andric /* ========================================================================== 4105fe6060f1SDimitry Andric Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat 4106fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) 4107fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4108fe6060f1SDimitry Andric Execution Slots: SLOT2 4109fe6060f1SDimitry Andric ========================================================================== */ 4110fe6060f1SDimitry Andric 4111*0eae32dcSDimitry Andric #define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt) 4112fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4113fe6060f1SDimitry Andric 4114fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4115fe6060f1SDimitry Andric /* ========================================================================== 4116fe6060f1SDimitry Andric Assembly Syntax: Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat 4117fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) 4118fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4119fe6060f1SDimitry Andric Execution Slots: SLOT2 4120fe6060f1SDimitry Andric ========================================================================== */ 4121fe6060f1SDimitry Andric 4122*0eae32dcSDimitry Andric #define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt) 4123fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4124fe6060f1SDimitry Andric 4125fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4126fe6060f1SDimitry Andric /* ========================================================================== 4127fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h) 4128fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) 4129fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4130fe6060f1SDimitry Andric Execution Slots: SLOT23 4131fe6060f1SDimitry Andric ========================================================================== */ 4132fe6060f1SDimitry Andric 4133*0eae32dcSDimitry Andric #define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt) 4134fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4135fe6060f1SDimitry Andric 4136fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4137fe6060f1SDimitry Andric /* ========================================================================== 4138fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vmpye(Vu32.uh,Rt32.uh) 4139fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt) 4140fe6060f1SDimitry Andric Instruction Type: CVI_VX 4141fe6060f1SDimitry Andric Execution Slots: SLOT23 4142fe6060f1SDimitry Andric ========================================================================== */ 4143fe6060f1SDimitry Andric 4144*0eae32dcSDimitry Andric #define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt) 4145fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4146fe6060f1SDimitry Andric 4147fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4148fe6060f1SDimitry Andric /* ========================================================================== 4149fe6060f1SDimitry Andric Assembly Syntax: Vx32.uw+=vmpye(Vu32.uh,Rt32.uh) 4150fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) 4151fe6060f1SDimitry Andric Instruction Type: CVI_VX 4152fe6060f1SDimitry Andric Execution Slots: SLOT23 4153fe6060f1SDimitry Andric ========================================================================== */ 4154fe6060f1SDimitry Andric 4155*0eae32dcSDimitry Andric #define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt) 4156fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4157fe6060f1SDimitry Andric 4158fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4159fe6060f1SDimitry Andric /* ========================================================================== 4160fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=vnavg(Vu32.b,Vv32.b) 4161fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) 4162fe6060f1SDimitry Andric Instruction Type: CVI_VA 4163fe6060f1SDimitry Andric Execution Slots: SLOT0123 4164fe6060f1SDimitry Andric ========================================================================== */ 4165fe6060f1SDimitry Andric 4166*0eae32dcSDimitry Andric #define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv) 4167fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4168fe6060f1SDimitry Andric 4169fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4170fe6060f1SDimitry Andric /* ========================================================================== 4171fe6060f1SDimitry Andric Assembly Syntax: Vd32.b=prefixsum(Qv4) 4172fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv) 4173fe6060f1SDimitry Andric Instruction Type: CVI_VS 4174fe6060f1SDimitry Andric Execution Slots: SLOT0123 4175fe6060f1SDimitry Andric ========================================================================== */ 4176fe6060f1SDimitry Andric 4177*0eae32dcSDimitry Andric #define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) 4178fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4179fe6060f1SDimitry Andric 4180fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4181fe6060f1SDimitry Andric /* ========================================================================== 4182fe6060f1SDimitry Andric Assembly Syntax: Vd32.h=prefixsum(Qv4) 4183fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv) 4184fe6060f1SDimitry Andric Instruction Type: CVI_VS 4185fe6060f1SDimitry Andric Execution Slots: SLOT0123 4186fe6060f1SDimitry Andric ========================================================================== */ 4187fe6060f1SDimitry Andric 4188*0eae32dcSDimitry Andric #define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) 4189fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4190fe6060f1SDimitry Andric 4191fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4192fe6060f1SDimitry Andric /* ========================================================================== 4193fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=prefixsum(Qv4) 4194fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv) 4195fe6060f1SDimitry Andric Instruction Type: CVI_VS 4196fe6060f1SDimitry Andric Execution Slots: SLOT0123 4197fe6060f1SDimitry Andric ========================================================================== */ 4198fe6060f1SDimitry Andric 4199*0eae32dcSDimitry Andric #define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) 4200fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4201fe6060f1SDimitry Andric 4202fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4203fe6060f1SDimitry Andric /* ========================================================================== 4204fe6060f1SDimitry Andric Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h=Vw32 4205fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) 4206fe6060f1SDimitry Andric Instruction Type: CVI_SCATTER 4207fe6060f1SDimitry Andric Execution Slots: SLOT0 4208fe6060f1SDimitry Andric ========================================================================== */ 4209fe6060f1SDimitry Andric 4210*0eae32dcSDimitry Andric #define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw) 4211fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4212fe6060f1SDimitry Andric 4213fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4214fe6060f1SDimitry Andric /* ========================================================================== 4215fe6060f1SDimitry Andric Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h+=Vw32 4216fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) 4217fe6060f1SDimitry Andric Instruction Type: CVI_SCATTER 4218fe6060f1SDimitry Andric Execution Slots: SLOT0 4219fe6060f1SDimitry Andric ========================================================================== */ 4220fe6060f1SDimitry Andric 4221*0eae32dcSDimitry Andric #define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw) 4222fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4223fe6060f1SDimitry Andric 4224fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4225fe6060f1SDimitry Andric /* ========================================================================== 4226fe6060f1SDimitry Andric Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32 4227fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) 4228fe6060f1SDimitry Andric Instruction Type: CVI_SCATTER 4229fe6060f1SDimitry Andric Execution Slots: SLOT0 4230fe6060f1SDimitry Andric ========================================================================== */ 4231fe6060f1SDimitry Andric 4232*0eae32dcSDimitry Andric #define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) 4233fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4234fe6060f1SDimitry Andric 4235fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4236fe6060f1SDimitry Andric /* ========================================================================== 4237fe6060f1SDimitry Andric Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 4238fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) 4239fe6060f1SDimitry Andric Instruction Type: CVI_SCATTER_DV 4240fe6060f1SDimitry Andric Execution Slots: SLOT0 4241fe6060f1SDimitry Andric ========================================================================== */ 4242fe6060f1SDimitry Andric 4243*0eae32dcSDimitry Andric #define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw) 4244fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4245fe6060f1SDimitry Andric 4246fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4247fe6060f1SDimitry Andric /* ========================================================================== 4248fe6060f1SDimitry Andric Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32 4249fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) 4250fe6060f1SDimitry Andric Instruction Type: CVI_SCATTER_DV 4251fe6060f1SDimitry Andric Execution Slots: SLOT0 4252fe6060f1SDimitry Andric ========================================================================== */ 4253fe6060f1SDimitry Andric 4254*0eae32dcSDimitry Andric #define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw) 4255fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4256fe6060f1SDimitry Andric 4257fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4258fe6060f1SDimitry Andric /* ========================================================================== 4259fe6060f1SDimitry Andric Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 4260fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) 4261fe6060f1SDimitry Andric Instruction Type: CVI_SCATTER_DV 4262fe6060f1SDimitry Andric Execution Slots: SLOT0 4263fe6060f1SDimitry Andric ========================================================================== */ 4264fe6060f1SDimitry Andric 4265*0eae32dcSDimitry Andric #define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw) 4266fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4267fe6060f1SDimitry Andric 4268fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4269fe6060f1SDimitry Andric /* ========================================================================== 4270fe6060f1SDimitry Andric Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w=Vw32 4271fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) 4272fe6060f1SDimitry Andric Instruction Type: CVI_SCATTER 4273fe6060f1SDimitry Andric Execution Slots: SLOT0 4274fe6060f1SDimitry Andric ========================================================================== */ 4275fe6060f1SDimitry Andric 4276*0eae32dcSDimitry Andric #define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw) 4277fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4278fe6060f1SDimitry Andric 4279fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4280fe6060f1SDimitry Andric /* ========================================================================== 4281fe6060f1SDimitry Andric Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w+=Vw32 4282fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) 4283fe6060f1SDimitry Andric Instruction Type: CVI_SCATTER 4284fe6060f1SDimitry Andric Execution Slots: SLOT0 4285fe6060f1SDimitry Andric ========================================================================== */ 4286fe6060f1SDimitry Andric 4287*0eae32dcSDimitry Andric #define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw) 4288fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4289fe6060f1SDimitry Andric 4290fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 65 4291fe6060f1SDimitry Andric /* ========================================================================== 4292fe6060f1SDimitry Andric Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32 4293fe6060f1SDimitry Andric C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) 4294fe6060f1SDimitry Andric Instruction Type: CVI_SCATTER 4295fe6060f1SDimitry Andric Execution Slots: SLOT0 4296fe6060f1SDimitry Andric ========================================================================== */ 4297fe6060f1SDimitry Andric 4298*0eae32dcSDimitry Andric #define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) 4299fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 65 */ 4300fe6060f1SDimitry Andric 4301fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 66 4302fe6060f1SDimitry Andric /* ========================================================================== 4303fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat 4304fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs) 4305fe6060f1SDimitry Andric Instruction Type: CVI_VA 4306fe6060f1SDimitry Andric Execution Slots: SLOT0123 4307fe6060f1SDimitry Andric ========================================================================== */ 4308fe6060f1SDimitry Andric 4309*0eae32dcSDimitry Andric #define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1)) 4310fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 66 */ 4311fe6060f1SDimitry Andric 4312fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 66 4313fe6060f1SDimitry Andric /* ========================================================================== 4314fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w=vasrinto(Vu32.w,Vv32.w) 4315fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 4316fe6060f1SDimitry Andric Instruction Type: CVI_VP_VS 4317fe6060f1SDimitry Andric Execution Slots: SLOT0123 4318fe6060f1SDimitry Andric ========================================================================== */ 4319fe6060f1SDimitry Andric 4320*0eae32dcSDimitry Andric #define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv) 4321fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 66 */ 4322fe6060f1SDimitry Andric 4323fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 66 4324fe6060f1SDimitry Andric /* ========================================================================== 4325fe6060f1SDimitry Andric Assembly Syntax: Vd32.uw=vrotr(Vu32.uw,Vv32.uw) 4326fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) 4327fe6060f1SDimitry Andric Instruction Type: CVI_VS 4328fe6060f1SDimitry Andric Execution Slots: SLOT0123 4329fe6060f1SDimitry Andric ========================================================================== */ 4330fe6060f1SDimitry Andric 4331*0eae32dcSDimitry Andric #define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv) 4332fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 66 */ 4333fe6060f1SDimitry Andric 4334fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 66 4335fe6060f1SDimitry Andric /* ========================================================================== 4336fe6060f1SDimitry Andric Assembly Syntax: Vd32.w=vsatdw(Vu32.w,Vv32.w) 4337fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv) 4338fe6060f1SDimitry Andric Instruction Type: CVI_VA 4339fe6060f1SDimitry Andric Execution Slots: SLOT0123 4340fe6060f1SDimitry Andric ========================================================================== */ 4341fe6060f1SDimitry Andric 4342*0eae32dcSDimitry Andric #define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv) 4343fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 66 */ 4344fe6060f1SDimitry Andric 4345fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 68 4346fe6060f1SDimitry Andric /* ========================================================================== 4347fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h 4348fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) 4349fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4350fe6060f1SDimitry Andric Execution Slots: SLOT23 4351fe6060f1SDimitry Andric ========================================================================== */ 4352fe6060f1SDimitry Andric 4353*0eae32dcSDimitry Andric #define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2) 4354fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4355fe6060f1SDimitry Andric 4356fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 68 4357fe6060f1SDimitry Andric /* ========================================================================== 4358fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h 4359fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) 4360fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4361fe6060f1SDimitry Andric Execution Slots: SLOT23 4362fe6060f1SDimitry Andric ========================================================================== */ 4363fe6060f1SDimitry Andric 4364*0eae32dcSDimitry Andric #define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2) 4365fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4366fe6060f1SDimitry Andric 4367fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 68 4368fe6060f1SDimitry Andric /* ========================================================================== 4369fe6060f1SDimitry Andric Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v 4370fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) 4371fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4372fe6060f1SDimitry Andric Execution Slots: SLOT23 4373fe6060f1SDimitry Andric ========================================================================== */ 4374fe6060f1SDimitry Andric 4375*0eae32dcSDimitry Andric #define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2) 4376fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4377fe6060f1SDimitry Andric 4378fe6060f1SDimitry Andric #if __HVX_ARCH__ >= 68 4379fe6060f1SDimitry Andric /* ========================================================================== 4380fe6060f1SDimitry Andric Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v 4381fe6060f1SDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) 4382fe6060f1SDimitry Andric Instruction Type: CVI_VX_DV 4383fe6060f1SDimitry Andric Execution Slots: SLOT23 4384fe6060f1SDimitry Andric ========================================================================== */ 4385fe6060f1SDimitry Andric 4386*0eae32dcSDimitry Andric #define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2) 4387fe6060f1SDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4388fe6060f1SDimitry Andric 4389*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4390*0eae32dcSDimitry Andric /* ========================================================================== 4391*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vabs(Vu32.hf) 4392*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vabs_Vhf(HVX_Vector Vu) 4393*0eae32dcSDimitry Andric Instruction Type: CVI_VX_LATE 4394*0eae32dcSDimitry Andric Execution Slots: SLOT23 4395*0eae32dcSDimitry Andric ========================================================================== */ 4396*0eae32dcSDimitry Andric 4397*0eae32dcSDimitry Andric #define Q6_Vhf_vabs_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_hf)(Vu) 4398*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4399*0eae32dcSDimitry Andric 4400*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4401*0eae32dcSDimitry Andric /* ========================================================================== 4402*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vabs(Vu32.sf) 4403*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vabs_Vsf(HVX_Vector Vu) 4404*0eae32dcSDimitry Andric Instruction Type: CVI_VX_LATE 4405*0eae32dcSDimitry Andric Execution Slots: SLOT23 4406*0eae32dcSDimitry Andric ========================================================================== */ 4407*0eae32dcSDimitry Andric 4408*0eae32dcSDimitry Andric #define Q6_Vsf_vabs_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabs_sf)(Vu) 4409*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4410*0eae32dcSDimitry Andric 4411*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4412*0eae32dcSDimitry Andric /* ========================================================================== 4413*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf16=vadd(Vu32.hf,Vv32.hf) 4414*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4415*0eae32dcSDimitry Andric Instruction Type: CVI_VS 4416*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4417*0eae32dcSDimitry Andric ========================================================================== */ 4418*0eae32dcSDimitry Andric 4419*0eae32dcSDimitry Andric #define Q6_Vqf16_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf)(Vu,Vv) 4420*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4421*0eae32dcSDimitry Andric 4422*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4423*0eae32dcSDimitry Andric /* ========================================================================== 4424*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vadd(Vu32.hf,Vv32.hf) 4425*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4426*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4427*0eae32dcSDimitry Andric Execution Slots: SLOT23 4428*0eae32dcSDimitry Andric ========================================================================== */ 4429*0eae32dcSDimitry Andric 4430*0eae32dcSDimitry Andric #define Q6_Vhf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_hf_hf)(Vu,Vv) 4431*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4432*0eae32dcSDimitry Andric 4433*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4434*0eae32dcSDimitry Andric /* ========================================================================== 4435*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.qf16) 4436*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) 4437*0eae32dcSDimitry Andric Instruction Type: CVI_VS 4438*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4439*0eae32dcSDimitry Andric ========================================================================== */ 4440*0eae32dcSDimitry Andric 4441*0eae32dcSDimitry Andric #define Q6_Vqf16_vadd_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16)(Vu,Vv) 4442*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4443*0eae32dcSDimitry Andric 4444*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4445*0eae32dcSDimitry Andric /* ========================================================================== 4446*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf16=vadd(Vu32.qf16,Vv32.hf) 4447*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vadd_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) 4448*0eae32dcSDimitry Andric Instruction Type: CVI_VS 4449*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4450*0eae32dcSDimitry Andric ========================================================================== */ 4451*0eae32dcSDimitry Andric 4452*0eae32dcSDimitry Andric #define Q6_Vqf16_vadd_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf16_mix)(Vu,Vv) 4453*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4454*0eae32dcSDimitry Andric 4455*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4456*0eae32dcSDimitry Andric /* ========================================================================== 4457*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.qf32) 4458*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) 4459*0eae32dcSDimitry Andric Instruction Type: CVI_VS 4460*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4461*0eae32dcSDimitry Andric ========================================================================== */ 4462*0eae32dcSDimitry Andric 4463*0eae32dcSDimitry Andric #define Q6_Vqf32_vadd_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32)(Vu,Vv) 4464*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4465*0eae32dcSDimitry Andric 4466*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4467*0eae32dcSDimitry Andric /* ========================================================================== 4468*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf32=vadd(Vu32.qf32,Vv32.sf) 4469*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) 4470*0eae32dcSDimitry Andric Instruction Type: CVI_VS 4471*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4472*0eae32dcSDimitry Andric ========================================================================== */ 4473*0eae32dcSDimitry Andric 4474*0eae32dcSDimitry Andric #define Q6_Vqf32_vadd_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_qf32_mix)(Vu,Vv) 4475*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4476*0eae32dcSDimitry Andric 4477*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4478*0eae32dcSDimitry Andric /* ========================================================================== 4479*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf32=vadd(Vu32.sf,Vv32.sf) 4480*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 4481*0eae32dcSDimitry Andric Instruction Type: CVI_VS 4482*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4483*0eae32dcSDimitry Andric ========================================================================== */ 4484*0eae32dcSDimitry Andric 4485*0eae32dcSDimitry Andric #define Q6_Vqf32_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf)(Vu,Vv) 4486*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4487*0eae32dcSDimitry Andric 4488*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4489*0eae32dcSDimitry Andric /* ========================================================================== 4490*0eae32dcSDimitry Andric Assembly Syntax: Vdd32.sf=vadd(Vu32.hf,Vv32.hf) 4491*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vadd_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4492*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4493*0eae32dcSDimitry Andric Execution Slots: SLOT23 4494*0eae32dcSDimitry Andric ========================================================================== */ 4495*0eae32dcSDimitry Andric 4496*0eae32dcSDimitry Andric #define Q6_Wsf_vadd_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_hf)(Vu,Vv) 4497*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4498*0eae32dcSDimitry Andric 4499*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4500*0eae32dcSDimitry Andric /* ========================================================================== 4501*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vadd(Vu32.sf,Vv32.sf) 4502*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vadd_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 4503*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4504*0eae32dcSDimitry Andric Execution Slots: SLOT23 4505*0eae32dcSDimitry Andric ========================================================================== */ 4506*0eae32dcSDimitry Andric 4507*0eae32dcSDimitry Andric #define Q6_Vsf_vadd_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadd_sf_sf)(Vu,Vv) 4508*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4509*0eae32dcSDimitry Andric 4510*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4511*0eae32dcSDimitry Andric /* ========================================================================== 4512*0eae32dcSDimitry Andric Assembly Syntax: Vd32.w=vfmv(Vu32.w) 4513*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vw_vfmv_Vw(HVX_Vector Vu) 4514*0eae32dcSDimitry Andric Instruction Type: CVI_VX_LATE 4515*0eae32dcSDimitry Andric Execution Slots: SLOT23 4516*0eae32dcSDimitry Andric ========================================================================== */ 4517*0eae32dcSDimitry Andric 4518*0eae32dcSDimitry Andric #define Q6_Vw_vfmv_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign_fp)(Vu) 4519*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4520*0eae32dcSDimitry Andric 4521*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4522*0eae32dcSDimitry Andric /* ========================================================================== 4523*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=Vu32.qf16 4524*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Vqf16(HVX_Vector Vu) 4525*0eae32dcSDimitry Andric Instruction Type: CVI_VS 4526*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4527*0eae32dcSDimitry Andric ========================================================================== */ 4528*0eae32dcSDimitry Andric 4529*0eae32dcSDimitry Andric #define Q6_Vhf_equals_Vqf16(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf16)(Vu) 4530*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4531*0eae32dcSDimitry Andric 4532*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4533*0eae32dcSDimitry Andric /* ========================================================================== 4534*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=Vuu32.qf32 4535*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_equals_Wqf32(HVX_VectorPair Vuu) 4536*0eae32dcSDimitry Andric Instruction Type: CVI_VS 4537*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4538*0eae32dcSDimitry Andric ========================================================================== */ 4539*0eae32dcSDimitry Andric 4540*0eae32dcSDimitry Andric #define Q6_Vhf_equals_Wqf32(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_hf_qf32)(Vuu) 4541*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4542*0eae32dcSDimitry Andric 4543*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4544*0eae32dcSDimitry Andric /* ========================================================================== 4545*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=Vu32.qf32 4546*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_equals_Vqf32(HVX_Vector Vu) 4547*0eae32dcSDimitry Andric Instruction Type: CVI_VS 4548*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4549*0eae32dcSDimitry Andric ========================================================================== */ 4550*0eae32dcSDimitry Andric 4551*0eae32dcSDimitry Andric #define Q6_Vsf_equals_Vqf32(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vconv_sf_qf32)(Vu) 4552*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4553*0eae32dcSDimitry Andric 4554*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4555*0eae32dcSDimitry Andric /* ========================================================================== 4556*0eae32dcSDimitry Andric Assembly Syntax: Vd32.b=vcvt(Vu32.hf,Vv32.hf) 4557*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vb_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4558*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4559*0eae32dcSDimitry Andric Execution Slots: SLOT23 4560*0eae32dcSDimitry Andric ========================================================================== */ 4561*0eae32dcSDimitry Andric 4562*0eae32dcSDimitry Andric #define Q6_Vb_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_b_hf)(Vu,Vv) 4563*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4564*0eae32dcSDimitry Andric 4565*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4566*0eae32dcSDimitry Andric /* ========================================================================== 4567*0eae32dcSDimitry Andric Assembly Syntax: Vd32.h=vcvt(Vu32.hf) 4568*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vh_vcvt_Vhf(HVX_Vector Vu) 4569*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4570*0eae32dcSDimitry Andric Execution Slots: SLOT23 4571*0eae32dcSDimitry Andric ========================================================================== */ 4572*0eae32dcSDimitry Andric 4573*0eae32dcSDimitry Andric #define Q6_Vh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_h_hf)(Vu) 4574*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4575*0eae32dcSDimitry Andric 4576*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4577*0eae32dcSDimitry Andric /* ========================================================================== 4578*0eae32dcSDimitry Andric Assembly Syntax: Vdd32.hf=vcvt(Vu32.b) 4579*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vb(HVX_Vector Vu) 4580*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4581*0eae32dcSDimitry Andric Execution Slots: SLOT23 4582*0eae32dcSDimitry Andric ========================================================================== */ 4583*0eae32dcSDimitry Andric 4584*0eae32dcSDimitry Andric #define Q6_Whf_vcvt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_b)(Vu) 4585*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4586*0eae32dcSDimitry Andric 4587*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4588*0eae32dcSDimitry Andric /* ========================================================================== 4589*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vcvt(Vu32.h) 4590*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vh(HVX_Vector Vu) 4591*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4592*0eae32dcSDimitry Andric Execution Slots: SLOT23 4593*0eae32dcSDimitry Andric ========================================================================== */ 4594*0eae32dcSDimitry Andric 4595*0eae32dcSDimitry Andric #define Q6_Vhf_vcvt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_h)(Vu) 4596*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4597*0eae32dcSDimitry Andric 4598*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4599*0eae32dcSDimitry Andric /* ========================================================================== 4600*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vcvt(Vu32.sf,Vv32.sf) 4601*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 4602*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4603*0eae32dcSDimitry Andric Execution Slots: SLOT23 4604*0eae32dcSDimitry Andric ========================================================================== */ 4605*0eae32dcSDimitry Andric 4606*0eae32dcSDimitry Andric #define Q6_Vhf_vcvt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_sf)(Vu,Vv) 4607*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4608*0eae32dcSDimitry Andric 4609*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4610*0eae32dcSDimitry Andric /* ========================================================================== 4611*0eae32dcSDimitry Andric Assembly Syntax: Vdd32.hf=vcvt(Vu32.ub) 4612*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Whf_vcvt_Vub(HVX_Vector Vu) 4613*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4614*0eae32dcSDimitry Andric Execution Slots: SLOT23 4615*0eae32dcSDimitry Andric ========================================================================== */ 4616*0eae32dcSDimitry Andric 4617*0eae32dcSDimitry Andric #define Q6_Whf_vcvt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_ub)(Vu) 4618*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4619*0eae32dcSDimitry Andric 4620*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4621*0eae32dcSDimitry Andric /* ========================================================================== 4622*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vcvt(Vu32.uh) 4623*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vcvt_Vuh(HVX_Vector Vu) 4624*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4625*0eae32dcSDimitry Andric Execution Slots: SLOT23 4626*0eae32dcSDimitry Andric ========================================================================== */ 4627*0eae32dcSDimitry Andric 4628*0eae32dcSDimitry Andric #define Q6_Vhf_vcvt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_hf_uh)(Vu) 4629*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4630*0eae32dcSDimitry Andric 4631*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4632*0eae32dcSDimitry Andric /* ========================================================================== 4633*0eae32dcSDimitry Andric Assembly Syntax: Vdd32.sf=vcvt(Vu32.hf) 4634*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vcvt_Vhf(HVX_Vector Vu) 4635*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4636*0eae32dcSDimitry Andric Execution Slots: SLOT23 4637*0eae32dcSDimitry Andric ========================================================================== */ 4638*0eae32dcSDimitry Andric 4639*0eae32dcSDimitry Andric #define Q6_Wsf_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_sf_hf)(Vu) 4640*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4641*0eae32dcSDimitry Andric 4642*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4643*0eae32dcSDimitry Andric /* ========================================================================== 4644*0eae32dcSDimitry Andric Assembly Syntax: Vd32.ub=vcvt(Vu32.hf,Vv32.hf) 4645*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vcvt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4646*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4647*0eae32dcSDimitry Andric Execution Slots: SLOT23 4648*0eae32dcSDimitry Andric ========================================================================== */ 4649*0eae32dcSDimitry Andric 4650*0eae32dcSDimitry Andric #define Q6_Vub_vcvt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_ub_hf)(Vu,Vv) 4651*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4652*0eae32dcSDimitry Andric 4653*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4654*0eae32dcSDimitry Andric /* ========================================================================== 4655*0eae32dcSDimitry Andric Assembly Syntax: Vd32.uh=vcvt(Vu32.hf) 4656*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcvt_Vhf(HVX_Vector Vu) 4657*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4658*0eae32dcSDimitry Andric Execution Slots: SLOT23 4659*0eae32dcSDimitry Andric ========================================================================== */ 4660*0eae32dcSDimitry Andric 4661*0eae32dcSDimitry Andric #define Q6_Vuh_vcvt_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcvt_uh_hf)(Vu) 4662*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4663*0eae32dcSDimitry Andric 4664*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4665*0eae32dcSDimitry Andric /* ========================================================================== 4666*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vdmpy(Vu32.hf,Vv32.hf) 4667*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4668*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4669*0eae32dcSDimitry Andric Execution Slots: SLOT23 4670*0eae32dcSDimitry Andric ========================================================================== */ 4671*0eae32dcSDimitry Andric 4672*0eae32dcSDimitry Andric #define Q6_Vsf_vdmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf)(Vu,Vv) 4673*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4674*0eae32dcSDimitry Andric 4675*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4676*0eae32dcSDimitry Andric /* ========================================================================== 4677*0eae32dcSDimitry Andric Assembly Syntax: Vx32.sf+=vdmpy(Vu32.hf,Vv32.hf) 4678*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vdmpyacc_VsfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 4679*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4680*0eae32dcSDimitry Andric Execution Slots: SLOT23 4681*0eae32dcSDimitry Andric ========================================================================== */ 4682*0eae32dcSDimitry Andric 4683*0eae32dcSDimitry Andric #define Q6_Vsf_vdmpyacc_VsfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpy_sf_hf_acc)(Vx,Vu,Vv) 4684*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4685*0eae32dcSDimitry Andric 4686*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4687*0eae32dcSDimitry Andric /* ========================================================================== 4688*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vfmax(Vu32.hf,Vv32.hf) 4689*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4690*0eae32dcSDimitry Andric Instruction Type: CVI_VX_LATE 4691*0eae32dcSDimitry Andric Execution Slots: SLOT23 4692*0eae32dcSDimitry Andric ========================================================================== */ 4693*0eae32dcSDimitry Andric 4694*0eae32dcSDimitry Andric #define Q6_Vhf_vfmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_hf)(Vu,Vv) 4695*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4696*0eae32dcSDimitry Andric 4697*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4698*0eae32dcSDimitry Andric /* ========================================================================== 4699*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vfmax(Vu32.sf,Vv32.sf) 4700*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 4701*0eae32dcSDimitry Andric Instruction Type: CVI_VX_LATE 4702*0eae32dcSDimitry Andric Execution Slots: SLOT23 4703*0eae32dcSDimitry Andric ========================================================================== */ 4704*0eae32dcSDimitry Andric 4705*0eae32dcSDimitry Andric #define Q6_Vsf_vfmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmax_sf)(Vu,Vv) 4706*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4707*0eae32dcSDimitry Andric 4708*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4709*0eae32dcSDimitry Andric /* ========================================================================== 4710*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vfmin(Vu32.hf,Vv32.hf) 4711*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4712*0eae32dcSDimitry Andric Instruction Type: CVI_VX_LATE 4713*0eae32dcSDimitry Andric Execution Slots: SLOT23 4714*0eae32dcSDimitry Andric ========================================================================== */ 4715*0eae32dcSDimitry Andric 4716*0eae32dcSDimitry Andric #define Q6_Vhf_vfmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_hf)(Vu,Vv) 4717*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4718*0eae32dcSDimitry Andric 4719*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4720*0eae32dcSDimitry Andric /* ========================================================================== 4721*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vfmin(Vu32.sf,Vv32.sf) 4722*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 4723*0eae32dcSDimitry Andric Instruction Type: CVI_VX_LATE 4724*0eae32dcSDimitry Andric Execution Slots: SLOT23 4725*0eae32dcSDimitry Andric ========================================================================== */ 4726*0eae32dcSDimitry Andric 4727*0eae32dcSDimitry Andric #define Q6_Vsf_vfmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfmin_sf)(Vu,Vv) 4728*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4729*0eae32dcSDimitry Andric 4730*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4731*0eae32dcSDimitry Andric /* ========================================================================== 4732*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vfneg(Vu32.hf) 4733*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vfneg_Vhf(HVX_Vector Vu) 4734*0eae32dcSDimitry Andric Instruction Type: CVI_VX_LATE 4735*0eae32dcSDimitry Andric Execution Slots: SLOT23 4736*0eae32dcSDimitry Andric ========================================================================== */ 4737*0eae32dcSDimitry Andric 4738*0eae32dcSDimitry Andric #define Q6_Vhf_vfneg_Vhf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_hf)(Vu) 4739*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4740*0eae32dcSDimitry Andric 4741*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4742*0eae32dcSDimitry Andric /* ========================================================================== 4743*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vfneg(Vu32.sf) 4744*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vfneg_Vsf(HVX_Vector Vu) 4745*0eae32dcSDimitry Andric Instruction Type: CVI_VX_LATE 4746*0eae32dcSDimitry Andric Execution Slots: SLOT23 4747*0eae32dcSDimitry Andric ========================================================================== */ 4748*0eae32dcSDimitry Andric 4749*0eae32dcSDimitry Andric #define Q6_Vsf_vfneg_Vsf(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vfneg_sf)(Vu) 4750*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4751*0eae32dcSDimitry Andric 4752*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4753*0eae32dcSDimitry Andric /* ========================================================================== 4754*0eae32dcSDimitry Andric Assembly Syntax: Qd4=vcmp.gt(Vu32.hf,Vv32.hf) 4755*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4756*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4757*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4758*0eae32dcSDimitry Andric ========================================================================== */ 4759*0eae32dcSDimitry Andric 4760*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gt_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf)(Vu,Vv)),-1) 4761*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4762*0eae32dcSDimitry Andric 4763*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4764*0eae32dcSDimitry Andric /* ========================================================================== 4765*0eae32dcSDimitry Andric Assembly Syntax: Qx4&=vcmp.gt(Vu32.hf,Vv32.hf) 4766*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 4767*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4768*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4769*0eae32dcSDimitry Andric ========================================================================== */ 4770*0eae32dcSDimitry Andric 4771*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtand_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 4772*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4773*0eae32dcSDimitry Andric 4774*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4775*0eae32dcSDimitry Andric /* ========================================================================== 4776*0eae32dcSDimitry Andric Assembly Syntax: Qx4|=vcmp.gt(Vu32.hf,Vv32.hf) 4777*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 4778*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4779*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4780*0eae32dcSDimitry Andric ========================================================================== */ 4781*0eae32dcSDimitry Andric 4782*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtor_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 4783*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4784*0eae32dcSDimitry Andric 4785*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4786*0eae32dcSDimitry Andric /* ========================================================================== 4787*0eae32dcSDimitry Andric Assembly Syntax: Qx4^=vcmp.gt(Vu32.hf,Vv32.hf) 4788*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhfVhf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 4789*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4790*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4791*0eae32dcSDimitry Andric ========================================================================== */ 4792*0eae32dcSDimitry Andric 4793*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtxacc_QVhfVhf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgthf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 4794*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4795*0eae32dcSDimitry Andric 4796*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4797*0eae32dcSDimitry Andric /* ========================================================================== 4798*0eae32dcSDimitry Andric Assembly Syntax: Qd4=vcmp.gt(Vu32.sf,Vv32.sf) 4799*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 4800*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4801*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4802*0eae32dcSDimitry Andric ========================================================================== */ 4803*0eae32dcSDimitry Andric 4804*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gt_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf)(Vu,Vv)),-1) 4805*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4806*0eae32dcSDimitry Andric 4807*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4808*0eae32dcSDimitry Andric /* ========================================================================== 4809*0eae32dcSDimitry Andric Assembly Syntax: Qx4&=vcmp.gt(Vu32.sf,Vv32.sf) 4810*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 4811*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4812*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4813*0eae32dcSDimitry Andric ========================================================================== */ 4814*0eae32dcSDimitry Andric 4815*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtand_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 4816*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4817*0eae32dcSDimitry Andric 4818*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4819*0eae32dcSDimitry Andric /* ========================================================================== 4820*0eae32dcSDimitry Andric Assembly Syntax: Qx4|=vcmp.gt(Vu32.sf,Vv32.sf) 4821*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 4822*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4823*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4824*0eae32dcSDimitry Andric ========================================================================== */ 4825*0eae32dcSDimitry Andric 4826*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtor_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 4827*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4828*0eae32dcSDimitry Andric 4829*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4830*0eae32dcSDimitry Andric /* ========================================================================== 4831*0eae32dcSDimitry Andric Assembly Syntax: Qx4^=vcmp.gt(Vu32.sf,Vv32.sf) 4832*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVsfVsf(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) 4833*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4834*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4835*0eae32dcSDimitry Andric ========================================================================== */ 4836*0eae32dcSDimitry Andric 4837*0eae32dcSDimitry Andric #define Q6_Q_vcmp_gtxacc_QVsfVsf(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtsf_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) 4838*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4839*0eae32dcSDimitry Andric 4840*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4841*0eae32dcSDimitry Andric /* ========================================================================== 4842*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vmax(Vu32.hf,Vv32.hf) 4843*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmax_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4844*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4845*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4846*0eae32dcSDimitry Andric ========================================================================== */ 4847*0eae32dcSDimitry Andric 4848*0eae32dcSDimitry Andric #define Q6_Vhf_vmax_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_hf)(Vu,Vv) 4849*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4850*0eae32dcSDimitry Andric 4851*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4852*0eae32dcSDimitry Andric /* ========================================================================== 4853*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vmax(Vu32.sf,Vv32.sf) 4854*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmax_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 4855*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4856*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4857*0eae32dcSDimitry Andric ========================================================================== */ 4858*0eae32dcSDimitry Andric 4859*0eae32dcSDimitry Andric #define Q6_Vsf_vmax_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmax_sf)(Vu,Vv) 4860*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4861*0eae32dcSDimitry Andric 4862*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4863*0eae32dcSDimitry Andric /* ========================================================================== 4864*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vmin(Vu32.hf,Vv32.hf) 4865*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmin_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4866*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4867*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4868*0eae32dcSDimitry Andric ========================================================================== */ 4869*0eae32dcSDimitry Andric 4870*0eae32dcSDimitry Andric #define Q6_Vhf_vmin_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_hf)(Vu,Vv) 4871*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4872*0eae32dcSDimitry Andric 4873*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4874*0eae32dcSDimitry Andric /* ========================================================================== 4875*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vmin(Vu32.sf,Vv32.sf) 4876*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmin_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 4877*0eae32dcSDimitry Andric Instruction Type: CVI_VA 4878*0eae32dcSDimitry Andric Execution Slots: SLOT0123 4879*0eae32dcSDimitry Andric ========================================================================== */ 4880*0eae32dcSDimitry Andric 4881*0eae32dcSDimitry Andric #define Q6_Vsf_vmin_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmin_sf)(Vu,Vv) 4882*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4883*0eae32dcSDimitry Andric 4884*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4885*0eae32dcSDimitry Andric /* ========================================================================== 4886*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vmpy(Vu32.hf,Vv32.hf) 4887*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4888*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4889*0eae32dcSDimitry Andric Execution Slots: SLOT23 4890*0eae32dcSDimitry Andric ========================================================================== */ 4891*0eae32dcSDimitry Andric 4892*0eae32dcSDimitry Andric #define Q6_Vhf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf)(Vu,Vv) 4893*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4894*0eae32dcSDimitry Andric 4895*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4896*0eae32dcSDimitry Andric /* ========================================================================== 4897*0eae32dcSDimitry Andric Assembly Syntax: Vx32.hf+=vmpy(Vu32.hf,Vv32.hf) 4898*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vmpyacc_VhfVhfVhf(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) 4899*0eae32dcSDimitry Andric Instruction Type: CVI_VX 4900*0eae32dcSDimitry Andric Execution Slots: SLOT23 4901*0eae32dcSDimitry Andric ========================================================================== */ 4902*0eae32dcSDimitry Andric 4903*0eae32dcSDimitry Andric #define Q6_Vhf_vmpyacc_VhfVhfVhf(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_hf_hf_acc)(Vx,Vu,Vv) 4904*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4905*0eae32dcSDimitry Andric 4906*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4907*0eae32dcSDimitry Andric /* ========================================================================== 4908*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.qf16) 4909*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) 4910*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4911*0eae32dcSDimitry Andric Execution Slots: SLOT23 4912*0eae32dcSDimitry Andric ========================================================================== */ 4913*0eae32dcSDimitry Andric 4914*0eae32dcSDimitry Andric #define Q6_Vqf16_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16)(Vu,Vv) 4915*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4916*0eae32dcSDimitry Andric 4917*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4918*0eae32dcSDimitry Andric /* ========================================================================== 4919*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf16=vmpy(Vu32.hf,Vv32.hf) 4920*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4921*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4922*0eae32dcSDimitry Andric Execution Slots: SLOT23 4923*0eae32dcSDimitry Andric ========================================================================== */ 4924*0eae32dcSDimitry Andric 4925*0eae32dcSDimitry Andric #define Q6_Vqf16_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_hf)(Vu,Vv) 4926*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4927*0eae32dcSDimitry Andric 4928*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4929*0eae32dcSDimitry Andric /* ========================================================================== 4930*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf16=vmpy(Vu32.qf16,Vv32.hf) 4931*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) 4932*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4933*0eae32dcSDimitry Andric Execution Slots: SLOT23 4934*0eae32dcSDimitry Andric ========================================================================== */ 4935*0eae32dcSDimitry Andric 4936*0eae32dcSDimitry Andric #define Q6_Vqf16_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf16_mix_hf)(Vu,Vv) 4937*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4938*0eae32dcSDimitry Andric 4939*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4940*0eae32dcSDimitry Andric /* ========================================================================== 4941*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf32=vmpy(Vu32.qf32,Vv32.qf32) 4942*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) 4943*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4944*0eae32dcSDimitry Andric Execution Slots: SLOT23 4945*0eae32dcSDimitry Andric ========================================================================== */ 4946*0eae32dcSDimitry Andric 4947*0eae32dcSDimitry Andric #define Q6_Vqf32_vmpy_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32)(Vu,Vv) 4948*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4949*0eae32dcSDimitry Andric 4950*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4951*0eae32dcSDimitry Andric /* ========================================================================== 4952*0eae32dcSDimitry Andric Assembly Syntax: Vdd32.qf32=vmpy(Vu32.hf,Vv32.hf) 4953*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4954*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4955*0eae32dcSDimitry Andric Execution Slots: SLOT23 4956*0eae32dcSDimitry Andric ========================================================================== */ 4957*0eae32dcSDimitry Andric 4958*0eae32dcSDimitry Andric #define Q6_Wqf32_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_hf)(Vu,Vv) 4959*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4960*0eae32dcSDimitry Andric 4961*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4962*0eae32dcSDimitry Andric /* ========================================================================== 4963*0eae32dcSDimitry Andric Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.hf) 4964*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) 4965*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4966*0eae32dcSDimitry Andric Execution Slots: SLOT23 4967*0eae32dcSDimitry Andric ========================================================================== */ 4968*0eae32dcSDimitry Andric 4969*0eae32dcSDimitry Andric #define Q6_Wqf32_vmpy_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_mix_hf)(Vu,Vv) 4970*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4971*0eae32dcSDimitry Andric 4972*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4973*0eae32dcSDimitry Andric /* ========================================================================== 4974*0eae32dcSDimitry Andric Assembly Syntax: Vdd32.qf32=vmpy(Vu32.qf16,Vv32.qf16) 4975*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wqf32_vmpy_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) 4976*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4977*0eae32dcSDimitry Andric Execution Slots: SLOT23 4978*0eae32dcSDimitry Andric ========================================================================== */ 4979*0eae32dcSDimitry Andric 4980*0eae32dcSDimitry Andric #define Q6_Wqf32_vmpy_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_qf16)(Vu,Vv) 4981*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4982*0eae32dcSDimitry Andric 4983*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4984*0eae32dcSDimitry Andric /* ========================================================================== 4985*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf32=vmpy(Vu32.sf,Vv32.sf) 4986*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 4987*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4988*0eae32dcSDimitry Andric Execution Slots: SLOT23 4989*0eae32dcSDimitry Andric ========================================================================== */ 4990*0eae32dcSDimitry Andric 4991*0eae32dcSDimitry Andric #define Q6_Vqf32_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_qf32_sf)(Vu,Vv) 4992*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 4993*0eae32dcSDimitry Andric 4994*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 4995*0eae32dcSDimitry Andric /* ========================================================================== 4996*0eae32dcSDimitry Andric Assembly Syntax: Vdd32.sf=vmpy(Vu32.hf,Vv32.hf) 4997*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpy_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 4998*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 4999*0eae32dcSDimitry Andric Execution Slots: SLOT23 5000*0eae32dcSDimitry Andric ========================================================================== */ 5001*0eae32dcSDimitry Andric 5002*0eae32dcSDimitry Andric #define Q6_Wsf_vmpy_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf)(Vu,Vv) 5003*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5004*0eae32dcSDimitry Andric 5005*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5006*0eae32dcSDimitry Andric /* ========================================================================== 5007*0eae32dcSDimitry Andric Assembly Syntax: Vxx32.sf+=vmpy(Vu32.hf,Vv32.hf) 5008*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vmpyacc_WsfVhfVhf(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) 5009*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 5010*0eae32dcSDimitry Andric Execution Slots: SLOT23 5011*0eae32dcSDimitry Andric ========================================================================== */ 5012*0eae32dcSDimitry Andric 5013*0eae32dcSDimitry Andric #define Q6_Wsf_vmpyacc_WsfVhfVhf(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_hf_acc)(Vxx,Vu,Vv) 5014*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5015*0eae32dcSDimitry Andric 5016*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5017*0eae32dcSDimitry Andric /* ========================================================================== 5018*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vmpy(Vu32.sf,Vv32.sf) 5019*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vmpy_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 5020*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 5021*0eae32dcSDimitry Andric Execution Slots: SLOT23 5022*0eae32dcSDimitry Andric ========================================================================== */ 5023*0eae32dcSDimitry Andric 5024*0eae32dcSDimitry Andric #define Q6_Vsf_vmpy_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpy_sf_sf)(Vu,Vv) 5025*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5026*0eae32dcSDimitry Andric 5027*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5028*0eae32dcSDimitry Andric /* ========================================================================== 5029*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf16=vsub(Vu32.hf,Vv32.hf) 5030*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 5031*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5032*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5033*0eae32dcSDimitry Andric ========================================================================== */ 5034*0eae32dcSDimitry Andric 5035*0eae32dcSDimitry Andric #define Q6_Vqf16_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf)(Vu,Vv) 5036*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5037*0eae32dcSDimitry Andric 5038*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5039*0eae32dcSDimitry Andric /* ========================================================================== 5040*0eae32dcSDimitry Andric Assembly Syntax: Vd32.hf=vsub(Vu32.hf,Vv32.hf) 5041*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vhf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 5042*0eae32dcSDimitry Andric Instruction Type: CVI_VX 5043*0eae32dcSDimitry Andric Execution Slots: SLOT23 5044*0eae32dcSDimitry Andric ========================================================================== */ 5045*0eae32dcSDimitry Andric 5046*0eae32dcSDimitry Andric #define Q6_Vhf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_hf_hf)(Vu,Vv) 5047*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5048*0eae32dcSDimitry Andric 5049*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5050*0eae32dcSDimitry Andric /* ========================================================================== 5051*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.qf16) 5052*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vqf16(HVX_Vector Vu, HVX_Vector Vv) 5053*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5054*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5055*0eae32dcSDimitry Andric ========================================================================== */ 5056*0eae32dcSDimitry Andric 5057*0eae32dcSDimitry Andric #define Q6_Vqf16_vsub_Vqf16Vqf16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16)(Vu,Vv) 5058*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5059*0eae32dcSDimitry Andric 5060*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5061*0eae32dcSDimitry Andric /* ========================================================================== 5062*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf16=vsub(Vu32.qf16,Vv32.hf) 5063*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf16_vsub_Vqf16Vhf(HVX_Vector Vu, HVX_Vector Vv) 5064*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5065*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5066*0eae32dcSDimitry Andric ========================================================================== */ 5067*0eae32dcSDimitry Andric 5068*0eae32dcSDimitry Andric #define Q6_Vqf16_vsub_Vqf16Vhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf16_mix)(Vu,Vv) 5069*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5070*0eae32dcSDimitry Andric 5071*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5072*0eae32dcSDimitry Andric /* ========================================================================== 5073*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.qf32) 5074*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vqf32(HVX_Vector Vu, HVX_Vector Vv) 5075*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5076*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5077*0eae32dcSDimitry Andric ========================================================================== */ 5078*0eae32dcSDimitry Andric 5079*0eae32dcSDimitry Andric #define Q6_Vqf32_vsub_Vqf32Vqf32(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32)(Vu,Vv) 5080*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5081*0eae32dcSDimitry Andric 5082*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5083*0eae32dcSDimitry Andric /* ========================================================================== 5084*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf32=vsub(Vu32.qf32,Vv32.sf) 5085*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_Vqf32Vsf(HVX_Vector Vu, HVX_Vector Vv) 5086*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5087*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5088*0eae32dcSDimitry Andric ========================================================================== */ 5089*0eae32dcSDimitry Andric 5090*0eae32dcSDimitry Andric #define Q6_Vqf32_vsub_Vqf32Vsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_qf32_mix)(Vu,Vv) 5091*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5092*0eae32dcSDimitry Andric 5093*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5094*0eae32dcSDimitry Andric /* ========================================================================== 5095*0eae32dcSDimitry Andric Assembly Syntax: Vd32.qf32=vsub(Vu32.sf,Vv32.sf) 5096*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vqf32_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 5097*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5098*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5099*0eae32dcSDimitry Andric ========================================================================== */ 5100*0eae32dcSDimitry Andric 5101*0eae32dcSDimitry Andric #define Q6_Vqf32_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf)(Vu,Vv) 5102*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5103*0eae32dcSDimitry Andric 5104*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5105*0eae32dcSDimitry Andric /* ========================================================================== 5106*0eae32dcSDimitry Andric Assembly Syntax: Vdd32.sf=vsub(Vu32.hf,Vv32.hf) 5107*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_VectorPair Q6_Wsf_vsub_VhfVhf(HVX_Vector Vu, HVX_Vector Vv) 5108*0eae32dcSDimitry Andric Instruction Type: CVI_VX_DV 5109*0eae32dcSDimitry Andric Execution Slots: SLOT23 5110*0eae32dcSDimitry Andric ========================================================================== */ 5111*0eae32dcSDimitry Andric 5112*0eae32dcSDimitry Andric #define Q6_Wsf_vsub_VhfVhf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_hf)(Vu,Vv) 5113*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5114*0eae32dcSDimitry Andric 5115*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 68 5116*0eae32dcSDimitry Andric /* ========================================================================== 5117*0eae32dcSDimitry Andric Assembly Syntax: Vd32.sf=vsub(Vu32.sf,Vv32.sf) 5118*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vsf_vsub_VsfVsf(HVX_Vector Vu, HVX_Vector Vv) 5119*0eae32dcSDimitry Andric Instruction Type: CVI_VX 5120*0eae32dcSDimitry Andric Execution Slots: SLOT23 5121*0eae32dcSDimitry Andric ========================================================================== */ 5122*0eae32dcSDimitry Andric 5123*0eae32dcSDimitry Andric #define Q6_Vsf_vsub_VsfVsf(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsub_sf_sf)(Vu,Vv) 5124*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 68 */ 5125*0eae32dcSDimitry Andric 5126*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 69 5127*0eae32dcSDimitry Andric /* ========================================================================== 5128*0eae32dcSDimitry Andric Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):rnd:sat 5129*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) 5130*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5131*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5132*0eae32dcSDimitry Andric ========================================================================== */ 5133*0eae32dcSDimitry Andric 5134*0eae32dcSDimitry Andric #define Q6_Vub_vasr_WuhVub_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubrndsat)(Vuu,Vv) 5135*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 69 */ 5136*0eae32dcSDimitry Andric 5137*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 69 5138*0eae32dcSDimitry Andric /* ========================================================================== 5139*0eae32dcSDimitry Andric Assembly Syntax: Vd32.ub=vasr(Vuu32.uh,Vv32.ub):sat 5140*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_WuhVub_sat(HVX_VectorPair Vuu, HVX_Vector Vv) 5141*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5142*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5143*0eae32dcSDimitry Andric ========================================================================== */ 5144*0eae32dcSDimitry Andric 5145*0eae32dcSDimitry Andric #define Q6_Vub_vasr_WuhVub_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvuhubsat)(Vuu,Vv) 5146*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 69 */ 5147*0eae32dcSDimitry Andric 5148*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 69 5149*0eae32dcSDimitry Andric /* ========================================================================== 5150*0eae32dcSDimitry Andric Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):rnd:sat 5151*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_rnd_sat(HVX_VectorPair Vuu, HVX_Vector Vv) 5152*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5153*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5154*0eae32dcSDimitry Andric ========================================================================== */ 5155*0eae32dcSDimitry Andric 5156*0eae32dcSDimitry Andric #define Q6_Vuh_vasr_WwVuh_rnd_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhrndsat)(Vuu,Vv) 5157*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 69 */ 5158*0eae32dcSDimitry Andric 5159*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 69 5160*0eae32dcSDimitry Andric /* ========================================================================== 5161*0eae32dcSDimitry Andric Assembly Syntax: Vd32.uh=vasr(Vuu32.w,Vv32.uh):sat 5162*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_WwVuh_sat(HVX_VectorPair Vuu, HVX_Vector Vv) 5163*0eae32dcSDimitry Andric Instruction Type: CVI_VS 5164*0eae32dcSDimitry Andric Execution Slots: SLOT0123 5165*0eae32dcSDimitry Andric ========================================================================== */ 5166*0eae32dcSDimitry Andric 5167*0eae32dcSDimitry Andric #define Q6_Vuh_vasr_WwVuh_sat(Vuu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrvwuhsat)(Vuu,Vv) 5168*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 69 */ 5169*0eae32dcSDimitry Andric 5170*0eae32dcSDimitry Andric #if __HVX_ARCH__ >= 69 5171*0eae32dcSDimitry Andric /* ========================================================================== 5172*0eae32dcSDimitry Andric Assembly Syntax: Vd32.uh=vmpy(Vu32.uh,Vv32.uh):>>16 5173*0eae32dcSDimitry Andric C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmpy_VuhVuh_rs16(HVX_Vector Vu, HVX_Vector Vv) 5174*0eae32dcSDimitry Andric Instruction Type: CVI_VX 5175*0eae32dcSDimitry Andric Execution Slots: SLOT23 5176*0eae32dcSDimitry Andric ========================================================================== */ 5177*0eae32dcSDimitry Andric 5178*0eae32dcSDimitry Andric #define Q6_Vuh_vmpy_VuhVuh_rs16(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhvs)(Vu,Vv) 5179*0eae32dcSDimitry Andric #endif /* __HEXAGON_ARCH___ >= 69 */ 5180*0eae32dcSDimitry Andric 5181fe6060f1SDimitry Andric #endif /* __HVX__ */ 5182fe6060f1SDimitry Andric 5183fe6060f1SDimitry Andric #endif 5184