xref: /freebsd-src/contrib/llvm-project/clang/lib/Headers/htmintrin.h (revision 0b57cec536236d46e3dba9bd041533462f33dbb7)
1*0b57cec5SDimitry Andric /*===---- htmintrin.h - Standard header for PowerPC HTM ---------------===*\
2*0b57cec5SDimitry Andric  *
3*0b57cec5SDimitry Andric  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4*0b57cec5SDimitry Andric  * See https://llvm.org/LICENSE.txt for license information.
5*0b57cec5SDimitry Andric  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6*0b57cec5SDimitry Andric  *
7*0b57cec5SDimitry Andric \*===----------------------------------------------------------------------===*/
8*0b57cec5SDimitry Andric 
9*0b57cec5SDimitry Andric #ifndef __HTMINTRIN_H
10*0b57cec5SDimitry Andric #define __HTMINTRIN_H
11*0b57cec5SDimitry Andric 
12*0b57cec5SDimitry Andric #ifndef __HTM__
13*0b57cec5SDimitry Andric #error "HTM instruction set not enabled"
14*0b57cec5SDimitry Andric #endif
15*0b57cec5SDimitry Andric 
16*0b57cec5SDimitry Andric #ifdef __powerpc__
17*0b57cec5SDimitry Andric 
18*0b57cec5SDimitry Andric #include <stdint.h>
19*0b57cec5SDimitry Andric 
20*0b57cec5SDimitry Andric typedef uint64_t texasr_t;
21*0b57cec5SDimitry Andric typedef uint32_t texasru_t;
22*0b57cec5SDimitry Andric typedef uint32_t texasrl_t;
23*0b57cec5SDimitry Andric typedef uintptr_t tfiar_t;
24*0b57cec5SDimitry Andric typedef uintptr_t tfhar_t;
25*0b57cec5SDimitry Andric 
26*0b57cec5SDimitry Andric #define _HTM_STATE(CR0) ((CR0 >> 1) & 0x3)
27*0b57cec5SDimitry Andric #define _HTM_NONTRANSACTIONAL 0x0
28*0b57cec5SDimitry Andric #define _HTM_SUSPENDED        0x1
29*0b57cec5SDimitry Andric #define _HTM_TRANSACTIONAL    0x2
30*0b57cec5SDimitry Andric 
31*0b57cec5SDimitry Andric #define _TEXASR_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
32*0b57cec5SDimitry Andric   (((TEXASR) >> (63-(BITNUM))) & ((1<<(SIZE))-1))
33*0b57cec5SDimitry Andric #define _TEXASRU_EXTRACT_BITS(TEXASR,BITNUM,SIZE) \
34*0b57cec5SDimitry Andric   (((TEXASR) >> (31-(BITNUM))) & ((1<<(SIZE))-1))
35*0b57cec5SDimitry Andric 
36*0b57cec5SDimitry Andric #define _TEXASR_FAILURE_CODE(TEXASR) \
37*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 7, 8)
38*0b57cec5SDimitry Andric #define _TEXASRU_FAILURE_CODE(TEXASRU) \
39*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 8)
40*0b57cec5SDimitry Andric 
41*0b57cec5SDimitry Andric #define _TEXASR_FAILURE_PERSISTENT(TEXASR) \
42*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 7, 1)
43*0b57cec5SDimitry Andric #define _TEXASRU_FAILURE_PERSISTENT(TEXASRU) \
44*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 7, 1)
45*0b57cec5SDimitry Andric 
46*0b57cec5SDimitry Andric #define _TEXASR_DISALLOWED(TEXASR) \
47*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 8, 1)
48*0b57cec5SDimitry Andric #define _TEXASRU_DISALLOWED(TEXASRU) \
49*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 8, 1)
50*0b57cec5SDimitry Andric 
51*0b57cec5SDimitry Andric #define _TEXASR_NESTING_OVERFLOW(TEXASR) \
52*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 9, 1)
53*0b57cec5SDimitry Andric #define _TEXASRU_NESTING_OVERFLOW(TEXASRU) \
54*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 9, 1)
55*0b57cec5SDimitry Andric 
56*0b57cec5SDimitry Andric #define _TEXASR_FOOTPRINT_OVERFLOW(TEXASR) \
57*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 10, 1)
58*0b57cec5SDimitry Andric #define _TEXASRU_FOOTPRINT_OVERFLOW(TEXASRU) \
59*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 10, 1)
60*0b57cec5SDimitry Andric 
61*0b57cec5SDimitry Andric #define _TEXASR_SELF_INDUCED_CONFLICT(TEXASR) \
62*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 11, 1)
63*0b57cec5SDimitry Andric #define _TEXASRU_SELF_INDUCED_CONFLICT(TEXASRU) \
64*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 11, 1)
65*0b57cec5SDimitry Andric 
66*0b57cec5SDimitry Andric #define _TEXASR_NON_TRANSACTIONAL_CONFLICT(TEXASR) \
67*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 12, 1)
68*0b57cec5SDimitry Andric #define _TEXASRU_NON_TRANSACTIONAL_CONFLICT(TEXASRU) \
69*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 12, 1)
70*0b57cec5SDimitry Andric 
71*0b57cec5SDimitry Andric #define _TEXASR_TRANSACTION_CONFLICT(TEXASR) \
72*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 13, 1)
73*0b57cec5SDimitry Andric #define _TEXASRU_TRANSACTION_CONFLICT(TEXASRU) \
74*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 13, 1)
75*0b57cec5SDimitry Andric 
76*0b57cec5SDimitry Andric #define _TEXASR_TRANSLATION_INVALIDATION_CONFLICT(TEXASR) \
77*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 14, 1)
78*0b57cec5SDimitry Andric #define _TEXASRU_TRANSLATION_INVALIDATION_CONFLICT(TEXASRU) \
79*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 14, 1)
80*0b57cec5SDimitry Andric 
81*0b57cec5SDimitry Andric #define _TEXASR_IMPLEMENTAION_SPECIFIC(TEXASR) \
82*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 15, 1)
83*0b57cec5SDimitry Andric #define _TEXASRU_IMPLEMENTAION_SPECIFIC(TEXASRU) \
84*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 15, 1)
85*0b57cec5SDimitry Andric 
86*0b57cec5SDimitry Andric #define _TEXASR_INSTRUCTION_FETCH_CONFLICT(TEXASR) \
87*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 16, 1)
88*0b57cec5SDimitry Andric #define _TEXASRU_INSTRUCTION_FETCH_CONFLICT(TEXASRU) \
89*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 16, 1)
90*0b57cec5SDimitry Andric 
91*0b57cec5SDimitry Andric #define _TEXASR_ABORT(TEXASR) \
92*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 31, 1)
93*0b57cec5SDimitry Andric #define _TEXASRU_ABORT(TEXASRU) \
94*0b57cec5SDimitry Andric   _TEXASRU_EXTRACT_BITS(TEXASRU, 31, 1)
95*0b57cec5SDimitry Andric 
96*0b57cec5SDimitry Andric 
97*0b57cec5SDimitry Andric #define _TEXASR_SUSPENDED(TEXASR) \
98*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 32, 1)
99*0b57cec5SDimitry Andric 
100*0b57cec5SDimitry Andric #define _TEXASR_PRIVILEGE(TEXASR) \
101*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 35, 2)
102*0b57cec5SDimitry Andric 
103*0b57cec5SDimitry Andric #define _TEXASR_FAILURE_SUMMARY(TEXASR) \
104*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 36, 1)
105*0b57cec5SDimitry Andric 
106*0b57cec5SDimitry Andric #define _TEXASR_TFIAR_EXACT(TEXASR) \
107*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 37, 1)
108*0b57cec5SDimitry Andric 
109*0b57cec5SDimitry Andric #define _TEXASR_ROT(TEXASR) \
110*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 38, 1)
111*0b57cec5SDimitry Andric 
112*0b57cec5SDimitry Andric #define _TEXASR_TRANSACTION_LEVEL(TEXASR) \
113*0b57cec5SDimitry Andric   _TEXASR_EXTRACT_BITS(TEXASR, 63, 12)
114*0b57cec5SDimitry Andric 
115*0b57cec5SDimitry Andric #endif /* __powerpc */
116*0b57cec5SDimitry Andric 
117*0b57cec5SDimitry Andric #ifdef __s390__
118*0b57cec5SDimitry Andric 
119*0b57cec5SDimitry Andric /* Condition codes generated by tbegin  */
120*0b57cec5SDimitry Andric #define _HTM_TBEGIN_STARTED       0
121*0b57cec5SDimitry Andric #define _HTM_TBEGIN_INDETERMINATE 1
122*0b57cec5SDimitry Andric #define _HTM_TBEGIN_TRANSIENT     2
123*0b57cec5SDimitry Andric #define _HTM_TBEGIN_PERSISTENT    3
124*0b57cec5SDimitry Andric 
125*0b57cec5SDimitry Andric /* The abort codes below this threshold are reserved for machine use.  */
126*0b57cec5SDimitry Andric #define _HTM_FIRST_USER_ABORT_CODE 256
127*0b57cec5SDimitry Andric 
128*0b57cec5SDimitry Andric /* The transaction diagnostic block is it is defined in the Principles
129*0b57cec5SDimitry Andric    of Operation chapter 5-91.  */
130*0b57cec5SDimitry Andric 
131*0b57cec5SDimitry Andric struct __htm_tdb {
132*0b57cec5SDimitry Andric   unsigned char format;                /*   0 */
133*0b57cec5SDimitry Andric   unsigned char flags;
134*0b57cec5SDimitry Andric   unsigned char reserved1[4];
135*0b57cec5SDimitry Andric   unsigned short nesting_depth;
136*0b57cec5SDimitry Andric   unsigned long long abort_code;       /*   8 */
137*0b57cec5SDimitry Andric   unsigned long long conflict_token;   /*  16 */
138*0b57cec5SDimitry Andric   unsigned long long atia;             /*  24 */
139*0b57cec5SDimitry Andric   unsigned char eaid;                  /*  32 */
140*0b57cec5SDimitry Andric   unsigned char dxc;
141*0b57cec5SDimitry Andric   unsigned char reserved2[2];
142*0b57cec5SDimitry Andric   unsigned int program_int_id;
143*0b57cec5SDimitry Andric   unsigned long long exception_id;     /*  40 */
144*0b57cec5SDimitry Andric   unsigned long long bea;              /*  48 */
145*0b57cec5SDimitry Andric   unsigned char reserved3[72];         /*  56 */
146*0b57cec5SDimitry Andric   unsigned long long gprs[16];         /* 128 */
147*0b57cec5SDimitry Andric } __attribute__((__packed__, __aligned__ (8)));
148*0b57cec5SDimitry Andric 
149*0b57cec5SDimitry Andric 
150*0b57cec5SDimitry Andric /* Helper intrinsics to retry tbegin in case of transient failure.  */
151*0b57cec5SDimitry Andric 
152*0b57cec5SDimitry Andric static __inline int __attribute__((__always_inline__, __nodebug__))
__builtin_tbegin_retry_null(int __retry)153*0b57cec5SDimitry Andric __builtin_tbegin_retry_null (int __retry)
154*0b57cec5SDimitry Andric {
155*0b57cec5SDimitry Andric   int cc, i = 0;
156*0b57cec5SDimitry Andric 
157*0b57cec5SDimitry Andric   while ((cc = __builtin_tbegin(0)) == _HTM_TBEGIN_TRANSIENT
158*0b57cec5SDimitry Andric          && i++ < __retry)
159*0b57cec5SDimitry Andric     __builtin_tx_assist(i);
160*0b57cec5SDimitry Andric 
161*0b57cec5SDimitry Andric   return cc;
162*0b57cec5SDimitry Andric }
163*0b57cec5SDimitry Andric 
164*0b57cec5SDimitry Andric static __inline int __attribute__((__always_inline__, __nodebug__))
__builtin_tbegin_retry_tdb(void * __tdb,int __retry)165*0b57cec5SDimitry Andric __builtin_tbegin_retry_tdb (void *__tdb, int __retry)
166*0b57cec5SDimitry Andric {
167*0b57cec5SDimitry Andric   int cc, i = 0;
168*0b57cec5SDimitry Andric 
169*0b57cec5SDimitry Andric   while ((cc = __builtin_tbegin(__tdb)) == _HTM_TBEGIN_TRANSIENT
170*0b57cec5SDimitry Andric          && i++ < __retry)
171*0b57cec5SDimitry Andric     __builtin_tx_assist(i);
172*0b57cec5SDimitry Andric 
173*0b57cec5SDimitry Andric   return cc;
174*0b57cec5SDimitry Andric }
175*0b57cec5SDimitry Andric 
176*0b57cec5SDimitry Andric #define __builtin_tbegin_retry(tdb, retry) \
177*0b57cec5SDimitry Andric   (__builtin_constant_p(tdb == 0) && tdb == 0 ? \
178*0b57cec5SDimitry Andric    __builtin_tbegin_retry_null(retry) : \
179*0b57cec5SDimitry Andric    __builtin_tbegin_retry_tdb(tdb, retry))
180*0b57cec5SDimitry Andric 
181*0b57cec5SDimitry Andric static __inline int __attribute__((__always_inline__, __nodebug__))
__builtin_tbegin_retry_nofloat_null(int __retry)182*0b57cec5SDimitry Andric __builtin_tbegin_retry_nofloat_null (int __retry)
183*0b57cec5SDimitry Andric {
184*0b57cec5SDimitry Andric   int cc, i = 0;
185*0b57cec5SDimitry Andric 
186*0b57cec5SDimitry Andric   while ((cc = __builtin_tbegin_nofloat(0)) == _HTM_TBEGIN_TRANSIENT
187*0b57cec5SDimitry Andric          && i++ < __retry)
188*0b57cec5SDimitry Andric     __builtin_tx_assist(i);
189*0b57cec5SDimitry Andric 
190*0b57cec5SDimitry Andric   return cc;
191*0b57cec5SDimitry Andric }
192*0b57cec5SDimitry Andric 
193*0b57cec5SDimitry Andric static __inline int __attribute__((__always_inline__, __nodebug__))
__builtin_tbegin_retry_nofloat_tdb(void * __tdb,int __retry)194*0b57cec5SDimitry Andric __builtin_tbegin_retry_nofloat_tdb (void *__tdb, int __retry)
195*0b57cec5SDimitry Andric {
196*0b57cec5SDimitry Andric   int cc, i = 0;
197*0b57cec5SDimitry Andric 
198*0b57cec5SDimitry Andric   while ((cc = __builtin_tbegin_nofloat(__tdb)) == _HTM_TBEGIN_TRANSIENT
199*0b57cec5SDimitry Andric          && i++ < __retry)
200*0b57cec5SDimitry Andric     __builtin_tx_assist(i);
201*0b57cec5SDimitry Andric 
202*0b57cec5SDimitry Andric   return cc;
203*0b57cec5SDimitry Andric }
204*0b57cec5SDimitry Andric 
205*0b57cec5SDimitry Andric #define __builtin_tbegin_retry_nofloat(tdb, retry) \
206*0b57cec5SDimitry Andric   (__builtin_constant_p(tdb == 0) && tdb == 0 ? \
207*0b57cec5SDimitry Andric    __builtin_tbegin_retry_nofloat_null(retry) : \
208*0b57cec5SDimitry Andric    __builtin_tbegin_retry_nofloat_tdb(tdb, retry))
209*0b57cec5SDimitry Andric 
210*0b57cec5SDimitry Andric #endif /* __s390__ */
211*0b57cec5SDimitry Andric 
212*0b57cec5SDimitry Andric #endif /* __HTMINTRIN_H */
213