1*8ddb146aSEd Maste /* 2*8ddb146aSEd Maste Copyright (c) 2014, Intel Corporation 3*8ddb146aSEd Maste All rights reserved. 4*8ddb146aSEd Maste 5*8ddb146aSEd Maste Redistribution and use in source and binary forms, with or without 6*8ddb146aSEd Maste modification, are permitted provided that the following conditions are met: 7*8ddb146aSEd Maste 8*8ddb146aSEd Maste * Redistributions of source code must retain the above copyright notice, 9*8ddb146aSEd Maste * this list of conditions and the following disclaimer. 10*8ddb146aSEd Maste 11*8ddb146aSEd Maste * Redistributions in binary form must reproduce the above copyright notice, 12*8ddb146aSEd Maste * this list of conditions and the following disclaimer in the documentation 13*8ddb146aSEd Maste * and/or other materials provided with the distribution. 14*8ddb146aSEd Maste 15*8ddb146aSEd Maste * Neither the name of Intel Corporation nor the names of its contributors 16*8ddb146aSEd Maste * may be used to endorse or promote products derived from this software 17*8ddb146aSEd Maste * without specific prior written permission. 18*8ddb146aSEd Maste 19*8ddb146aSEd Maste THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 20*8ddb146aSEd Maste ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21*8ddb146aSEd Maste WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22*8ddb146aSEd Maste DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 23*8ddb146aSEd Maste ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24*8ddb146aSEd Maste (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25*8ddb146aSEd Maste LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 26*8ddb146aSEd Maste ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27*8ddb146aSEd Maste (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28*8ddb146aSEd Maste SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29*8ddb146aSEd Maste */ 30*8ddb146aSEd Maste 31*8ddb146aSEd Maste /* Values are optimized for Core Architecture */ 32*8ddb146aSEd Maste #define SHARED_CACHE_SIZE (4096*1024) /* Core Architecture L2 Cache */ 33*8ddb146aSEd Maste #define DATA_CACHE_SIZE (24*1024) /* Core Architecture L1 Data Cache */ 34*8ddb146aSEd Maste 35*8ddb146aSEd Maste #define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2) 36*8ddb146aSEd Maste #define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2) 37