xref: /dpdk/lib/net/rte_pdcp_hdr.h (revision fba9875559906e04eaeb74532f4cfd51194259a2)
1895ec77bSVolodymyr Fialko /* SPDX-License-Identifier: BSD-3-Clause
2895ec77bSVolodymyr Fialko  * Copyright(C) 2023 Marvell.
3895ec77bSVolodymyr Fialko  */
4895ec77bSVolodymyr Fialko 
5895ec77bSVolodymyr Fialko #ifndef RTE_PDCP_HDR_H
6895ec77bSVolodymyr Fialko #define RTE_PDCP_HDR_H
7895ec77bSVolodymyr Fialko 
8895ec77bSVolodymyr Fialko /**
9895ec77bSVolodymyr Fialko  * @file
10895ec77bSVolodymyr Fialko  *
11895ec77bSVolodymyr Fialko  * PDCP-related defines
12895ec77bSVolodymyr Fialko  *
13895ec77bSVolodymyr Fialko  * Based on - ETSI TS 138 323 V17.1.0 (2022-08)
14895ec77bSVolodymyr Fialko  * https://www.etsi.org/deliver/etsi_ts/138300_138399/138323/17.01.00_60/ts_138323v170100p.pdf
15895ec77bSVolodymyr Fialko  */
16895ec77bSVolodymyr Fialko 
17895ec77bSVolodymyr Fialko #include <rte_byteorder.h>
18895ec77bSVolodymyr Fialko 
19895ec77bSVolodymyr Fialko /**
20895ec77bSVolodymyr Fialko  * 4.3.1
21895ec77bSVolodymyr Fialko  *
22895ec77bSVolodymyr Fialko  * Indicate the maximum supported size of a PDCP Control PDU.
23895ec77bSVolodymyr Fialko  */
24895ec77bSVolodymyr Fialko #define RTE_PDCP_CTRL_PDU_SIZE_MAX 9000u
25895ec77bSVolodymyr Fialko 
26895ec77bSVolodymyr Fialko /**
27895ec77bSVolodymyr Fialko  * 6.3.4 MAC-I
28895ec77bSVolodymyr Fialko  *
29895ec77bSVolodymyr Fialko  * Indicate the size of MAC-I in PDCP PDU.
30895ec77bSVolodymyr Fialko  */
31895ec77bSVolodymyr Fialko #define RTE_PDCP_MAC_I_LEN 4
32895ec77bSVolodymyr Fialko 
33895ec77bSVolodymyr Fialko /**
34895ec77bSVolodymyr Fialko  * Indicate type of control information included in the corresponding PDCP
35895ec77bSVolodymyr Fialko  * Control PDU.
36895ec77bSVolodymyr Fialko  */
37895ec77bSVolodymyr Fialko enum rte_pdcp_ctrl_pdu_type {
38895ec77bSVolodymyr Fialko 	RTE_PDCP_CTRL_PDU_TYPE_STATUS_REPORT = 0,
39895ec77bSVolodymyr Fialko 	RTE_PDCP_CTRL_PDU_TYPE_ROHC_FEEDBACK = 1,
40895ec77bSVolodymyr Fialko 	RTE_PDCP_CTRL_PDU_TYPE_EHC_FEEDBACK = 2,
41895ec77bSVolodymyr Fialko 	RTE_PDCP_CRTL_PDU_TYPE_UDC_FEEDBACK = 3,
42895ec77bSVolodymyr Fialko };
43895ec77bSVolodymyr Fialko 
44895ec77bSVolodymyr Fialko /**
45895ec77bSVolodymyr Fialko  * 6.3.7 D/C
46895ec77bSVolodymyr Fialko  *
47895ec77bSVolodymyr Fialko  * This field indicates whether the corresponding PDCP PDU is a
48895ec77bSVolodymyr Fialko  * PDCP Data PDU or a PDCP Control PDU.
49895ec77bSVolodymyr Fialko  */
50895ec77bSVolodymyr Fialko enum rte_pdcp_pdu_type {
51895ec77bSVolodymyr Fialko 	RTE_PDCP_PDU_TYPE_CTRL = 0,
52895ec77bSVolodymyr Fialko 	RTE_PDCP_PDU_TYPE_DATA = 1,
53895ec77bSVolodymyr Fialko };
54895ec77bSVolodymyr Fialko 
55895ec77bSVolodymyr Fialko /**
56895ec77bSVolodymyr Fialko  * 6.2.2.1 Data PDU for SRBs
57895ec77bSVolodymyr Fialko  */
58895ec77bSVolodymyr Fialko __extension__
59*fba98755SAndre Muezerie struct __rte_packed_begin rte_pdcp_cp_data_pdu_sn_12_hdr {
60895ec77bSVolodymyr Fialko #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
61895ec77bSVolodymyr Fialko 	uint8_t sn_11_8 : 4;	/**< Sequence number bits 8-11 */
62895ec77bSVolodymyr Fialko 	uint8_t r : 4;		/**< Reserved */
63895ec77bSVolodymyr Fialko #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
64895ec77bSVolodymyr Fialko 	uint8_t r : 4;		/**< Reserved */
65895ec77bSVolodymyr Fialko 	uint8_t sn_11_8 : 4;	/**< Sequence number bits 8-11 */
66895ec77bSVolodymyr Fialko #endif
67895ec77bSVolodymyr Fialko 	uint8_t sn_7_0;		/**< Sequence number bits 0-7 */
68*fba98755SAndre Muezerie } __rte_packed_end;
69895ec77bSVolodymyr Fialko 
70895ec77bSVolodymyr Fialko /**
71895ec77bSVolodymyr Fialko  * 6.2.2.2 Data PDU for DRBs and MRBs with 12 bits PDCP SN
72895ec77bSVolodymyr Fialko  */
73895ec77bSVolodymyr Fialko __extension__
74*fba98755SAndre Muezerie struct __rte_packed_begin rte_pdcp_up_data_pdu_sn_12_hdr {
75895ec77bSVolodymyr Fialko #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
76895ec77bSVolodymyr Fialko 	uint8_t sn_11_8 : 4;	/**< Sequence number bits 8-11 */
77895ec77bSVolodymyr Fialko 	uint8_t r : 3;		/**< Reserved */
78895ec77bSVolodymyr Fialko 	uint8_t d_c : 1;	/**< D/C bit */
79895ec77bSVolodymyr Fialko #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
80895ec77bSVolodymyr Fialko 	uint8_t d_c : 1;	/**< D/C bit */
81895ec77bSVolodymyr Fialko 	uint8_t r : 3;		/**< Reserved */
82895ec77bSVolodymyr Fialko 	uint8_t sn_11_8 : 4;	/**< Sequence number bits 8-11 */
83895ec77bSVolodymyr Fialko #endif
84895ec77bSVolodymyr Fialko 	uint8_t sn_7_0;		/**< Sequence number bits 0-7 */
85*fba98755SAndre Muezerie } __rte_packed_end;
86895ec77bSVolodymyr Fialko 
87895ec77bSVolodymyr Fialko /**
88895ec77bSVolodymyr Fialko  * 6.2.2.3 Data PDU for DRBs and MRBs with 18 bits PDCP SN
89895ec77bSVolodymyr Fialko  */
90895ec77bSVolodymyr Fialko __extension__
91*fba98755SAndre Muezerie struct __rte_packed_begin rte_pdcp_up_data_pdu_sn_18_hdr {
92895ec77bSVolodymyr Fialko #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
93895ec77bSVolodymyr Fialko 	uint8_t sn_17_16 : 2;	/**< Sequence number bits 16-17 */
94895ec77bSVolodymyr Fialko 	uint8_t r : 5;		/**< Reserved */
95895ec77bSVolodymyr Fialko 	uint8_t d_c : 1;	/**< D/C bit */
96895ec77bSVolodymyr Fialko #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
97895ec77bSVolodymyr Fialko 	uint8_t d_c : 1;	/**< D/C bit */
98895ec77bSVolodymyr Fialko 	uint8_t r : 5;		/**< Reserved */
99895ec77bSVolodymyr Fialko 	uint8_t sn_17_16 : 2;	/**< Sequence number bits 16-17 */
100895ec77bSVolodymyr Fialko #endif
101895ec77bSVolodymyr Fialko 	uint8_t sn_15_8;	/**< Sequence number bits 8-15 */
102895ec77bSVolodymyr Fialko 	uint8_t sn_7_0;		/**< Sequence number bits 0-7 */
103*fba98755SAndre Muezerie } __rte_packed_end;
104895ec77bSVolodymyr Fialko 
105895ec77bSVolodymyr Fialko /**
106895ec77bSVolodymyr Fialko  * 6.2.3.1 Control PDU for PDCP status report
107895ec77bSVolodymyr Fialko  */
108895ec77bSVolodymyr Fialko __extension__
109*fba98755SAndre Muezerie struct __rte_packed_begin rte_pdcp_up_ctrl_pdu_hdr {
110895ec77bSVolodymyr Fialko #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
111895ec77bSVolodymyr Fialko 	uint8_t r : 4;		/**< Reserved */
112895ec77bSVolodymyr Fialko 	uint8_t pdu_type : 3;	/**< Control PDU type */
113895ec77bSVolodymyr Fialko 	uint8_t d_c : 1;	/**< D/C bit */
114895ec77bSVolodymyr Fialko #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
115895ec77bSVolodymyr Fialko 	uint8_t d_c : 1;	/**< D/C bit */
116895ec77bSVolodymyr Fialko 	uint8_t pdu_type : 3;	/**< Control PDU type */
117895ec77bSVolodymyr Fialko 	uint8_t r : 4;		/**< Reserved */
118895ec77bSVolodymyr Fialko #endif
119895ec77bSVolodymyr Fialko 	/**
120895ec77bSVolodymyr Fialko 	 * 6.3.9 FMC
121895ec77bSVolodymyr Fialko 	 *
122895ec77bSVolodymyr Fialko 	 * First Missing COUNT. This field indicates the COUNT value of the
123895ec77bSVolodymyr Fialko 	 * first missing PDCP SDU within the reordering window, i.e. RX_DELIV.
124895ec77bSVolodymyr Fialko 	 */
125895ec77bSVolodymyr Fialko 	rte_be32_t fmc;
126895ec77bSVolodymyr Fialko 	/**
127895ec77bSVolodymyr Fialko 	 * 6.3.10 Bitmap
128895ec77bSVolodymyr Fialko 	 *
129895ec77bSVolodymyr Fialko 	 * Length: Variable. The length of the bitmap field can be 0.
130895ec77bSVolodymyr Fialko 	 *
131895ec77bSVolodymyr Fialko 	 * This field indicates which SDUs are missing and which SDUs are
132895ec77bSVolodymyr Fialko 	 * correctly received in the receiving PDCP entity. The bit position of
133895ec77bSVolodymyr Fialko 	 * Nth bit in the Bitmap is N, i.e., the bit position of the first bit
134895ec77bSVolodymyr Fialko 	 * in the Bitmap is 1.
135895ec77bSVolodymyr Fialko 	 */
136895ec77bSVolodymyr Fialko 	uint8_t bitmap[];
137*fba98755SAndre Muezerie } __rte_packed_end;
138895ec77bSVolodymyr Fialko 
139895ec77bSVolodymyr Fialko #endif /* RTE_PDCP_HDR_H */
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