1e9b8532eSDong Zhou /* SPDX-License-Identifier: BSD-3-Clause 2e9b8532eSDong Zhou * Copyright (c) 2023 NVIDIA Corporation & Affiliates 3e9b8532eSDong Zhou */ 4e9b8532eSDong Zhou 5e9b8532eSDong Zhou #ifndef RTE_IB_H 6e9b8532eSDong Zhou #define RTE_IB_H 7e9b8532eSDong Zhou 8e9b8532eSDong Zhou /** 9e9b8532eSDong Zhou * @file 10e9b8532eSDong Zhou * 11e9b8532eSDong Zhou * InfiniBand headers definitions 12e9b8532eSDong Zhou * 13e9b8532eSDong Zhou * The infiniBand headers are used by RoCE (RDMA over Converged Ethernet). 14e9b8532eSDong Zhou */ 15e9b8532eSDong Zhou 16e9b8532eSDong Zhou #include <stdint.h> 17e9b8532eSDong Zhou 18e9b8532eSDong Zhou #include <rte_byteorder.h> 19e9b8532eSDong Zhou 20e9b8532eSDong Zhou /** 21e9b8532eSDong Zhou * InfiniBand Base Transport Header according to 22e9b8532eSDong Zhou * IB Specification Vol 1-Release-1.4. 23e9b8532eSDong Zhou */ 24e9b8532eSDong Zhou __extension__ 25*fba98755SAndre Muezerie struct __rte_packed_begin rte_ib_bth { 26e9b8532eSDong Zhou uint8_t opcode; /**< Opcode. */ 27e9b8532eSDong Zhou #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 28e9b8532eSDong Zhou uint8_t tver:4; /**< Transport Header Version. */ 29e9b8532eSDong Zhou uint8_t padcnt:2; /**< Pad Count. */ 30e9b8532eSDong Zhou uint8_t m:1; /**< MigReq. */ 31e9b8532eSDong Zhou uint8_t se:1; /**< Solicited Event. */ 32e9b8532eSDong Zhou #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 33e9b8532eSDong Zhou uint8_t se:1; /**< Solicited Event. */ 34e9b8532eSDong Zhou uint8_t m:1; /**< MigReq. */ 35e9b8532eSDong Zhou uint8_t padcnt:2; /**< Pad Count. */ 36e9b8532eSDong Zhou uint8_t tver:4; /**< Transport Header Version. */ 37e9b8532eSDong Zhou #endif 38e9b8532eSDong Zhou rte_be16_t pkey; /**< Partition key. */ 39e9b8532eSDong Zhou #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 40e9b8532eSDong Zhou uint8_t rsvd0:6; /**< Reserved. */ 41e9b8532eSDong Zhou uint8_t b:1; /**< BECN. */ 42e9b8532eSDong Zhou uint8_t f:1; /**< FECN. */ 43e9b8532eSDong Zhou #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 44e9b8532eSDong Zhou uint8_t f:1; /**< FECN. */ 45e9b8532eSDong Zhou uint8_t b:1; /**< BECN. */ 46e9b8532eSDong Zhou uint8_t rsvd0:6; /**< Reserved. */ 47e9b8532eSDong Zhou #endif 48e9b8532eSDong Zhou uint8_t dst_qp[3]; /**< Destination QP */ 49e9b8532eSDong Zhou #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 50e9b8532eSDong Zhou uint8_t rsvd1:7; /**< Reserved. */ 51e9b8532eSDong Zhou uint8_t a:1; /**< Acknowledge Request. */ 52e9b8532eSDong Zhou #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 53e9b8532eSDong Zhou uint8_t a:1; /**< Acknowledge Request. */ 54e9b8532eSDong Zhou uint8_t rsvd1:7; /**< Reserved. */ 55e9b8532eSDong Zhou #endif 56e9b8532eSDong Zhou uint8_t psn[3]; /**< Packet Sequence Number */ 57*fba98755SAndre Muezerie } __rte_packed_end; 58e9b8532eSDong Zhou 59e9b8532eSDong Zhou /** RoCEv2 default port. */ 60e9b8532eSDong Zhou #define RTE_ROCEV2_DEFAULT_PORT 4791 61e9b8532eSDong Zhou 62e9b8532eSDong Zhou #endif /* RTE_IB_H */ 63