199a2dd95SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 299a2dd95SBruce Richardson * Copyright(c) 2015 Cavium, Inc 399a2dd95SBruce Richardson */ 499a2dd95SBruce Richardson 599a2dd95SBruce Richardson #ifndef _RTE_CPUFLAGS_ARM64_H_ 699a2dd95SBruce Richardson #define _RTE_CPUFLAGS_ARM64_H_ 799a2dd95SBruce Richardson 899a2dd95SBruce Richardson /** 999a2dd95SBruce Richardson * Enumeration of all CPU features supported 1099a2dd95SBruce Richardson */ 1199a2dd95SBruce Richardson enum rte_cpu_flag_t { 12*c9083dafSWathsala Vithanage /* Floating point capability */ 1399a2dd95SBruce Richardson RTE_CPUFLAG_FP = 0, 14*c9083dafSWathsala Vithanage 15*c9083dafSWathsala Vithanage /* Arm Neon extension */ 1699a2dd95SBruce Richardson RTE_CPUFLAG_NEON, 17*c9083dafSWathsala Vithanage 18*c9083dafSWathsala Vithanage /* Generic timer event stream */ 1999a2dd95SBruce Richardson RTE_CPUFLAG_EVTSTRM, 20*c9083dafSWathsala Vithanage 21*c9083dafSWathsala Vithanage /* AES instructions */ 2299a2dd95SBruce Richardson RTE_CPUFLAG_AES, 23*c9083dafSWathsala Vithanage 24*c9083dafSWathsala Vithanage /* Polynomial multiply long instruction */ 2599a2dd95SBruce Richardson RTE_CPUFLAG_PMULL, 26*c9083dafSWathsala Vithanage 27*c9083dafSWathsala Vithanage /* SHA1 instructions */ 2899a2dd95SBruce Richardson RTE_CPUFLAG_SHA1, 29*c9083dafSWathsala Vithanage 30*c9083dafSWathsala Vithanage /* SHA2 instructions */ 3199a2dd95SBruce Richardson RTE_CPUFLAG_SHA2, 32*c9083dafSWathsala Vithanage 33*c9083dafSWathsala Vithanage /* CRC32 instruction */ 3499a2dd95SBruce Richardson RTE_CPUFLAG_CRC32, 35*c9083dafSWathsala Vithanage 36*c9083dafSWathsala Vithanage /* 37*c9083dafSWathsala Vithanage * LDADD, LDCLR, LDEOR, LDSET, LDSMAX, LDSMIN, LDUMAX, LDUMIN, CAS, 38*c9083dafSWathsala Vithanage * CASP, and SWP instructions 39*c9083dafSWathsala Vithanage */ 4099a2dd95SBruce Richardson RTE_CPUFLAG_ATOMICS, 41*c9083dafSWathsala Vithanage 42*c9083dafSWathsala Vithanage /* Arm SVE extension */ 4399a2dd95SBruce Richardson RTE_CPUFLAG_SVE, 44*c9083dafSWathsala Vithanage 45*c9083dafSWathsala Vithanage /* Arm SVE2 extension */ 4699a2dd95SBruce Richardson RTE_CPUFLAG_SVE2, 47*c9083dafSWathsala Vithanage 48*c9083dafSWathsala Vithanage /* SVE-AES instructions */ 4999a2dd95SBruce Richardson RTE_CPUFLAG_SVEAES, 50*c9083dafSWathsala Vithanage 51*c9083dafSWathsala Vithanage /* SVE-PMULL instruction */ 5299a2dd95SBruce Richardson RTE_CPUFLAG_SVEPMULL, 53*c9083dafSWathsala Vithanage 54*c9083dafSWathsala Vithanage /* SVE bit permute instructions */ 5599a2dd95SBruce Richardson RTE_CPUFLAG_SVEBITPERM, 56*c9083dafSWathsala Vithanage 57*c9083dafSWathsala Vithanage /* SVE-SHA3 instructions */ 5899a2dd95SBruce Richardson RTE_CPUFLAG_SVESHA3, 59*c9083dafSWathsala Vithanage 60*c9083dafSWathsala Vithanage /* SVE-SM4 instructions */ 6199a2dd95SBruce Richardson RTE_CPUFLAG_SVESM4, 62*c9083dafSWathsala Vithanage 63*c9083dafSWathsala Vithanage /* CFINV, RMIF, SETF16, SETF8, AXFLAG, and XAFLAG instructions */ 6499a2dd95SBruce Richardson RTE_CPUFLAG_FLAGM2, 65*c9083dafSWathsala Vithanage 66*c9083dafSWathsala Vithanage /* FRINT32Z, FRINT32X, FRINT64Z, and FRINT64X instructions */ 6799a2dd95SBruce Richardson RTE_CPUFLAG_FRINT, 68*c9083dafSWathsala Vithanage 69*c9083dafSWathsala Vithanage /* SVE Int8 matrix multiplication instructions */ 7099a2dd95SBruce Richardson RTE_CPUFLAG_SVEI8MM, 71*c9083dafSWathsala Vithanage 72*c9083dafSWathsala Vithanage /* SVE FP32 floating-point matrix multiplication instructions */ 7399a2dd95SBruce Richardson RTE_CPUFLAG_SVEF32MM, 74*c9083dafSWathsala Vithanage 75*c9083dafSWathsala Vithanage /* SVE FP64 floating-point matrix multiplication instructions */ 7699a2dd95SBruce Richardson RTE_CPUFLAG_SVEF64MM, 77*c9083dafSWathsala Vithanage 78*c9083dafSWathsala Vithanage /* SVE BFloat16 instructions */ 7999a2dd95SBruce Richardson RTE_CPUFLAG_SVEBF16, 80*c9083dafSWathsala Vithanage 81*c9083dafSWathsala Vithanage /* 64 bit execution state of the Arm architecture */ 8299a2dd95SBruce Richardson RTE_CPUFLAG_AARCH64, 832f1a90f0SWathsala Vithanage 842f1a90f0SWathsala Vithanage /* WFET and WFIT instructions */ 852f1a90f0SWathsala Vithanage RTE_CPUFLAG_WFXT, 8699a2dd95SBruce Richardson }; 8799a2dd95SBruce Richardson 8899a2dd95SBruce Richardson #include "generic/rte_cpuflags.h" 8999a2dd95SBruce Richardson 9099a2dd95SBruce Richardson #endif /* _RTE_CPUFLAGS_ARM64_H_ */ 91