xref: /dpdk/lib/bbdev/rte_bbdev_op.h (revision 909a13331668883b5f997773123d2a34ad5e079d)
199a2dd95SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
299a2dd95SBruce Richardson  * Copyright(c) 2017 Intel Corporation
399a2dd95SBruce Richardson  */
499a2dd95SBruce Richardson 
599a2dd95SBruce Richardson #ifndef _RTE_BBDEV_OP_H_
699a2dd95SBruce Richardson #define _RTE_BBDEV_OP_H_
799a2dd95SBruce Richardson 
899a2dd95SBruce Richardson /**
999a2dd95SBruce Richardson  * @file rte_bbdev_op.h
1099a2dd95SBruce Richardson  *
1199a2dd95SBruce Richardson  * Defines wireless base band layer 1 operations and capabilities
1299a2dd95SBruce Richardson  */
1399a2dd95SBruce Richardson 
1499a2dd95SBruce Richardson #include <stdint.h>
1599a2dd95SBruce Richardson 
161094dd94SDavid Marchand #include <rte_compat.h>
1799a2dd95SBruce Richardson #include <rte_common.h>
1899a2dd95SBruce Richardson #include <rte_mbuf.h>
1999a2dd95SBruce Richardson #include <rte_memory.h>
2099a2dd95SBruce Richardson #include <rte_mempool.h>
2199a2dd95SBruce Richardson 
22719834a6SMattias Rönnblom #ifdef __cplusplus
23719834a6SMattias Rönnblom extern "C" {
24719834a6SMattias Rönnblom #endif
25719834a6SMattias Rönnblom 
2699a2dd95SBruce Richardson /* Number of columns in sub-block interleaver (36.212, section 5.1.4.1.1) */
2799a2dd95SBruce Richardson #define RTE_BBDEV_TURBO_C_SUBBLOCK (32)
2899a2dd95SBruce Richardson /* Maximum size of Transport Block (36.213, Table, Table 7.1.7.2.5-1) */
2999a2dd95SBruce Richardson #define RTE_BBDEV_TURBO_MAX_TB_SIZE (391656)
3099a2dd95SBruce Richardson /* Maximum size of Code Block (36.212, Table 5.1.3-3) */
3199a2dd95SBruce Richardson #define RTE_BBDEV_TURBO_MAX_CB_SIZE (6144)
3299a2dd95SBruce Richardson /* Maximum size of Code Block */
3399a2dd95SBruce Richardson #define RTE_BBDEV_LDPC_MAX_CB_SIZE (8448)
3499a2dd95SBruce Richardson /* Minimum size of Code Block */
3599a2dd95SBruce Richardson #define RTE_BBDEV_LDPC_MIN_CB_SIZE (40)
3699a2dd95SBruce Richardson /* Maximum E size we can manage with default mbuf */
3799a2dd95SBruce Richardson #define RTE_BBDEV_LDPC_E_MAX_MBUF (64000)
3899a2dd95SBruce Richardson /* Minimum size of Code Block (36.212, Table 5.1.3-3) */
3999a2dd95SBruce Richardson #define RTE_BBDEV_TURBO_MIN_CB_SIZE (40)
4099a2dd95SBruce Richardson /* Maximum size of circular buffer */
4199a2dd95SBruce Richardson #define RTE_BBDEV_TURBO_MAX_KW (18528)
4299a2dd95SBruce Richardson /*
4399a2dd95SBruce Richardson  * Turbo: Maximum number of Code Blocks in Transport Block. It is calculated
4499a2dd95SBruce Richardson  * based on maximum size of one Code Block and one Transport Block
4599a2dd95SBruce Richardson  * (considering CRC24A and CRC24B):
4699a2dd95SBruce Richardson  * (391656 + 24) / (6144 - 24) = 64
4799a2dd95SBruce Richardson  */
4899a2dd95SBruce Richardson #define RTE_BBDEV_TURBO_MAX_CODE_BLOCKS (64)
4999a2dd95SBruce Richardson /* LDPC:  Maximum number of Code Blocks in Transport Block.*/
5099a2dd95SBruce Richardson #define RTE_BBDEV_LDPC_MAX_CODE_BLOCKS (256)
519d393325SNicolas Chautru /* 12 CS maximum */
529d393325SNicolas Chautru #define RTE_BBDEV_MAX_CS_2 (6)
530aa8b208SNicolas Chautru #define RTE_BBDEV_MAX_CS   (12)
54089148fcSNicolas Chautru /* MLD-TS up to 4 layers */
55089148fcSNicolas Chautru #define RTE_BBDEV_MAX_MLD_LAYERS (4)
56089148fcSNicolas Chautru /* 12 SB per RB */
57089148fcSNicolas Chautru #define RTE_BBDEV_SCPERRB (12)
5899a2dd95SBruce Richardson 
59e70212ccSNicolas Chautru /*
60e70212ccSNicolas Chautru  * Maximum size to be used to manage the enum rte_bbdev_op_type
61e70212ccSNicolas Chautru  * including padding for future enum insertion.
62e70212ccSNicolas Chautru  * The enum values must be explicitly kept smaller or equal to this padded maximum size.
63e70212ccSNicolas Chautru  */
64e70212ccSNicolas Chautru #define RTE_BBDEV_OP_TYPE_SIZE_MAX 8
65e70212ccSNicolas Chautru 
6699a2dd95SBruce Richardson /** Flags for turbo decoder operation and capability structure */
6799a2dd95SBruce Richardson enum rte_bbdev_op_td_flag_bitmasks {
6899a2dd95SBruce Richardson 	/** If sub block de-interleaving is to be performed. */
6999a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE = (1ULL << 0),
7099a2dd95SBruce Richardson 	/** To use CRC Type 24B (otherwise use CRC Type 24A). */
7199a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_CRC_TYPE_24B = (1ULL << 1),
7299a2dd95SBruce Richardson 	/** If turbo equalization is to be performed. */
7399a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_EQUALIZER = (1ULL << 2),
7499a2dd95SBruce Richardson 	/** If set, saturate soft output to +/-127 */
7599a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_SOFT_OUT_SATURATE = (1ULL << 3),
7699a2dd95SBruce Richardson 	/** Set to 1 to start iteration from even, else odd; one iteration =
7799a2dd95SBruce Richardson 	 * max_iteration + 0.5
7899a2dd95SBruce Richardson 	 */
7999a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_HALF_ITERATION_EVEN = (1ULL << 4),
8099a2dd95SBruce Richardson 	/** If 0, TD stops after CRC matches; else if 1, runs to end of next
8199a2dd95SBruce Richardson 	 * odd iteration after CRC matches
8299a2dd95SBruce Richardson 	 */
8399a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH = (1ULL << 5),
8499a2dd95SBruce Richardson 	/** Set if soft output is required to be output  */
8599a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_SOFT_OUTPUT = (1ULL << 6),
8699a2dd95SBruce Richardson 	/** Set to enable early termination mode */
8799a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_EARLY_TERMINATION = (1ULL << 7),
8899a2dd95SBruce Richardson 	/** Set if a device supports decoder dequeue interrupts */
8999a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_DEC_INTERRUPTS = (1ULL << 9),
9099a2dd95SBruce Richardson 	/** Set if positive LLR encoded input is supported. Positive LLR value
9199a2dd95SBruce Richardson 	 * represents the level of confidence for bit '1', and vice versa for
9299a2dd95SBruce Richardson 	 * bit '0'.
9399a2dd95SBruce Richardson 	 * This is mutually exclusive with RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN
9499a2dd95SBruce Richardson 	 * when used to formalize the input data format.
9599a2dd95SBruce Richardson 	 */
9699a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN = (1ULL << 10),
9799a2dd95SBruce Richardson 	/** Set if negative LLR encoded input is supported. Negative LLR value
9899a2dd95SBruce Richardson 	 * represents the level of confidence for bit '1', and vice versa for
9999a2dd95SBruce Richardson 	 * bit '0'.
10099a2dd95SBruce Richardson 	 * This is mutually exclusive with RTE_BBDEV_TURBO_POS_LLR_1_BIT_IN
10199a2dd95SBruce Richardson 	 * when used to formalize the input data format.
10299a2dd95SBruce Richardson 	 */
10399a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN = (1ULL << 11),
10499a2dd95SBruce Richardson 	/** Set if positive LLR soft output is supported. Positive LLR value
10599a2dd95SBruce Richardson 	 * represents the level of confidence for bit '1', and vice versa for
10699a2dd95SBruce Richardson 	 * bit '0'.
10799a2dd95SBruce Richardson 	 * This is mutually exclusive with
10899a2dd95SBruce Richardson 	 * RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT when used to formalize
10999a2dd95SBruce Richardson 	 * the input data format.
11099a2dd95SBruce Richardson 	 */
11199a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_POS_LLR_1_BIT_SOFT_OUT = (1ULL << 12),
11299a2dd95SBruce Richardson 	/** Set if negative LLR soft output is supported. Negative LLR value
11399a2dd95SBruce Richardson 	 * represents the level of confidence for bit '1', and vice versa for
11499a2dd95SBruce Richardson 	 * bit '0'.
11599a2dd95SBruce Richardson 	 * This is mutually exclusive with
11699a2dd95SBruce Richardson 	 * RTE_BBDEV_TURBO_POS_LLR_1_BIT_SOFT_OUT when used to formalize the
11799a2dd95SBruce Richardson 	 * input data format.
11899a2dd95SBruce Richardson 	 */
11999a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT = (1ULL << 13),
12099a2dd95SBruce Richardson 	/** Set if driver supports flexible parallel MAP engine decoding. If
12199a2dd95SBruce Richardson 	 * not supported, num_maps (number of MAP engines) argument is unusable.
12299a2dd95SBruce Richardson 	 */
12399a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_MAP_DEC = (1ULL << 14),
12499a2dd95SBruce Richardson 	/** Set if a device supports scatter-gather functionality */
12599a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_DEC_SCATTER_GATHER = (1ULL << 15),
12699a2dd95SBruce Richardson 	/** Set to keep CRC24B bits appended while decoding. Only usable when
12799a2dd95SBruce Richardson 	 * decoding Transport Block mode.
12899a2dd95SBruce Richardson 	 */
12910ea15e3SNicolas Chautru 	RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP = (1ULL << 16),
13010ea15e3SNicolas Chautru 	/** Set to drop CRC24B bits not to be appended while decoding.
13110ea15e3SNicolas Chautru 	 */
13210ea15e3SNicolas Chautru 	RTE_BBDEV_TURBO_DEC_CRC_24B_DROP = (1ULL << 17)
13399a2dd95SBruce Richardson };
13499a2dd95SBruce Richardson 
13599a2dd95SBruce Richardson 
13699a2dd95SBruce Richardson /** Flags for turbo encoder operation and capability structure */
13799a2dd95SBruce Richardson enum rte_bbdev_op_te_flag_bitmasks {
13899a2dd95SBruce Richardson 	/** Ignore rv_index and set K0 = 0 */
13999a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_RV_INDEX_BYPASS = (1ULL << 0),
14099a2dd95SBruce Richardson 	/** If rate matching is to be performed */
14199a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_RATE_MATCH = (1ULL << 1),
14299a2dd95SBruce Richardson 	/** This bit must be set to enable CRC-24B generation */
14399a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_CRC_24B_ATTACH = (1ULL << 2),
14499a2dd95SBruce Richardson 	/** This bit must be set to enable CRC-24A generation */
14599a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_CRC_24A_ATTACH = (1ULL << 3),
14699a2dd95SBruce Richardson 	/** Set if a device supports encoder dequeue interrupts */
14799a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_ENC_INTERRUPTS = (1ULL << 4),
14899a2dd95SBruce Richardson 	/** Set if a device supports scatter-gather functionality */
14999a2dd95SBruce Richardson 	RTE_BBDEV_TURBO_ENC_SCATTER_GATHER = (1ULL << 5)
15099a2dd95SBruce Richardson };
15199a2dd95SBruce Richardson 
15299a2dd95SBruce Richardson /** Flags for LDPC decoder operation and capability structure */
15399a2dd95SBruce Richardson enum rte_bbdev_op_ldpcdec_flag_bitmasks {
15499a2dd95SBruce Richardson 	/** Set for transport block CRC-24A checking */
15599a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK = (1ULL << 0),
15699a2dd95SBruce Richardson 	/** Set for code block CRC-24B checking */
15799a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK = (1ULL << 1),
15899a2dd95SBruce Richardson 	/** Set to drop the last CRC bits decoding output */
15999a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP = (1ULL << 2),
160cc360fd3SNicolas Chautru 	/** Set for transport block CRC-16 checking */
161cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_CRC_TYPE_16_CHECK = (1ULL << 3),
16299a2dd95SBruce Richardson 	/** Set for bit-level de-interleaver bypass on Rx stream. */
163cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS = (1ULL << 4),
16499a2dd95SBruce Richardson 	/** Set for HARQ combined input stream enable. */
165cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE = (1ULL << 5),
16699a2dd95SBruce Richardson 	/** Set for HARQ combined output stream enable. */
167cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE = (1ULL << 6),
16899a2dd95SBruce Richardson 	/** Set for LDPC decoder bypass.
16999a2dd95SBruce Richardson 	 *  RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE must be set.
17099a2dd95SBruce Richardson 	 */
171cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_DECODE_BYPASS = (1ULL << 7),
17299a2dd95SBruce Richardson 	/** Set for soft-output stream enable */
173cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_SOFT_OUT_ENABLE = (1ULL << 8),
17499a2dd95SBruce Richardson 	/** Set for Rate-Matching bypass on soft-out stream. */
175cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS = (1ULL << 9),
17699a2dd95SBruce Richardson 	/** Set for bit-level de-interleaver bypass on soft-output stream. */
177cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS = (1ULL << 10),
17899a2dd95SBruce Richardson 	/** Set for iteration stopping on successful decode condition
17999a2dd95SBruce Richardson 	 *  i.e. a successful syndrome check.
18099a2dd95SBruce Richardson 	 */
181cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE = (1ULL << 11),
18299a2dd95SBruce Richardson 	/** Set if a device supports decoder dequeue interrupts. */
183cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_DEC_INTERRUPTS = (1ULL << 12),
18499a2dd95SBruce Richardson 	/** Set if a device supports scatter-gather functionality. */
185cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_DEC_SCATTER_GATHER = (1ULL << 13),
18699a2dd95SBruce Richardson 	/** Set if a device supports input/output HARQ compression. */
187cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION = (1ULL << 14),
18899a2dd95SBruce Richardson 	/** Set if a device supports input LLR compression. */
189cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_LLR_COMPRESSION = (1ULL << 15),
19099a2dd95SBruce Richardson 	/** Set if a device supports HARQ input from
19199a2dd95SBruce Richardson 	 *  device's internal memory.
19299a2dd95SBruce Richardson 	 */
193cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE = (1ULL << 16),
19499a2dd95SBruce Richardson 	/** Set if a device supports HARQ output to
19599a2dd95SBruce Richardson 	 *  device's internal memory.
19699a2dd95SBruce Richardson 	 */
197cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE = (1ULL << 17),
19899a2dd95SBruce Richardson 	/** Set if a device supports loop-back access to
19999a2dd95SBruce Richardson 	 *  HARQ internal memory. Intended for troubleshooting.
20099a2dd95SBruce Richardson 	 */
201cc360fd3SNicolas Chautru 	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK = (1ULL << 18),
20299a2dd95SBruce Richardson 	/** Set if a device includes LLR filler bits in the circular buffer
20399a2dd95SBruce Richardson 	 *  for HARQ memory. If not set, it is assumed the filler bits are not
20499a2dd95SBruce Richardson 	 *  in HARQ memory and handled directly by the LDPC decoder.
20599a2dd95SBruce Richardson 	 */
206f4e6c4efSNicolas Chautru 	RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS = (1ULL << 19),
207f4e6c4efSNicolas Chautru 	/** Set if a device supports input/output HARQ 4bits compression. */
208f4e6c4efSNicolas Chautru 	RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION = (1ULL << 20)
20999a2dd95SBruce Richardson };
21099a2dd95SBruce Richardson 
21199a2dd95SBruce Richardson /** Flags for LDPC encoder operation and capability structure */
21299a2dd95SBruce Richardson enum rte_bbdev_op_ldpcenc_flag_bitmasks {
21399a2dd95SBruce Richardson 	/** Set for bit-level interleaver bypass on output stream. */
21499a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_INTERLEAVER_BYPASS = (1ULL << 0),
21599a2dd95SBruce Richardson 	/** If rate matching is to be performed */
21699a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_RATE_MATCH = (1ULL << 1),
21799a2dd95SBruce Richardson 	/** Set for transport block CRC-24A attach */
21899a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_CRC_24A_ATTACH = (1ULL << 2),
21999a2dd95SBruce Richardson 	/** Set for code block CRC-24B attach */
22099a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_CRC_24B_ATTACH = (1ULL << 3),
22199a2dd95SBruce Richardson 	/** Set for code block CRC-16 attach */
22299a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_CRC_16_ATTACH = (1ULL << 4),
22399a2dd95SBruce Richardson 	/** Set if a device supports encoder dequeue interrupts. */
22499a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_ENC_INTERRUPTS = (1ULL << 5),
22599a2dd95SBruce Richardson 	/** Set if a device supports scatter-gather functionality. */
22699a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_ENC_SCATTER_GATHER = (1ULL << 6),
22799a2dd95SBruce Richardson 	/** Set if a device supports concatenation of non byte aligned output */
22899a2dd95SBruce Richardson 	RTE_BBDEV_LDPC_ENC_CONCATENATION = (1ULL << 7)
22999a2dd95SBruce Richardson };
23099a2dd95SBruce Richardson 
2319d393325SNicolas Chautru /** Flags for FFT operation and capability structure. */
2329d393325SNicolas Chautru enum rte_bbdev_op_fft_flag_bitmasks {
2339d393325SNicolas Chautru 	/** Flexible windowing capability. */
2349d393325SNicolas Chautru 	RTE_BBDEV_FFT_WINDOWING = (1ULL << 0),
2359d393325SNicolas Chautru 	/** Flexible adjustment of Cyclic Shift time offset. */
2369d393325SNicolas Chautru 	RTE_BBDEV_FFT_CS_ADJUSTMENT = (1ULL << 1),
2379d393325SNicolas Chautru 	/** Set for bypass the DFT and get directly into iDFT input. */
2389d393325SNicolas Chautru 	RTE_BBDEV_FFT_DFT_BYPASS = (1ULL << 2),
2399d393325SNicolas Chautru 	/** Set for bypass the IDFT and get directly the DFT output. */
2409d393325SNicolas Chautru 	RTE_BBDEV_FFT_IDFT_BYPASS = (1ULL << 3),
2419d393325SNicolas Chautru 	/** Set for bypass time domain windowing. */
2429d393325SNicolas Chautru 	RTE_BBDEV_FFT_WINDOWING_BYPASS = (1ULL << 4),
2439d393325SNicolas Chautru 	/** Set for optional power measurement on DFT output. */
2449d393325SNicolas Chautru 	RTE_BBDEV_FFT_POWER_MEAS = (1ULL << 5),
2459d393325SNicolas Chautru 	/** Set if the input data used FP16 format. */
2469d393325SNicolas Chautru 	RTE_BBDEV_FFT_FP16_INPUT = (1ULL << 6),
2479d393325SNicolas Chautru 	/** Set if the output data uses FP16 format. */
2480aa8b208SNicolas Chautru 	RTE_BBDEV_FFT_FP16_OUTPUT = (1ULL << 7),
2490aa8b208SNicolas Chautru 	/** Flexible adjustment of Timing offset adjustment per CS. */
2500aa8b208SNicolas Chautru 	RTE_BBDEV_FFT_TIMING_OFFSET_PER_CS = (1ULL << 8),
2510aa8b208SNicolas Chautru 	/** Flexible adjustment of Timing error correction per CS. */
2520aa8b208SNicolas Chautru 	RTE_BBDEV_FFT_TIMING_ERROR = (1ULL << 9),
2530aa8b208SNicolas Chautru 	/** Set for optional frequency domain dewindowing. */
2540aa8b208SNicolas Chautru 	RTE_BBDEV_FFT_DEWINDOWING = (1ULL << 10),
2550aa8b208SNicolas Chautru 	/** Flexible adjustment of frequency resampling mode. */
2560aa8b208SNicolas Chautru 	RTE_BBDEV_FFT_FREQ_RESAMPLING = (1ULL << 11)
2579d393325SNicolas Chautru };
2589d393325SNicolas Chautru 
259089148fcSNicolas Chautru /** Flags for MLDTS operation and capability structure */
260089148fcSNicolas Chautru enum rte_bbdev_op_mldts_flag_bitmasks {
261089148fcSNicolas Chautru 	/**  Set if the device supports C/R repetition options.  */
262089148fcSNicolas Chautru 	RTE_BBDEV_MLDTS_REP = (1ULL << 0),
263089148fcSNicolas Chautru };
264089148fcSNicolas Chautru 
26599a2dd95SBruce Richardson /** Flags for the Code Block/Transport block mode  */
26699a2dd95SBruce Richardson enum rte_bbdev_op_cb_mode {
26799a2dd95SBruce Richardson 	/** One operation is one or fraction of one transport block  */
26899a2dd95SBruce Richardson 	RTE_BBDEV_TRANSPORT_BLOCK = 0,
26999a2dd95SBruce Richardson 	/** One operation is one code block mode */
27099a2dd95SBruce Richardson 	RTE_BBDEV_CODE_BLOCK = 1,
27199a2dd95SBruce Richardson };
27299a2dd95SBruce Richardson 
27399a2dd95SBruce Richardson /** Data input and output buffer for BBDEV operations */
27499a2dd95SBruce Richardson struct rte_bbdev_op_data {
27599a2dd95SBruce Richardson 	/** The mbuf data structure representing the data for BBDEV operation.
27699a2dd95SBruce Richardson 	 *
27799a2dd95SBruce Richardson 	 * This mbuf pointer can point to one Code Block (CB) data buffer or
27899a2dd95SBruce Richardson 	 * multiple CBs contiguously located next to each other.
27999a2dd95SBruce Richardson 	 * A Transport Block (TB) represents a whole piece of data that is
28099a2dd95SBruce Richardson 	 * divided into one or more CBs. Maximum number of CBs can be contained
28199a2dd95SBruce Richardson 	 * in one TB is defined by RTE_BBDEV_(TURBO/LDPC)_MAX_CODE_BLOCKS.
28299a2dd95SBruce Richardson 	 *
28399a2dd95SBruce Richardson 	 * An mbuf data structure cannot represent more than one TB. The
28499a2dd95SBruce Richardson 	 * smallest piece of data that can be contained in one mbuf is one CB.
28599a2dd95SBruce Richardson 	 * An mbuf can include one contiguous CB, subset of contiguous CBs that
28699a2dd95SBruce Richardson 	 * are belonging to one TB, or all contiguous CBs that are belonging to
28799a2dd95SBruce Richardson 	 * one TB.
28899a2dd95SBruce Richardson 	 *
28999a2dd95SBruce Richardson 	 * If a BBDEV PMD supports the extended capability "Scatter-Gather",
29099a2dd95SBruce Richardson 	 * then it is capable of collecting (gathering) non-contiguous
29199a2dd95SBruce Richardson 	 * (scattered) data from multiple locations in the memory.
29299a2dd95SBruce Richardson 	 * This capability is reported by the capability flags:
29399a2dd95SBruce Richardson 	 * - RTE_BBDEV_(TURBO/LDPC)_ENC_SCATTER_GATHER and
29499a2dd95SBruce Richardson 	 * - RTE_BBDEV_(TURBO/LDPC)_DEC_SCATTER_GATHER.
29599a2dd95SBruce Richardson 	 * Only if a BBDEV PMD supports this feature, chained mbuf data
29699a2dd95SBruce Richardson 	 * structures are accepted. A chained mbuf can represent one
29799a2dd95SBruce Richardson 	 * non-contiguous CB or multiple non-contiguous CBs.
29899a2dd95SBruce Richardson 	 * If BBDEV PMD does not support this feature, it will assume inbound
29999a2dd95SBruce Richardson 	 * mbuf data contains one segment.
30099a2dd95SBruce Richardson 	 *
30199a2dd95SBruce Richardson 	 * The output mbuf data though is always one segment, even if the input
30299a2dd95SBruce Richardson 	 * was a chained mbuf.
30399a2dd95SBruce Richardson 	 */
30499a2dd95SBruce Richardson 	struct rte_mbuf *data;
30599a2dd95SBruce Richardson 	/** The starting point of the BBDEV (encode/decode) operation,
30699a2dd95SBruce Richardson 	 * in bytes.
30799a2dd95SBruce Richardson 	 *
30899a2dd95SBruce Richardson 	 * BBDEV starts to read data past this offset.
30999a2dd95SBruce Richardson 	 * In case of chained mbuf, this offset applies only to the first mbuf
31099a2dd95SBruce Richardson 	 * segment.
31199a2dd95SBruce Richardson 	 */
31299a2dd95SBruce Richardson 	uint32_t offset;
31399a2dd95SBruce Richardson 	/** The total data length to be processed in one operation, in bytes.
31499a2dd95SBruce Richardson 	 *
31599a2dd95SBruce Richardson 	 * In case the mbuf data is representing one CB, this is the length of
31699a2dd95SBruce Richardson 	 * the CB undergoing the operation.
31799a2dd95SBruce Richardson 	 * If it's for multiple CBs, this is the total length of those CBs
31899a2dd95SBruce Richardson 	 * undergoing the operation.
31999a2dd95SBruce Richardson 	 * If it is for one TB, this is the total length of the TB under
32099a2dd95SBruce Richardson 	 * operation.
32199a2dd95SBruce Richardson 	 *
32299a2dd95SBruce Richardson 	 * In case of chained mbuf, this data length includes the lengths of the
32399a2dd95SBruce Richardson 	 * "scattered" data segments undergoing the operation.
32499a2dd95SBruce Richardson 	 */
32599a2dd95SBruce Richardson 	uint32_t length;
32699a2dd95SBruce Richardson };
32799a2dd95SBruce Richardson 
32899a2dd95SBruce Richardson /** Turbo decode code block parameters */
32999a2dd95SBruce Richardson struct rte_bbdev_op_dec_turbo_cb_params {
33099a2dd95SBruce Richardson 	/** The K size of the input CB, in bits [40:6144], as specified in
33199a2dd95SBruce Richardson 	 * 3GPP TS 36.212.
33299a2dd95SBruce Richardson 	 * This size is inclusive of CRC bits, regardless whether it was
33399a2dd95SBruce Richardson 	 * pre-calculated by the application or not.
33499a2dd95SBruce Richardson 	 */
33599a2dd95SBruce Richardson 	uint16_t k;
33699a2dd95SBruce Richardson 	/** The E length of the CB rate matched LLR output, in bytes, as in
33799a2dd95SBruce Richardson 	 * 3GPP TS 36.212.
33899a2dd95SBruce Richardson 	 */
33999a2dd95SBruce Richardson 	uint32_t e;
34099a2dd95SBruce Richardson };
34199a2dd95SBruce Richardson 
34299a2dd95SBruce Richardson /** LDPC decode code block parameters */
34399a2dd95SBruce Richardson struct rte_bbdev_op_dec_ldpc_cb_params {
34499a2dd95SBruce Richardson 	/** Rate matching output sequence length in bits or LLRs.
34599a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.1]
34699a2dd95SBruce Richardson 	 */
34799a2dd95SBruce Richardson 	uint32_t e;
34899a2dd95SBruce Richardson };
34999a2dd95SBruce Richardson 
35099a2dd95SBruce Richardson /** Turbo decode transport block parameters */
35199a2dd95SBruce Richardson struct rte_bbdev_op_dec_turbo_tb_params {
35299a2dd95SBruce Richardson 	/** The K- size of the input CB, in bits [40:6144], that is in the
35399a2dd95SBruce Richardson 	 * Turbo operation when r < C-, as in 3GPP TS 36.212.
35499a2dd95SBruce Richardson 	 */
35599a2dd95SBruce Richardson 	uint16_t k_neg;
35699a2dd95SBruce Richardson 	/** The K+ size of the input CB, in bits [40:6144], that is in the
35799a2dd95SBruce Richardson 	 * Turbo operation when r >= C-, as in 3GPP TS 36.212.
35899a2dd95SBruce Richardson 	 */
35999a2dd95SBruce Richardson 	uint16_t k_pos;
36099a2dd95SBruce Richardson 	/** The number of CBs that have K- size, [0:63] */
36199a2dd95SBruce Richardson 	uint8_t c_neg;
36299a2dd95SBruce Richardson 	/** The total number of CBs in the TB,
36399a2dd95SBruce Richardson 	 * [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS]
36499a2dd95SBruce Richardson 	 */
36599a2dd95SBruce Richardson 	uint8_t c;
36699a2dd95SBruce Richardson 	/** The number of CBs that uses Ea before switching to Eb, [0:63] */
36799a2dd95SBruce Richardson 	uint8_t cab;
36899a2dd95SBruce Richardson 	/** The E size of the CB rate matched output to use in the Turbo
36999a2dd95SBruce Richardson 	 * operation when r < cab
37099a2dd95SBruce Richardson 	 */
37199a2dd95SBruce Richardson 	uint32_t ea;
37299a2dd95SBruce Richardson 	/** The E size of the CB rate matched output to use in the Turbo
37399a2dd95SBruce Richardson 	 * operation when r >= cab
37499a2dd95SBruce Richardson 	 */
37599a2dd95SBruce Richardson 	uint32_t eb;
37699a2dd95SBruce Richardson 	/** The index of the first CB in the inbound mbuf data, default is 0 */
37799a2dd95SBruce Richardson 	uint8_t r;
37899a2dd95SBruce Richardson };
37999a2dd95SBruce Richardson 
38099a2dd95SBruce Richardson /** LDPC decode transport block parameters */
38199a2dd95SBruce Richardson struct rte_bbdev_op_dec_ldpc_tb_params {
38299a2dd95SBruce Richardson 	/** Ea, length after rate matching in bits, r < cab.
38399a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.1]
38499a2dd95SBruce Richardson 	 */
38599a2dd95SBruce Richardson 	uint32_t ea;
38699a2dd95SBruce Richardson 	/** Eb, length after rate matching in bits, r >= cab.
38799a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.1]
38899a2dd95SBruce Richardson 	 */
38999a2dd95SBruce Richardson 	uint32_t eb;
39099a2dd95SBruce Richardson 	/** The total number of CBs in the TB or partial TB
39199a2dd95SBruce Richardson 	 * [1:RTE_BBDEV_LDPC_MAX_CODE_BLOCKS]
39299a2dd95SBruce Richardson 	 */
39399a2dd95SBruce Richardson 	uint8_t c;
39499a2dd95SBruce Richardson 	/** The index of the first CB in the inbound mbuf data, default is 0 */
39599a2dd95SBruce Richardson 	uint8_t r;
39699a2dd95SBruce Richardson 	/** The number of CBs that use Ea before switching to Eb, [0:63] */
39799a2dd95SBruce Richardson 	uint8_t cab;
39899a2dd95SBruce Richardson };
39999a2dd95SBruce Richardson 
40099a2dd95SBruce Richardson /** Operation structure for Turbo decode.
40199a2dd95SBruce Richardson  * An operation can be performed on one CB at a time "CB-mode".
40299a2dd95SBruce Richardson  * An operation can be performed on one or multiple CBs that logically
40399a2dd95SBruce Richardson  * belong to one TB "TB-mode".
40499a2dd95SBruce Richardson  * The provided K size parameter of the CB is its size coming from the
40599a2dd95SBruce Richardson  * decode operation.
40699a2dd95SBruce Richardson  * CRC24A/B check is requested by the application by setting the flag
40799a2dd95SBruce Richardson  * RTE_BBDEV_TURBO_CRC_TYPE_24B for CRC24B check or CRC24A otherwise.
40899a2dd95SBruce Richardson  * In TB-mode, BBDEV concatenates the decoded CBs one next to the other with
40999a2dd95SBruce Richardson  * relevant CRC24B in between.
41099a2dd95SBruce Richardson  *
41199a2dd95SBruce Richardson  * The input encoded CB data is the Virtual Circular Buffer data stream, wk,
41299a2dd95SBruce Richardson  * with the null padding included as described in 3GPP TS 36.212
41399a2dd95SBruce Richardson  * section 5.1.4.1.2 and shown in 3GPP TS 36.212 section 5.1.4.1 Figure 5.1.4-1.
41499a2dd95SBruce Richardson  * The size of the virtual circular buffer is 3*Kpi, where Kpi is the 32 byte
41599a2dd95SBruce Richardson  * aligned value of K, as specified in 3GPP TS 36.212 section 5.1.4.1.1.
41699a2dd95SBruce Richardson  *
41799a2dd95SBruce Richardson  * Each byte in the input circular buffer is the LLR value of each bit of the
41899a2dd95SBruce Richardson  * original CB.
41999a2dd95SBruce Richardson  *
42099a2dd95SBruce Richardson  * Hard output is a mandatory capability that all BBDEV PMDs support. This is
42199a2dd95SBruce Richardson  * the decoded CBs of K sizes (CRC24A/B is the last 24-bit in each decoded CB).
42299a2dd95SBruce Richardson  * Soft output is an optional capability for BBDEV PMDs. If supported, an LLR
42399a2dd95SBruce Richardson  * rate matched output is computed in the soft_output buffer structure.
42499a2dd95SBruce Richardson  *
42599a2dd95SBruce Richardson  * The output mbuf data structure is expected to be allocated by the
42699a2dd95SBruce Richardson  * application with enough room for the output data.
42799a2dd95SBruce Richardson  */
428c49c880fSNicolas Chautru 
429c49c880fSNicolas Chautru /* Structure rte_bbdev_op_turbo_dec 8< */
43099a2dd95SBruce Richardson struct rte_bbdev_op_turbo_dec {
43199a2dd95SBruce Richardson 	/** The Virtual Circular Buffer, wk, size 3*Kpi for each CB */
43299a2dd95SBruce Richardson 	struct rte_bbdev_op_data input;
43399a2dd95SBruce Richardson 	/** The hard decisions buffer for the decoded output,
43499a2dd95SBruce Richardson 	 * size K for each CB
43599a2dd95SBruce Richardson 	 */
43699a2dd95SBruce Richardson 	struct rte_bbdev_op_data hard_output;
43799a2dd95SBruce Richardson 	/** The soft LLR output buffer - optional */
43899a2dd95SBruce Richardson 	struct rte_bbdev_op_data soft_output;
43999a2dd95SBruce Richardson 
44099a2dd95SBruce Richardson 	/** Flags from rte_bbdev_op_td_flag_bitmasks */
44199a2dd95SBruce Richardson 	uint32_t op_flags;
44299a2dd95SBruce Richardson 
44399a2dd95SBruce Richardson 	/** Rv index for rate matching [0:3] */
44499a2dd95SBruce Richardson 	uint8_t rv_index;
44599a2dd95SBruce Richardson 	/** The minimum number of iterations to perform in decoding all CBs in
44699a2dd95SBruce Richardson 	 * this operation - input
44799a2dd95SBruce Richardson 	 */
44899a2dd95SBruce Richardson 	uint8_t iter_min:4;
44999a2dd95SBruce Richardson 	/** The maximum number of iterations to perform in decoding all CBs in
45099a2dd95SBruce Richardson 	 * this operation - input
45199a2dd95SBruce Richardson 	 */
45299a2dd95SBruce Richardson 	uint8_t iter_max:4;
45399a2dd95SBruce Richardson 	/** The maximum number of iterations that were performed in decoding
45499a2dd95SBruce Richardson 	 * all CBs in this decode operation - output
45599a2dd95SBruce Richardson 	 */
45699a2dd95SBruce Richardson 	uint8_t iter_count;
45799a2dd95SBruce Richardson 	/** 5 bit extrinsic scale (scale factor on extrinsic info) */
45899a2dd95SBruce Richardson 	uint8_t ext_scale;
45999a2dd95SBruce Richardson 	/** Number of MAP engines to use in decode,
46099a2dd95SBruce Richardson 	 *  must be power of 2 (or 0 to auto-select)
46199a2dd95SBruce Richardson 	 */
46299a2dd95SBruce Richardson 	uint8_t num_maps;
46399a2dd95SBruce Richardson 
46499a2dd95SBruce Richardson 	/** [0 - TB : 1 - CB] */
46599a2dd95SBruce Richardson 	uint8_t code_block_mode;
46699a2dd95SBruce Richardson 	union {
46799a2dd95SBruce Richardson 		/** Struct which stores Code Block specific parameters */
46899a2dd95SBruce Richardson 		struct rte_bbdev_op_dec_turbo_cb_params cb_params;
46999a2dd95SBruce Richardson 		/** Struct which stores Transport Block specific parameters */
47099a2dd95SBruce Richardson 		struct rte_bbdev_op_dec_turbo_tb_params tb_params;
47199a2dd95SBruce Richardson 	};
47299a2dd95SBruce Richardson };
473c49c880fSNicolas Chautru /* >8 End of structure rte_bbdev_op_turbo_dec. */
47499a2dd95SBruce Richardson 
47599a2dd95SBruce Richardson /** Operation structure for LDPC decode.
47699a2dd95SBruce Richardson  *
47799a2dd95SBruce Richardson  * An operation can be performed on one CB at a time "CB-mode".
47899a2dd95SBruce Richardson  * An operation can also be performed on one or multiple CBs that logically
47999a2dd95SBruce Richardson  * belong to a TB "TB-mode" (Currently not supported).
48099a2dd95SBruce Richardson  *
48199a2dd95SBruce Richardson  * The input encoded CB data is the Virtual Circular Buffer data stream.
48299a2dd95SBruce Richardson  *
48399a2dd95SBruce Richardson  * Each byte in the input circular buffer is the LLR value of each bit of the
48499a2dd95SBruce Richardson  * original CB.
48599a2dd95SBruce Richardson  *
48699a2dd95SBruce Richardson  * Hard output is a mandatory capability that all BBDEV PMDs support. This is
48799a2dd95SBruce Richardson  * the decoded CBs (CRC24A/B is the last 24-bit in each decoded CB).
48899a2dd95SBruce Richardson  *
48999a2dd95SBruce Richardson  * Soft output is an optional capability for BBDEV PMDs. If supported, an LLR
49099a2dd95SBruce Richardson  * rate matched output is computed in the soft_output buffer structure.
49199a2dd95SBruce Richardson  * These are A Posteriori Probabilities (APP) LLR samples for coded bits.
49299a2dd95SBruce Richardson  *
49399a2dd95SBruce Richardson  * HARQ combined output is an optional capability for BBDEV PMDs.
49499a2dd95SBruce Richardson  * If supported, a LLR output is streamed to the harq_combined_output
49599a2dd95SBruce Richardson  * buffer.
49699a2dd95SBruce Richardson  *
49799a2dd95SBruce Richardson  * HARQ combined input is an optional capability for BBDEV PMDs.
49899a2dd95SBruce Richardson  * If supported, a LLR input is streamed from the harq_combined_input
49999a2dd95SBruce Richardson  * buffer.
50099a2dd95SBruce Richardson  *
50199a2dd95SBruce Richardson  * The output mbuf data structure is expected to be allocated by the
50299a2dd95SBruce Richardson  * application with enough room for the output data.
50399a2dd95SBruce Richardson  */
504c49c880fSNicolas Chautru 
505c49c880fSNicolas Chautru /* Structure rte_bbdev_op_ldpc_dec 8< */
50699a2dd95SBruce Richardson struct rte_bbdev_op_ldpc_dec {
50799a2dd95SBruce Richardson 	/** The Virtual Circular Buffer for this code block, one LLR
50899a2dd95SBruce Richardson 	 * per bit of the original CB.
50999a2dd95SBruce Richardson 	 */
51099a2dd95SBruce Richardson 	struct rte_bbdev_op_data input;
51199a2dd95SBruce Richardson 	/** The hard decisions buffer for the decoded output,
51299a2dd95SBruce Richardson 	 * size K for each CB
51399a2dd95SBruce Richardson 	 */
51499a2dd95SBruce Richardson 	struct rte_bbdev_op_data hard_output;
51599a2dd95SBruce Richardson 	/** The soft LLR output LLR stream buffer - optional */
51699a2dd95SBruce Richardson 	struct rte_bbdev_op_data soft_output;
51799a2dd95SBruce Richardson 	/** The HARQ combined LLR stream input buffer - optional */
51899a2dd95SBruce Richardson 	struct rte_bbdev_op_data harq_combined_input;
51999a2dd95SBruce Richardson 	/** The HARQ combined LLR stream output buffer - optional */
52099a2dd95SBruce Richardson 	struct rte_bbdev_op_data harq_combined_output;
52199a2dd95SBruce Richardson 
52299a2dd95SBruce Richardson 	/** Flags from rte_bbdev_op_ldpcdec_flag_bitmasks */
52399a2dd95SBruce Richardson 	uint32_t op_flags;
52499a2dd95SBruce Richardson 
52599a2dd95SBruce Richardson 	/** Rate matching redundancy version
52699a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.1]
52799a2dd95SBruce Richardson 	 */
52899a2dd95SBruce Richardson 	uint8_t rv_index;
52999a2dd95SBruce Richardson 	/** The maximum number of iterations to perform in decoding CB in
53099a2dd95SBruce Richardson 	 *  this operation - input
53199a2dd95SBruce Richardson 	 */
53299a2dd95SBruce Richardson 	uint8_t iter_max;
53399a2dd95SBruce Richardson 	/** The number of iterations that were performed in decoding
53499a2dd95SBruce Richardson 	 * CB in this decode operation - output
53599a2dd95SBruce Richardson 	 */
53699a2dd95SBruce Richardson 	uint8_t iter_count;
53799a2dd95SBruce Richardson 	/** 1: LDPC Base graph 1, 2: LDPC Base graph 2.
53899a2dd95SBruce Richardson 	 * [3GPP TS38.212, section 5.2.2]
53999a2dd95SBruce Richardson 	 */
54099a2dd95SBruce Richardson 	uint8_t basegraph;
54199a2dd95SBruce Richardson 	/** Zc, LDPC lifting size.
54299a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.2.2]
54399a2dd95SBruce Richardson 	 */
54499a2dd95SBruce Richardson 	uint16_t z_c;
54599a2dd95SBruce Richardson 	/** Ncb, length of the circular buffer in bits.
54699a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.1]
54799a2dd95SBruce Richardson 	 */
54899a2dd95SBruce Richardson 	uint16_t n_cb;
54999a2dd95SBruce Richardson 	/** Qm, modulation order {1,2,4,6,8}.
55099a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.2]
55199a2dd95SBruce Richardson 	 */
55299a2dd95SBruce Richardson 	uint8_t q_m;
55399a2dd95SBruce Richardson 	/** Number of Filler bits, n_filler = K – K’
55499a2dd95SBruce Richardson 	 *  [3GPP TS38.212 section 5.2.2]
55599a2dd95SBruce Richardson 	 */
55699a2dd95SBruce Richardson 	uint16_t n_filler;
55799a2dd95SBruce Richardson 	/** [0 - TB : 1 - CB] */
55899a2dd95SBruce Richardson 	uint8_t code_block_mode;
55999a2dd95SBruce Richardson 	union {
56099a2dd95SBruce Richardson 		/** Struct which stores Code Block specific parameters */
56199a2dd95SBruce Richardson 		struct rte_bbdev_op_dec_ldpc_cb_params cb_params;
56299a2dd95SBruce Richardson 		/** Struct which stores Transport Block specific parameters */
56399a2dd95SBruce Richardson 		struct rte_bbdev_op_dec_ldpc_tb_params tb_params;
56499a2dd95SBruce Richardson 	};
565*591d38ccSNicolas Chautru 	/** Optional k0 Rate matching starting position, overrides rv_index when non null
566*591d38ccSNicolas Chautru 	 *  [3GPP TS38.212, section 5.4.2.1]
567*591d38ccSNicolas Chautru 	 */
568*591d38ccSNicolas Chautru 	uint16_t k0;
56999a2dd95SBruce Richardson };
570c49c880fSNicolas Chautru /* >8 End of structure rte_bbdev_op_ldpc_dec. */
57199a2dd95SBruce Richardson 
57299a2dd95SBruce Richardson /** Turbo encode code block parameters */
57399a2dd95SBruce Richardson struct rte_bbdev_op_enc_turbo_cb_params {
57499a2dd95SBruce Richardson 	/** The K size of the input CB, in bits [40:6144], as specified in
57599a2dd95SBruce Richardson 	 * 3GPP TS 36.212.
57699a2dd95SBruce Richardson 	 * This size is inclusive of CRC24A, regardless whether it was
57799a2dd95SBruce Richardson 	 * pre-calculated by the application or not.
57899a2dd95SBruce Richardson 	 */
57999a2dd95SBruce Richardson 	uint16_t k;
58099a2dd95SBruce Richardson 	/** The E length of the CB rate matched output, in bits, as in
58199a2dd95SBruce Richardson 	 * 3GPP TS 36.212.
58299a2dd95SBruce Richardson 	 */
58399a2dd95SBruce Richardson 	uint32_t e;
58499a2dd95SBruce Richardson 	/** The Ncb soft buffer size of the CB rate matched output [K:3*Kpi],
58599a2dd95SBruce Richardson 	 * in bits, as specified in 3GPP TS 36.212.
58699a2dd95SBruce Richardson 	 */
58799a2dd95SBruce Richardson 	uint16_t ncb;
58899a2dd95SBruce Richardson };
58999a2dd95SBruce Richardson 
59099a2dd95SBruce Richardson /** Turbo encode transport block parameters */
59199a2dd95SBruce Richardson struct rte_bbdev_op_enc_turbo_tb_params {
59299a2dd95SBruce Richardson 	/** The K- size of the input CB, in bits [40:6144], that is in the
59399a2dd95SBruce Richardson 	 * Turbo operation when r < C-, as in 3GPP TS 36.212.
59499a2dd95SBruce Richardson 	 * This size is inclusive of CRC24B, regardless whether it was
59599a2dd95SBruce Richardson 	 * pre-calculated and appended by the application or not.
59699a2dd95SBruce Richardson 	 */
59799a2dd95SBruce Richardson 	uint16_t k_neg;
59899a2dd95SBruce Richardson 	/** The K+ size of the input CB, in bits [40:6144], that is in the
59999a2dd95SBruce Richardson 	 * Turbo operation when r >= C-, as in 3GPP TS 36.212.
60099a2dd95SBruce Richardson 	 * This size is inclusive of CRC24B, regardless whether it was
60199a2dd95SBruce Richardson 	 * pre-calculated and appended by the application or not.
60299a2dd95SBruce Richardson 	 */
60399a2dd95SBruce Richardson 	uint16_t k_pos;
60499a2dd95SBruce Richardson 	/** The number of CBs that have K- size, [0:63] */
60599a2dd95SBruce Richardson 	uint8_t c_neg;
60699a2dd95SBruce Richardson 	/** The total number of CBs in the TB,
60799a2dd95SBruce Richardson 	 * [1:RTE_BBDEV_TURBO_MAX_CODE_BLOCKS]
60899a2dd95SBruce Richardson 	 */
60999a2dd95SBruce Richardson 	uint8_t c;
61099a2dd95SBruce Richardson 	/** The number of CBs that uses Ea before switching to Eb, [0:63] */
61199a2dd95SBruce Richardson 	uint8_t cab;
61299a2dd95SBruce Richardson 	/** The E size of the CB rate matched output to use in the Turbo
61399a2dd95SBruce Richardson 	 * operation when r < cab
61499a2dd95SBruce Richardson 	 */
61599a2dd95SBruce Richardson 	uint32_t ea;
61699a2dd95SBruce Richardson 	/** The E size of the CB rate matched output to use in the Turbo
61799a2dd95SBruce Richardson 	 * operation when r >= cab
61899a2dd95SBruce Richardson 	 */
61999a2dd95SBruce Richardson 	uint32_t eb;
62099a2dd95SBruce Richardson 	/** The Ncb soft buffer size for the rate matched CB that is used in
62199a2dd95SBruce Richardson 	 * the Turbo operation when r < C-, [K:3*Kpi]
62299a2dd95SBruce Richardson 	 */
62399a2dd95SBruce Richardson 	uint16_t ncb_neg;
62499a2dd95SBruce Richardson 	/** The Ncb soft buffer size for the rate matched CB that is used in
62599a2dd95SBruce Richardson 	 * the Turbo operation when r >= C-, [K:3*Kpi]
62699a2dd95SBruce Richardson 	 */
62799a2dd95SBruce Richardson 	uint16_t ncb_pos;
62899a2dd95SBruce Richardson 	/** The index of the first CB in the inbound mbuf data, default is 0 */
62999a2dd95SBruce Richardson 	uint8_t r;
63099a2dd95SBruce Richardson };
63199a2dd95SBruce Richardson 
63299a2dd95SBruce Richardson /** LDPC encode code block parameters */
63399a2dd95SBruce Richardson struct rte_bbdev_op_enc_ldpc_cb_params {
63499a2dd95SBruce Richardson 	/** E, length after rate matching in bits.
63599a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.1]
63699a2dd95SBruce Richardson 	 */
63799a2dd95SBruce Richardson 	uint32_t e;
63899a2dd95SBruce Richardson };
63999a2dd95SBruce Richardson 
64099a2dd95SBruce Richardson /** LDPC encode transport block parameters */
64199a2dd95SBruce Richardson struct rte_bbdev_op_enc_ldpc_tb_params {
64299a2dd95SBruce Richardson 	/** Ea, length after rate matching in bits, r < cab.
64399a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.1]
64499a2dd95SBruce Richardson 	 */
64599a2dd95SBruce Richardson 	uint32_t ea;
64699a2dd95SBruce Richardson 	/** Eb, length after rate matching in bits, r >= cab.
64799a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.1]
64899a2dd95SBruce Richardson 	 */
64999a2dd95SBruce Richardson 	uint32_t eb;
65099a2dd95SBruce Richardson 	/** The total number of CBs in the TB or partial TB
65199a2dd95SBruce Richardson 	 * [1:RTE_BBDEV_LDPC_MAX_CODE_BLOCKS]
65299a2dd95SBruce Richardson 	 */
65399a2dd95SBruce Richardson 	uint8_t c;
65499a2dd95SBruce Richardson 	/** The index of the first CB in the inbound mbuf data, default is 0 */
65599a2dd95SBruce Richardson 	uint8_t r;
65699a2dd95SBruce Richardson 	/** The number of CBs that use Ea before switching to Eb, [0:63] */
65799a2dd95SBruce Richardson 	uint8_t cab;
65899a2dd95SBruce Richardson };
65999a2dd95SBruce Richardson 
66099a2dd95SBruce Richardson /** Operation structure for Turbo encode.
66199a2dd95SBruce Richardson  * An operation can be performed on one CB at a time "CB-mode".
66299a2dd95SBruce Richardson  * An operation can pbe erformd on one or multiple CBs that logically
66399a2dd95SBruce Richardson  * belong to one TB "TB-mode".
66499a2dd95SBruce Richardson  *
66599a2dd95SBruce Richardson  * In CB-mode, CRC24A/B is an optional operation. K size parameter is not
66699a2dd95SBruce Richardson  * affected by CRC24A/B inclusion, this only affects the inbound mbuf data
66799a2dd95SBruce Richardson  * length. Not all BBDEV PMDs are capable of CRC24A/B calculation. Flags
66899a2dd95SBruce Richardson  * RTE_BBDEV_TURBO_CRC_24A_ATTACH and RTE_BBDEV_TURBO_CRC_24B_ATTACH informs
66999a2dd95SBruce Richardson  * the application with relevant capability. These flags can be set in the
67099a2dd95SBruce Richardson  * op_flags parameter to indicate BBDEV to calculate and append CRC24A to CB
67199a2dd95SBruce Richardson  * before going forward with Turbo encoding.
67299a2dd95SBruce Richardson  *
67399a2dd95SBruce Richardson  * In TB-mode, CRC24A is assumed to be pre-calculated and appended to the
67499a2dd95SBruce Richardson  * inbound TB mbuf data buffer.
67599a2dd95SBruce Richardson  *
67699a2dd95SBruce Richardson  * The output mbuf data structure is expected to be allocated by the
67799a2dd95SBruce Richardson  * application with enough room for the output data.
67899a2dd95SBruce Richardson  */
679c49c880fSNicolas Chautru 
680c49c880fSNicolas Chautru /* Structure rte_bbdev_op_turbo_enc 8< */
68199a2dd95SBruce Richardson struct rte_bbdev_op_turbo_enc {
68299a2dd95SBruce Richardson 	/** The input CB or TB data */
68399a2dd95SBruce Richardson 	struct rte_bbdev_op_data input;
68499a2dd95SBruce Richardson 	/** The rate matched CB or TB output buffer */
68599a2dd95SBruce Richardson 	struct rte_bbdev_op_data output;
68699a2dd95SBruce Richardson 	/** Flags from rte_bbdev_op_te_flag_bitmasks */
68799a2dd95SBruce Richardson 	uint32_t op_flags;
68899a2dd95SBruce Richardson 
68999a2dd95SBruce Richardson 	/** Rv index for rate matching [0:3] */
69099a2dd95SBruce Richardson 	uint8_t rv_index;
69199a2dd95SBruce Richardson 	/** [0 - TB : 1 - CB] */
69299a2dd95SBruce Richardson 	uint8_t code_block_mode;
69399a2dd95SBruce Richardson 	union {
69499a2dd95SBruce Richardson 		/** Struct which stores Code Block specific parameters */
69599a2dd95SBruce Richardson 		struct rte_bbdev_op_enc_turbo_cb_params cb_params;
69699a2dd95SBruce Richardson 		/** Struct which stores Transport Block specific parameters */
69799a2dd95SBruce Richardson 		struct rte_bbdev_op_enc_turbo_tb_params tb_params;
69899a2dd95SBruce Richardson 	};
69999a2dd95SBruce Richardson };
700c49c880fSNicolas Chautru /* >8 End of structure rte_bbdev_op_turbo_enc. */
70199a2dd95SBruce Richardson 
70299a2dd95SBruce Richardson /** Operation structure for LDPC encode.
70399a2dd95SBruce Richardson  * An operation can be performed on one CB at a time "CB-mode".
70499a2dd95SBruce Richardson  * An operation can be performed on one or multiple CBs that logically
70599a2dd95SBruce Richardson  * belong to a TB "TB-mode".
70699a2dd95SBruce Richardson  *
70799a2dd95SBruce Richardson  * The input data is the CB or TB input to the decoder.
70899a2dd95SBruce Richardson  *
70999a2dd95SBruce Richardson  * The output data is the ratematched CB or TB data, or the output after
71099a2dd95SBruce Richardson  * bit-selection if RTE_BBDEV_LDPC_INTERLEAVER_BYPASS is set.
71199a2dd95SBruce Richardson  *
71299a2dd95SBruce Richardson  * The output mbuf data structure is expected to be allocated by the
71399a2dd95SBruce Richardson  * application with enough room for the output data.
71499a2dd95SBruce Richardson  */
715c49c880fSNicolas Chautru 
716c49c880fSNicolas Chautru /* Structure rte_bbdev_op_ldpc_enc 8< */
71799a2dd95SBruce Richardson struct rte_bbdev_op_ldpc_enc {
71899a2dd95SBruce Richardson 	/** The input TB or CB data */
71999a2dd95SBruce Richardson 	struct rte_bbdev_op_data input;
72099a2dd95SBruce Richardson 	/** The rate matched TB or CB output buffer */
72199a2dd95SBruce Richardson 	struct rte_bbdev_op_data output;
72299a2dd95SBruce Richardson 
72399a2dd95SBruce Richardson 	/** Flags from rte_bbdev_op_ldpcenc_flag_bitmasks */
72499a2dd95SBruce Richardson 	uint32_t op_flags;
72599a2dd95SBruce Richardson 
72699a2dd95SBruce Richardson 	/** Rate matching redundancy version */
72799a2dd95SBruce Richardson 	uint8_t rv_index;
72899a2dd95SBruce Richardson 	/** 1: LDPC Base graph 1, 2: LDPC Base graph 2.
72999a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.2.2]
73099a2dd95SBruce Richardson 	 */
73199a2dd95SBruce Richardson 	uint8_t basegraph;
73299a2dd95SBruce Richardson 	/** Zc, LDPC lifting size.
73399a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.2.2]
73499a2dd95SBruce Richardson 	 */
73599a2dd95SBruce Richardson 	uint16_t z_c;
73699a2dd95SBruce Richardson 	/** Ncb, length of the circular buffer in bits.
73799a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.1]
73899a2dd95SBruce Richardson 	 */
73999a2dd95SBruce Richardson 	uint16_t n_cb;
74099a2dd95SBruce Richardson 	/** Qm, modulation order {2,4,6,8,10}.
74199a2dd95SBruce Richardson 	 *  [3GPP TS38.212, section 5.4.2.2]
74299a2dd95SBruce Richardson 	 */
74399a2dd95SBruce Richardson 	uint8_t q_m;
74499a2dd95SBruce Richardson 	/** Number of Filler bits, n_filler = K – K’
74599a2dd95SBruce Richardson 	 *  [3GPP TS38.212 section 5.2.2]
74699a2dd95SBruce Richardson 	 */
74799a2dd95SBruce Richardson 	uint16_t n_filler;
74899a2dd95SBruce Richardson 	/** [0 - TB : 1 - CB] */
74999a2dd95SBruce Richardson 	uint8_t code_block_mode;
75099a2dd95SBruce Richardson 	union {
75199a2dd95SBruce Richardson 		/** Struct which stores Code Block specific parameters */
75299a2dd95SBruce Richardson 		struct rte_bbdev_op_enc_ldpc_cb_params cb_params;
75399a2dd95SBruce Richardson 		/** Struct which stores Transport Block specific parameters */
75499a2dd95SBruce Richardson 		struct rte_bbdev_op_enc_ldpc_tb_params tb_params;
75599a2dd95SBruce Richardson 	};
75699a2dd95SBruce Richardson };
757c49c880fSNicolas Chautru /* >8 End of structure rte_bbdev_op_ldpc_enc. */
75899a2dd95SBruce Richardson 
7599d393325SNicolas Chautru /** Operation structure for FFT processing.
7609d393325SNicolas Chautru  *
7619d393325SNicolas Chautru  * The operation processes the data for multiple antennas in a single call
7629d393325SNicolas Chautru  * (i.e. for all the REs belonging to a given SRS sequence for instance).
7639d393325SNicolas Chautru  *
7649d393325SNicolas Chautru  * The output mbuf data structure is expected to be allocated by the
7659d393325SNicolas Chautru  * application with enough room for the output data.
7669d393325SNicolas Chautru  */
767c49c880fSNicolas Chautru 
768c49c880fSNicolas Chautru /* Structure rte_bbdev_op_fft 8< */
7699d393325SNicolas Chautru struct rte_bbdev_op_fft {
7709d393325SNicolas Chautru 	/** Input data starting from first antenna. */
7719d393325SNicolas Chautru 	struct rte_bbdev_op_data base_input;
7729d393325SNicolas Chautru 	/** Output data starting from first antenna and first cyclic shift. */
7739d393325SNicolas Chautru 	struct rte_bbdev_op_data base_output;
7740aa8b208SNicolas Chautru 	/** Optional frequency window input data. */
7750aa8b208SNicolas Chautru 	struct rte_bbdev_op_data dewindowing_input;
7769d393325SNicolas Chautru 	/** Optional power measurement output data. */
7779d393325SNicolas Chautru 	struct rte_bbdev_op_data power_meas_output;
7789d393325SNicolas Chautru 	/** Flags from rte_bbdev_op_fft_flag_bitmasks. */
7799d393325SNicolas Chautru 	uint32_t op_flags;
7809d393325SNicolas Chautru 	/** Input sequence size in 32-bits points. */
7819d393325SNicolas Chautru 	uint16_t input_sequence_size;
7829d393325SNicolas Chautru 	/** Padding at the start of the sequence. */
7839d393325SNicolas Chautru 	uint16_t input_leading_padding;
7849d393325SNicolas Chautru 	/** Output sequence size in 32-bits points. */
7859d393325SNicolas Chautru 	uint16_t output_sequence_size;
7869d393325SNicolas Chautru 	/** Depadding at the start of the DFT output. */
7879d393325SNicolas Chautru 	uint16_t output_leading_depadding;
7889d393325SNicolas Chautru 	/** Window index being used for each cyclic shift output. */
7899d393325SNicolas Chautru 	uint8_t window_index[RTE_BBDEV_MAX_CS_2];
7909d393325SNicolas Chautru 	/** Bitmap of the cyclic shift output requested. */
7919d393325SNicolas Chautru 	uint16_t cs_bitmap;
7929d393325SNicolas Chautru 	/** Number of antennas as a log2 – 8 to 128. */
7939d393325SNicolas Chautru 	uint8_t num_antennas_log2;
7949d393325SNicolas Chautru 	/** iDFT size as a log2 - 32 to 2048. */
7959d393325SNicolas Chautru 	uint8_t idft_log2;
7969d393325SNicolas Chautru 	/** DFT size as a log2 - 8 to 2048. */
7979d393325SNicolas Chautru 	uint8_t dft_log2;
7989d393325SNicolas Chautru 	/** Adjustment of position of the cyclic shifts - -31 to 31. */
7999d393325SNicolas Chautru 	int8_t cs_time_adjustment;
8009d393325SNicolas Chautru 	/** iDFT shift down. */
8019d393325SNicolas Chautru 	int8_t idft_shift;
8029d393325SNicolas Chautru 	/** DFT shift down. */
8039d393325SNicolas Chautru 	int8_t dft_shift;
8049d393325SNicolas Chautru 	/** NCS reciprocal factor. */
8059d393325SNicolas Chautru 	uint16_t ncs_reciprocal;
8069d393325SNicolas Chautru 	/** Power measurement out shift down. */
8079d393325SNicolas Chautru 	uint16_t power_shift;
8089d393325SNicolas Chautru 	/** Adjust the FP6 exponent for INT<->FP16 conversion. */
8099d393325SNicolas Chautru 	uint16_t fp16_exp_adjust;
8100aa8b208SNicolas Chautru 	/** Frequency resampling : 0: Transparent Mode1: 4/3 Resample2: 2/3 Resample. */
8110aa8b208SNicolas Chautru 	int8_t freq_resample_mode;
8120aa8b208SNicolas Chautru 	/** Output depadded size prior to frequency resampling. */
8130aa8b208SNicolas Chautru 	uint16_t output_depadded_size;
8140aa8b208SNicolas Chautru 	/** Time error correction initial phase. */
8150aa8b208SNicolas Chautru 	uint16_t cs_theta_0[RTE_BBDEV_MAX_CS];
8160aa8b208SNicolas Chautru 	/** Time error correction phase increment. */
8170aa8b208SNicolas Chautru 	uint32_t cs_theta_d[RTE_BBDEV_MAX_CS];
8180aa8b208SNicolas Chautru 	/* Time offset per CS of time domain samples. */
8190aa8b208SNicolas Chautru 	int8_t time_offset[RTE_BBDEV_MAX_CS];
8209d393325SNicolas Chautru };
821c49c880fSNicolas Chautru /* >8 End of structure rte_bbdev_op_fft. */
8229d393325SNicolas Chautru 
823089148fcSNicolas Chautru /** Operation structure for MLDTS processing.
824089148fcSNicolas Chautru  *
825089148fcSNicolas Chautru  * The output mbuf data structure is expected to be allocated by the
826089148fcSNicolas Chautru  * application with enough room for the output data.
827089148fcSNicolas Chautru  */
828089148fcSNicolas Chautru 
829089148fcSNicolas Chautru /* Structure rte_bbdev_op_mldts 8< */
830089148fcSNicolas Chautru struct rte_bbdev_op_mldts {
831089148fcSNicolas Chautru 	/** Input data QHy from QR decomposition. */
832089148fcSNicolas Chautru 	struct rte_bbdev_op_data qhy_input;
833089148fcSNicolas Chautru 	/** Input data R from QR decomposition. */
834089148fcSNicolas Chautru 	struct rte_bbdev_op_data r_input;
835089148fcSNicolas Chautru 	/** Output data post MLD-TS. */
836089148fcSNicolas Chautru 	struct rte_bbdev_op_data output;
837089148fcSNicolas Chautru 	/** Flags from *rte_bbdev_op_MLDTS_flag_bitmasks*. */
838089148fcSNicolas Chautru 	uint32_t op_flags;
839089148fcSNicolas Chautru 	/** Number of RBs. */
840089148fcSNicolas Chautru 	uint16_t num_rbs;
841089148fcSNicolas Chautru 	/** Number of layers 2->4. */
842089148fcSNicolas Chautru 	uint16_t num_layers;
843089148fcSNicolas Chautru 	/** Modulation order (2->8 QPSK to 256QAM). */
844089148fcSNicolas Chautru 	uint8_t q_m[RTE_BBDEV_MAX_MLD_LAYERS];
845089148fcSNicolas Chautru 	/** Row repetition for the same R matrix - subcarriers. */
846089148fcSNicolas Chautru 	uint8_t r_rep;
847089148fcSNicolas Chautru 	/** Column repetition for the same R matrix - symbols. */
848089148fcSNicolas Chautru 	uint8_t c_rep;
849089148fcSNicolas Chautru };
850089148fcSNicolas Chautru /* >8 End of structure rte_bbdev_op_mldts. */
851089148fcSNicolas Chautru 
85299a2dd95SBruce Richardson /** List of the capabilities for the Turbo Decoder */
85399a2dd95SBruce Richardson struct rte_bbdev_op_cap_turbo_dec {
85499a2dd95SBruce Richardson 	/** Flags from rte_bbdev_op_td_flag_bitmasks */
85599a2dd95SBruce Richardson 	uint32_t capability_flags;
85699a2dd95SBruce Richardson 	/** Maximal LLR absolute value. Acceptable LLR values lie in range
85799a2dd95SBruce Richardson 	 * [-max_llr_modulus, max_llr_modulus].
85899a2dd95SBruce Richardson 	 */
85999a2dd95SBruce Richardson 	int8_t max_llr_modulus;
86099a2dd95SBruce Richardson 	/** Num input code block buffers */
86199a2dd95SBruce Richardson 	uint8_t num_buffers_src;  /**< Num input code block buffers */
86299a2dd95SBruce Richardson 	/** Num hard output code block buffers */
86399a2dd95SBruce Richardson 	uint8_t num_buffers_hard_out;
86499a2dd95SBruce Richardson 	/** Num soft output code block buffers if supported by the driver */
86599a2dd95SBruce Richardson 	uint8_t num_buffers_soft_out;
86699a2dd95SBruce Richardson };
86799a2dd95SBruce Richardson 
86899a2dd95SBruce Richardson /** List of the capabilities for the Turbo Encoder */
86999a2dd95SBruce Richardson struct rte_bbdev_op_cap_turbo_enc {
87099a2dd95SBruce Richardson 	/** Flags from rte_bbdev_op_te_flag_bitmasks */
87199a2dd95SBruce Richardson 	uint32_t capability_flags;
87299a2dd95SBruce Richardson 	/** Num input code block buffers */
87399a2dd95SBruce Richardson 	uint8_t num_buffers_src;
87499a2dd95SBruce Richardson 	/** Num output code block buffers */
87599a2dd95SBruce Richardson 	uint8_t num_buffers_dst;
87699a2dd95SBruce Richardson };
87799a2dd95SBruce Richardson 
87899a2dd95SBruce Richardson /** List of the capabilities for the LDPC Decoder */
87999a2dd95SBruce Richardson struct rte_bbdev_op_cap_ldpc_dec {
88099a2dd95SBruce Richardson 	/** Flags from rte_bbdev_op_ldpcdec_flag_bitmasks */
88199a2dd95SBruce Richardson 	uint32_t capability_flags;
88299a2dd95SBruce Richardson 	/** LLR size in bits. LLR is a two’s complement number. */
88399a2dd95SBruce Richardson 	int8_t llr_size;
88499a2dd95SBruce Richardson 	/** LLR numbers of decimals bit for arithmetic representation */
88599a2dd95SBruce Richardson 	int8_t llr_decimals;
88699a2dd95SBruce Richardson 	/** Num input code block buffers */
88799a2dd95SBruce Richardson 	uint16_t num_buffers_src;
88899a2dd95SBruce Richardson 	/** Num hard output code block buffers */
88999a2dd95SBruce Richardson 	uint16_t num_buffers_hard_out;
89099a2dd95SBruce Richardson 	/** Num soft output code block buffers if supported by the driver */
89199a2dd95SBruce Richardson 	uint16_t num_buffers_soft_out;
89299a2dd95SBruce Richardson };
89399a2dd95SBruce Richardson 
89499a2dd95SBruce Richardson /** List of the capabilities for the LDPC Encoder */
89599a2dd95SBruce Richardson struct rte_bbdev_op_cap_ldpc_enc {
89699a2dd95SBruce Richardson 	/** Flags from rte_bbdev_op_ldpcenc_flag_bitmasks */
89799a2dd95SBruce Richardson 	uint32_t capability_flags;
89899a2dd95SBruce Richardson 	/** Num input code block buffers */
89999a2dd95SBruce Richardson 	uint16_t num_buffers_src;
90099a2dd95SBruce Richardson 	/** Num output code block buffers */
90199a2dd95SBruce Richardson 	uint16_t num_buffers_dst;
90299a2dd95SBruce Richardson };
90399a2dd95SBruce Richardson 
9049d393325SNicolas Chautru /** List of the capabilities for the FFT. */
9059d393325SNicolas Chautru struct rte_bbdev_op_cap_fft {
9069d393325SNicolas Chautru 	/** Flags from *rte_bbdev_op_fft_flag_bitmasks*. */
9079d393325SNicolas Chautru 	uint32_t capability_flags;
908089148fcSNicolas Chautru 	/** Num input code block buffers. */
909089148fcSNicolas Chautru 	uint16_t num_buffers_src;
910089148fcSNicolas Chautru 	/** Num output code block buffers. */
911089148fcSNicolas Chautru 	uint16_t num_buffers_dst;
912d921348cSNicolas Chautru 	/** Number of FFT windows supported. */
913d921348cSNicolas Chautru 	uint16_t fft_windows_num;
914089148fcSNicolas Chautru };
915089148fcSNicolas Chautru 
916089148fcSNicolas Chautru /** List of the capabilities for the MLD */
917089148fcSNicolas Chautru struct rte_bbdev_op_cap_mld {
918089148fcSNicolas Chautru 	/** Flags from rte_bbdev_op_mldts_flag_bitmasks */
919089148fcSNicolas Chautru 	uint32_t capability_flags;
9209d393325SNicolas Chautru 	/** Number of input code block buffers. */
9219d393325SNicolas Chautru 	uint16_t num_buffers_src;
9229d393325SNicolas Chautru 	/** Number of output code block buffers. */
9239d393325SNicolas Chautru 	uint16_t num_buffers_dst;
9249d393325SNicolas Chautru };
9259d393325SNicolas Chautru 
926e70212ccSNicolas Chautru /** Different operation types supported by the device.
927e70212ccSNicolas Chautru  *  The related macro RTE_BBDEV_OP_TYPE_SIZE_MAX can be used as an absolute maximum for
928e70212ccSNicolas Chautru  *  notably sizing array while allowing for future enumeration insertion.
929e70212ccSNicolas Chautru  */
93099a2dd95SBruce Richardson enum rte_bbdev_op_type {
93199a2dd95SBruce Richardson 	RTE_BBDEV_OP_NONE,  /**< Dummy operation that does nothing */
93299a2dd95SBruce Richardson 	RTE_BBDEV_OP_TURBO_DEC,  /**< Turbo decode */
93399a2dd95SBruce Richardson 	RTE_BBDEV_OP_TURBO_ENC,  /**< Turbo encode */
93499a2dd95SBruce Richardson 	RTE_BBDEV_OP_LDPC_DEC,  /**< LDPC decode */
93599a2dd95SBruce Richardson 	RTE_BBDEV_OP_LDPC_ENC,  /**< LDPC encode */
9369d393325SNicolas Chautru 	RTE_BBDEV_OP_FFT,  /**< FFT */
937089148fcSNicolas Chautru 	RTE_BBDEV_OP_MLDTS,  /**< MLD-TS */
938e70212ccSNicolas Chautru 	/* Note: RTE_BBDEV_OP_TYPE_SIZE_MAX must be larger or equal to maximum enum value */
93999a2dd95SBruce Richardson };
94099a2dd95SBruce Richardson 
94199a2dd95SBruce Richardson /** Bit indexes of possible errors reported through status field */
94299a2dd95SBruce Richardson enum {
94399a2dd95SBruce Richardson 	RTE_BBDEV_DRV_ERROR,
94499a2dd95SBruce Richardson 	RTE_BBDEV_DATA_ERROR,
94599a2dd95SBruce Richardson 	RTE_BBDEV_CRC_ERROR,
946089148fcSNicolas Chautru 	RTE_BBDEV_SYNDROME_ERROR,
947089148fcSNicolas Chautru 	RTE_BBDEV_ENGINE_ERROR
94899a2dd95SBruce Richardson };
94999a2dd95SBruce Richardson 
95099a2dd95SBruce Richardson /** Structure specifying a single encode operation */
95199a2dd95SBruce Richardson struct rte_bbdev_enc_op {
95299a2dd95SBruce Richardson 	/** Status of operation that was performed */
95399a2dd95SBruce Richardson 	int status;
95499a2dd95SBruce Richardson 	/** Mempool which op instance is in */
95599a2dd95SBruce Richardson 	struct rte_mempool *mempool;
95699a2dd95SBruce Richardson 	/** Opaque pointer for user data */
95799a2dd95SBruce Richardson 	void *opaque_data;
95899a2dd95SBruce Richardson 	union {
95999a2dd95SBruce Richardson 		/** Contains turbo decoder specific parameters */
96099a2dd95SBruce Richardson 		struct rte_bbdev_op_turbo_enc turbo_enc;
96199a2dd95SBruce Richardson 		/** Contains LDPC decoder specific parameters */
96299a2dd95SBruce Richardson 		struct rte_bbdev_op_ldpc_enc ldpc_enc;
96399a2dd95SBruce Richardson 	};
96499a2dd95SBruce Richardson };
96599a2dd95SBruce Richardson 
96699a2dd95SBruce Richardson /** Structure specifying a single decode operation */
96799a2dd95SBruce Richardson struct rte_bbdev_dec_op {
96899a2dd95SBruce Richardson 	/** Status of operation that was performed */
96999a2dd95SBruce Richardson 	int status;
97099a2dd95SBruce Richardson 	/** Mempool which op instance is in */
97199a2dd95SBruce Richardson 	struct rte_mempool *mempool;
97299a2dd95SBruce Richardson 	/** Opaque pointer for user data */
97399a2dd95SBruce Richardson 	void *opaque_data;
97499a2dd95SBruce Richardson 	union {
97599a2dd95SBruce Richardson 		/** Contains turbo decoder specific parameters */
97699a2dd95SBruce Richardson 		struct rte_bbdev_op_turbo_dec turbo_dec;
97799a2dd95SBruce Richardson 		/** Contains LDPC decoder specific parameters */
97899a2dd95SBruce Richardson 		struct rte_bbdev_op_ldpc_dec ldpc_dec;
97999a2dd95SBruce Richardson 	};
98099a2dd95SBruce Richardson };
98199a2dd95SBruce Richardson 
9829d393325SNicolas Chautru /** Structure specifying a single FFT operation. */
9839d393325SNicolas Chautru struct rte_bbdev_fft_op {
9849d393325SNicolas Chautru 	/** Status of operation performed. */
9859d393325SNicolas Chautru 	int status;
9869d393325SNicolas Chautru 	/** Mempool used for op instance. */
9879d393325SNicolas Chautru 	struct rte_mempool *mempool;
9889d393325SNicolas Chautru 	/** Opaque pointer for user data. */
9899d393325SNicolas Chautru 	void *opaque_data;
9909d393325SNicolas Chautru 	/** Contains turbo decoder specific parameters. */
9919d393325SNicolas Chautru 	struct rte_bbdev_op_fft fft;
9929d393325SNicolas Chautru };
9939d393325SNicolas Chautru 
994089148fcSNicolas Chautru /** Structure specifying a single mldts operation */
995089148fcSNicolas Chautru struct rte_bbdev_mldts_op {
996089148fcSNicolas Chautru 	/** Status of operation that was performed. */
997089148fcSNicolas Chautru 	int status;
998089148fcSNicolas Chautru 	/** Mempool which op instance is in. */
999089148fcSNicolas Chautru 	struct rte_mempool *mempool;
1000089148fcSNicolas Chautru 	/** Opaque pointer for user data. */
1001089148fcSNicolas Chautru 	void *opaque_data;
1002089148fcSNicolas Chautru 	/** Contains turbo decoder specific parameters. */
1003089148fcSNicolas Chautru 	struct rte_bbdev_op_mldts mldts;
1004089148fcSNicolas Chautru };
1005089148fcSNicolas Chautru 
100699a2dd95SBruce Richardson /** Operation capabilities supported by a device */
100799a2dd95SBruce Richardson struct rte_bbdev_op_cap {
100899a2dd95SBruce Richardson 	enum rte_bbdev_op_type type;  /**< Type of operation */
100999a2dd95SBruce Richardson 	union {
101099a2dd95SBruce Richardson 		struct rte_bbdev_op_cap_turbo_dec turbo_dec;
101199a2dd95SBruce Richardson 		struct rte_bbdev_op_cap_turbo_enc turbo_enc;
101299a2dd95SBruce Richardson 		struct rte_bbdev_op_cap_ldpc_dec ldpc_dec;
101399a2dd95SBruce Richardson 		struct rte_bbdev_op_cap_ldpc_enc ldpc_enc;
10149d393325SNicolas Chautru 		struct rte_bbdev_op_cap_fft fft;
1015089148fcSNicolas Chautru 		struct rte_bbdev_op_cap_mld mld;
101699a2dd95SBruce Richardson 	} cap;  /**< Operation-type specific capabilities */
101799a2dd95SBruce Richardson };
101899a2dd95SBruce Richardson 
101999a2dd95SBruce Richardson /** @internal Private data structure stored with operation pool. */
102099a2dd95SBruce Richardson struct rte_bbdev_op_pool_private {
102199a2dd95SBruce Richardson 	enum rte_bbdev_op_type type;  /**< Type of operations in a pool */
102299a2dd95SBruce Richardson };
102399a2dd95SBruce Richardson 
102499a2dd95SBruce Richardson /**
102599a2dd95SBruce Richardson  * Converts queue operation type from enum to string
102699a2dd95SBruce Richardson  *
102799a2dd95SBruce Richardson  * @param op_type
102899a2dd95SBruce Richardson  *   Operation type as enum
102999a2dd95SBruce Richardson  *
103099a2dd95SBruce Richardson  * @returns
103199a2dd95SBruce Richardson  *   Operation type as string or NULL if op_type is invalid
103299a2dd95SBruce Richardson  */
103399a2dd95SBruce Richardson const char*
103499a2dd95SBruce Richardson rte_bbdev_op_type_str(enum rte_bbdev_op_type op_type);
103599a2dd95SBruce Richardson 
103699a2dd95SBruce Richardson /**
103799a2dd95SBruce Richardson  * Creates a bbdev operation mempool
103899a2dd95SBruce Richardson  *
103999a2dd95SBruce Richardson  * @param name
104099a2dd95SBruce Richardson  *   Pool name.
104199a2dd95SBruce Richardson  * @param type
104299a2dd95SBruce Richardson  *   Operation type, use RTE_BBDEV_OP_NONE for a pool which supports all
104399a2dd95SBruce Richardson  *   operation types.
104499a2dd95SBruce Richardson  * @param num_elements
104599a2dd95SBruce Richardson  *   Number of elements in the pool.
104699a2dd95SBruce Richardson  * @param cache_size
104799a2dd95SBruce Richardson  *   Number of elements to cache on an lcore, see rte_mempool_create() for
104899a2dd95SBruce Richardson  *   further details about cache size.
104999a2dd95SBruce Richardson  * @param socket_id
105099a2dd95SBruce Richardson  *   Socket to allocate memory on.
105199a2dd95SBruce Richardson  *
105299a2dd95SBruce Richardson  * @return
105399a2dd95SBruce Richardson  *   - Pointer to a mempool on success,
105499a2dd95SBruce Richardson  *   - NULL pointer on failure.
105599a2dd95SBruce Richardson  */
105699a2dd95SBruce Richardson struct rte_mempool *
105799a2dd95SBruce Richardson rte_bbdev_op_pool_create(const char *name, enum rte_bbdev_op_type type,
105899a2dd95SBruce Richardson 		unsigned int num_elements, unsigned int cache_size,
105999a2dd95SBruce Richardson 		int socket_id);
106099a2dd95SBruce Richardson 
106199a2dd95SBruce Richardson /**
106299a2dd95SBruce Richardson  * Bulk allocate encode operations from a mempool with parameter defaults reset.
106399a2dd95SBruce Richardson  *
106499a2dd95SBruce Richardson  * @param mempool
106599a2dd95SBruce Richardson  *   Operation mempool, created by rte_bbdev_op_pool_create().
106699a2dd95SBruce Richardson  * @param ops
106799a2dd95SBruce Richardson  *   Output array to place allocated operations
106899a2dd95SBruce Richardson  * @param num_ops
106999a2dd95SBruce Richardson  *   Number of operations to allocate
107099a2dd95SBruce Richardson  *
107199a2dd95SBruce Richardson  * @returns
107299a2dd95SBruce Richardson  *   - 0 on success
107399a2dd95SBruce Richardson  *   - EINVAL if invalid mempool is provided
107499a2dd95SBruce Richardson  */
107599a2dd95SBruce Richardson static inline int
107699a2dd95SBruce Richardson rte_bbdev_enc_op_alloc_bulk(struct rte_mempool *mempool,
10773541de4fSNicolas Chautru 		struct rte_bbdev_enc_op **ops, unsigned int num_ops)
107899a2dd95SBruce Richardson {
107999a2dd95SBruce Richardson 	struct rte_bbdev_op_pool_private *priv;
108099a2dd95SBruce Richardson 
108199a2dd95SBruce Richardson 	/* Check type */
108299a2dd95SBruce Richardson 	priv = (struct rte_bbdev_op_pool_private *)
108399a2dd95SBruce Richardson 			rte_mempool_get_priv(mempool);
108499a2dd95SBruce Richardson 	if (unlikely((priv->type != RTE_BBDEV_OP_TURBO_ENC) &&
108599a2dd95SBruce Richardson 					(priv->type != RTE_BBDEV_OP_LDPC_ENC)))
108699a2dd95SBruce Richardson 		return -EINVAL;
108799a2dd95SBruce Richardson 
108899a2dd95SBruce Richardson 	/* Get elements */
1089b3af2227SNicolas Chautru 	return rte_mempool_get_bulk(mempool, (void **)ops, num_ops);
109099a2dd95SBruce Richardson }
109199a2dd95SBruce Richardson 
109299a2dd95SBruce Richardson /**
109399a2dd95SBruce Richardson  * Bulk allocate decode operations from a mempool with parameter defaults reset.
109499a2dd95SBruce Richardson  *
109599a2dd95SBruce Richardson  * @param mempool
109699a2dd95SBruce Richardson  *   Operation mempool, created by rte_bbdev_op_pool_create().
109799a2dd95SBruce Richardson  * @param ops
109899a2dd95SBruce Richardson  *   Output array to place allocated operations
109999a2dd95SBruce Richardson  * @param num_ops
110099a2dd95SBruce Richardson  *   Number of operations to allocate
110199a2dd95SBruce Richardson  *
110299a2dd95SBruce Richardson  * @returns
110399a2dd95SBruce Richardson  *   - 0 on success
110499a2dd95SBruce Richardson  *   - EINVAL if invalid mempool is provided
110599a2dd95SBruce Richardson  */
110699a2dd95SBruce Richardson static inline int
110799a2dd95SBruce Richardson rte_bbdev_dec_op_alloc_bulk(struct rte_mempool *mempool,
11083541de4fSNicolas Chautru 		struct rte_bbdev_dec_op **ops, unsigned int num_ops)
110999a2dd95SBruce Richardson {
111099a2dd95SBruce Richardson 	struct rte_bbdev_op_pool_private *priv;
111199a2dd95SBruce Richardson 
111299a2dd95SBruce Richardson 	/* Check type */
111399a2dd95SBruce Richardson 	priv = (struct rte_bbdev_op_pool_private *)
111499a2dd95SBruce Richardson 			rte_mempool_get_priv(mempool);
111599a2dd95SBruce Richardson 	if (unlikely((priv->type != RTE_BBDEV_OP_TURBO_DEC) &&
111699a2dd95SBruce Richardson 					(priv->type != RTE_BBDEV_OP_LDPC_DEC)))
111799a2dd95SBruce Richardson 		return -EINVAL;
111899a2dd95SBruce Richardson 
111999a2dd95SBruce Richardson 	/* Get elements */
1120b3af2227SNicolas Chautru 	return rte_mempool_get_bulk(mempool, (void **)ops, num_ops);
112199a2dd95SBruce Richardson }
112299a2dd95SBruce Richardson 
112399a2dd95SBruce Richardson /**
11249d393325SNicolas Chautru  * Bulk allocate FFT operations from a mempool with default parameters.
11259d393325SNicolas Chautru  *
11269d393325SNicolas Chautru  * @param mempool
11279d393325SNicolas Chautru  *   Operation mempool, created by *rte_bbdev_op_pool_create*.
11289d393325SNicolas Chautru  * @param ops
11299d393325SNicolas Chautru  *   Output array to place allocated operations.
11309d393325SNicolas Chautru  * @param num_ops
11319d393325SNicolas Chautru  *   Number of operations to allocate.
11329d393325SNicolas Chautru  *
11339d393325SNicolas Chautru  * @returns
11349d393325SNicolas Chautru  *   - 0 on success.
11359d393325SNicolas Chautru  *   - EINVAL if invalid mempool is provided.
11369d393325SNicolas Chautru  */
11379d393325SNicolas Chautru static inline int
11389d393325SNicolas Chautru rte_bbdev_fft_op_alloc_bulk(struct rte_mempool *mempool,
11393541de4fSNicolas Chautru 		struct rte_bbdev_fft_op **ops, unsigned int num_ops)
11409d393325SNicolas Chautru {
11419d393325SNicolas Chautru 	struct rte_bbdev_op_pool_private *priv;
11429d393325SNicolas Chautru 
11439d393325SNicolas Chautru 	/* Check type */
11449d393325SNicolas Chautru 	priv = (struct rte_bbdev_op_pool_private *)rte_mempool_get_priv(mempool);
11459d393325SNicolas Chautru 	if (unlikely(priv->type != RTE_BBDEV_OP_FFT))
11469d393325SNicolas Chautru 		return -EINVAL;
11479d393325SNicolas Chautru 
11489d393325SNicolas Chautru 	/* Get elements */
1149b3af2227SNicolas Chautru 	return rte_mempool_get_bulk(mempool, (void **)ops, num_ops);
11509d393325SNicolas Chautru }
11519d393325SNicolas Chautru 
11529d393325SNicolas Chautru /**
1153089148fcSNicolas Chautru  * Bulk allocate MLD operations from a mempool with parameter defaults reset.
1154089148fcSNicolas Chautru  *
1155089148fcSNicolas Chautru  * @param mempool
1156089148fcSNicolas Chautru  *   Operation mempool, created by *rte_bbdev_op_pool_create*.
1157089148fcSNicolas Chautru  * @param ops
1158089148fcSNicolas Chautru  *   Output array to place allocated operations.
1159089148fcSNicolas Chautru  * @param num_ops
1160089148fcSNicolas Chautru  *   Number of operations to allocate.
1161089148fcSNicolas Chautru  *
1162089148fcSNicolas Chautru  * @returns
1163089148fcSNicolas Chautru  *   - 0 on success.
1164089148fcSNicolas Chautru  *   - EINVAL if invalid mempool is provided.
1165089148fcSNicolas Chautru  */
1166089148fcSNicolas Chautru static inline int
1167089148fcSNicolas Chautru rte_bbdev_mldts_op_alloc_bulk(struct rte_mempool *mempool,
1168089148fcSNicolas Chautru 		struct rte_bbdev_mldts_op **ops, uint16_t num_ops)
1169089148fcSNicolas Chautru {
1170089148fcSNicolas Chautru 	struct rte_bbdev_op_pool_private *priv;
1171089148fcSNicolas Chautru 
1172089148fcSNicolas Chautru 	/* Check type */
1173089148fcSNicolas Chautru 	priv = (struct rte_bbdev_op_pool_private *)rte_mempool_get_priv(mempool);
1174089148fcSNicolas Chautru 	if (unlikely(priv->type != RTE_BBDEV_OP_MLDTS))
1175089148fcSNicolas Chautru 		return -EINVAL;
1176089148fcSNicolas Chautru 
1177089148fcSNicolas Chautru 	/* Get elements */
1178089148fcSNicolas Chautru 	return rte_mempool_get_bulk(mempool, (void **)ops, num_ops);
1179089148fcSNicolas Chautru }
1180089148fcSNicolas Chautru 
1181089148fcSNicolas Chautru /**
118299a2dd95SBruce Richardson  * Free decode operation structures that were allocated by
118399a2dd95SBruce Richardson  * rte_bbdev_dec_op_alloc_bulk().
118499a2dd95SBruce Richardson  * All structures must belong to the same mempool.
118599a2dd95SBruce Richardson  *
118699a2dd95SBruce Richardson  * @param ops
118799a2dd95SBruce Richardson  *   Operation structures
118899a2dd95SBruce Richardson  * @param num_ops
118999a2dd95SBruce Richardson  *   Number of structures
119099a2dd95SBruce Richardson  */
119199a2dd95SBruce Richardson static inline void
119299a2dd95SBruce Richardson rte_bbdev_dec_op_free_bulk(struct rte_bbdev_dec_op **ops, unsigned int num_ops)
119399a2dd95SBruce Richardson {
119499a2dd95SBruce Richardson 	if (num_ops > 0)
119599a2dd95SBruce Richardson 		rte_mempool_put_bulk(ops[0]->mempool, (void **)ops, num_ops);
119699a2dd95SBruce Richardson }
119799a2dd95SBruce Richardson 
119899a2dd95SBruce Richardson /**
119999a2dd95SBruce Richardson  * Free encode operation structures that were allocated by
120099a2dd95SBruce Richardson  * rte_bbdev_enc_op_alloc_bulk().
120199a2dd95SBruce Richardson  * All structures must belong to the same mempool.
120299a2dd95SBruce Richardson  *
120399a2dd95SBruce Richardson  * @param ops
120499a2dd95SBruce Richardson  *   Operation structures
120599a2dd95SBruce Richardson  * @param num_ops
120699a2dd95SBruce Richardson  *   Number of structures
120799a2dd95SBruce Richardson  */
120899a2dd95SBruce Richardson static inline void
120999a2dd95SBruce Richardson rte_bbdev_enc_op_free_bulk(struct rte_bbdev_enc_op **ops, unsigned int num_ops)
121099a2dd95SBruce Richardson {
121199a2dd95SBruce Richardson 	if (num_ops > 0)
121299a2dd95SBruce Richardson 		rte_mempool_put_bulk(ops[0]->mempool, (void **)ops, num_ops);
121399a2dd95SBruce Richardson }
121499a2dd95SBruce Richardson 
12159d393325SNicolas Chautru /**
12169d393325SNicolas Chautru  * Free encode operation structures that were allocated by
12179d393325SNicolas Chautru  * *rte_bbdev_fft_op_alloc_bulk*.
12189d393325SNicolas Chautru  * All structures must belong to the same mempool.
12199d393325SNicolas Chautru  *
12209d393325SNicolas Chautru  * @param ops
12219d393325SNicolas Chautru  *   Operation structures.
12229d393325SNicolas Chautru  * @param num_ops
12239d393325SNicolas Chautru  *   Number of structures.
12249d393325SNicolas Chautru  */
12259d393325SNicolas Chautru static inline void
12269d393325SNicolas Chautru rte_bbdev_fft_op_free_bulk(struct rte_bbdev_fft_op **ops, unsigned int num_ops)
12279d393325SNicolas Chautru {
12289d393325SNicolas Chautru 	if (num_ops > 0)
12299d393325SNicolas Chautru 		rte_mempool_put_bulk(ops[0]->mempool, (void **)ops, num_ops);
12309d393325SNicolas Chautru }
12319d393325SNicolas Chautru 
1232089148fcSNicolas Chautru /**
1233089148fcSNicolas Chautru  * Free encode operation structures that were allocated by
1234089148fcSNicolas Chautru  * rte_bbdev_mldts_op_alloc_bulk().
1235089148fcSNicolas Chautru  * All structures must belong to the same mempool.
1236089148fcSNicolas Chautru  *
1237089148fcSNicolas Chautru  * @param ops
1238089148fcSNicolas Chautru  *   Operation structures
1239089148fcSNicolas Chautru  * @param num_ops
1240089148fcSNicolas Chautru  *   Number of structures
1241089148fcSNicolas Chautru  */
1242089148fcSNicolas Chautru static inline void
1243089148fcSNicolas Chautru rte_bbdev_mldts_op_free_bulk(struct rte_bbdev_mldts_op **ops, unsigned int num_ops)
1244089148fcSNicolas Chautru {
1245089148fcSNicolas Chautru 	if (num_ops > 0)
1246089148fcSNicolas Chautru 		rte_mempool_put_bulk(ops[0]->mempool, (void **)ops, num_ops);
1247089148fcSNicolas Chautru }
1248089148fcSNicolas Chautru 
124999a2dd95SBruce Richardson #ifdef __cplusplus
125099a2dd95SBruce Richardson }
125199a2dd95SBruce Richardson #endif
125299a2dd95SBruce Richardson 
125399a2dd95SBruce Richardson #endif /* _RTE_BBDEV_OP_H_ */
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