xref: /dpdk/examples/link_status_interrupt/main.c (revision 98a1648109b8dbaa4e6b821c17d1f6bd86d33a9a)
1af75078fSIntel /*-
2af75078fSIntel  *   BSD LICENSE
3af75078fSIntel  *
4e9d48c00SBruce Richardson  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5af75078fSIntel  *   All rights reserved.
6af75078fSIntel  *
7af75078fSIntel  *   Redistribution and use in source and binary forms, with or without
8af75078fSIntel  *   modification, are permitted provided that the following conditions
9af75078fSIntel  *   are met:
10af75078fSIntel  *
11af75078fSIntel  *     * Redistributions of source code must retain the above copyright
12af75078fSIntel  *       notice, this list of conditions and the following disclaimer.
13af75078fSIntel  *     * Redistributions in binary form must reproduce the above copyright
14af75078fSIntel  *       notice, this list of conditions and the following disclaimer in
15af75078fSIntel  *       the documentation and/or other materials provided with the
16af75078fSIntel  *       distribution.
17af75078fSIntel  *     * Neither the name of Intel Corporation nor the names of its
18af75078fSIntel  *       contributors may be used to endorse or promote products derived
19af75078fSIntel  *       from this software without specific prior written permission.
20af75078fSIntel  *
21af75078fSIntel  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22af75078fSIntel  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23af75078fSIntel  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24af75078fSIntel  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25af75078fSIntel  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26af75078fSIntel  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27af75078fSIntel  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28af75078fSIntel  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29af75078fSIntel  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30af75078fSIntel  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31af75078fSIntel  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32af75078fSIntel  */
33af75078fSIntel 
34af75078fSIntel #include <stdio.h>
35af75078fSIntel #include <stdlib.h>
36af75078fSIntel #include <string.h>
37af75078fSIntel #include <stdint.h>
38af75078fSIntel #include <inttypes.h>
39af75078fSIntel #include <sys/types.h>
40af75078fSIntel #include <string.h>
41af75078fSIntel #include <sys/queue.h>
42af75078fSIntel #include <netinet/in.h>
43af75078fSIntel #include <setjmp.h>
44af75078fSIntel #include <stdarg.h>
45af75078fSIntel #include <ctype.h>
46af75078fSIntel #include <errno.h>
47af75078fSIntel #include <getopt.h>
48af75078fSIntel 
49af75078fSIntel #include <rte_common.h>
50af75078fSIntel #include <rte_log.h>
51af75078fSIntel #include <rte_memory.h>
52af75078fSIntel #include <rte_memcpy.h>
53af75078fSIntel #include <rte_memzone.h>
54af75078fSIntel #include <rte_tailq.h>
55af75078fSIntel #include <rte_eal.h>
56af75078fSIntel #include <rte_per_lcore.h>
57af75078fSIntel #include <rte_launch.h>
58af75078fSIntel #include <rte_atomic.h>
59af75078fSIntel #include <rte_cycles.h>
60af75078fSIntel #include <rte_prefetch.h>
61af75078fSIntel #include <rte_lcore.h>
62af75078fSIntel #include <rte_per_lcore.h>
63af75078fSIntel #include <rte_branch_prediction.h>
64af75078fSIntel #include <rte_interrupts.h>
65af75078fSIntel #include <rte_pci.h>
66af75078fSIntel #include <rte_random.h>
67af75078fSIntel #include <rte_debug.h>
68af75078fSIntel #include <rte_ether.h>
69af75078fSIntel #include <rte_ethdev.h>
70af75078fSIntel #include <rte_ring.h>
71af75078fSIntel #include <rte_mempool.h>
72af75078fSIntel #include <rte_mbuf.h>
73af75078fSIntel 
74af75078fSIntel #define RTE_LOGTYPE_LSI RTE_LOGTYPE_USER1
75af75078fSIntel 
76af75078fSIntel #define MBUF_SIZE (2048 + sizeof(struct rte_mbuf) + RTE_PKTMBUF_HEADROOM)
77af75078fSIntel #define NB_MBUF   8192
78af75078fSIntel 
79af75078fSIntel #define MAX_PKT_BURST 32
805c95261dSIntel #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */
81af75078fSIntel 
82af75078fSIntel /*
83af75078fSIntel  * Configurable number of RX/TX ring descriptors
84af75078fSIntel  */
85af75078fSIntel #define RTE_TEST_RX_DESC_DEFAULT 128
86af75078fSIntel #define RTE_TEST_TX_DESC_DEFAULT 512
87af75078fSIntel static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT;
88af75078fSIntel static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT;
89af75078fSIntel 
90af75078fSIntel /* ethernet addresses of ports */
911c17baf4SIntel static struct ether_addr lsi_ports_eth_addr[RTE_MAX_ETHPORTS];
92af75078fSIntel 
93af75078fSIntel /* mask of enabled ports */
94af75078fSIntel static uint32_t lsi_enabled_port_mask = 0;
95af75078fSIntel 
96af75078fSIntel static unsigned int lsi_rx_queue_per_lcore = 1;
97af75078fSIntel 
98af75078fSIntel /* destination port for L2 forwarding */
991c17baf4SIntel static unsigned lsi_dst_ports[RTE_MAX_ETHPORTS] = {0};
100af75078fSIntel 
101af75078fSIntel #define MAX_PKT_BURST 32
102af75078fSIntel struct mbuf_table {
103af75078fSIntel 	unsigned len;
104af75078fSIntel 	struct rte_mbuf *m_table[MAX_PKT_BURST];
105af75078fSIntel };
106af75078fSIntel 
107af75078fSIntel #define MAX_RX_QUEUE_PER_LCORE 16
108af75078fSIntel #define MAX_TX_QUEUE_PER_PORT 16
109af75078fSIntel struct lcore_queue_conf {
1100c3d715cSIntel 	unsigned n_rx_port;
1110c3d715cSIntel 	unsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];
112af75078fSIntel 	unsigned tx_queue_id;
1131c17baf4SIntel 	struct mbuf_table tx_mbufs[RTE_MAX_ETHPORTS];
114af75078fSIntel 
115af75078fSIntel } __rte_cache_aligned;
116af75078fSIntel struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];
117af75078fSIntel 
118af75078fSIntel static const struct rte_eth_conf port_conf = {
119af75078fSIntel 	.rxmode = {
120af75078fSIntel 		.split_hdr_size = 0,
121af75078fSIntel 		.header_split   = 0, /**< Header Split disabled */
122af75078fSIntel 		.hw_ip_checksum = 0, /**< IP checksum offload disabled */
123af75078fSIntel 		.hw_vlan_filter = 0, /**< VLAN filtering disabled */
124af75078fSIntel 		.jumbo_frame    = 0, /**< Jumbo Frame Support disabled */
125af75078fSIntel 		.hw_strip_crc   = 0, /**< CRC stripped by hardware */
126af75078fSIntel 	},
127af75078fSIntel 	.txmode = {
12832e7aa0bSIntel 		.mq_mode = ETH_MQ_TX_NONE,
129af75078fSIntel 	},
130af75078fSIntel 	.intr_conf = {
131af75078fSIntel 		.lsc = 1, /**< lsc interrupt feature enabled */
132af75078fSIntel 	},
133af75078fSIntel };
134af75078fSIntel 
135af75078fSIntel struct rte_mempool * lsi_pktmbuf_pool = NULL;
136af75078fSIntel 
137af75078fSIntel /* Per-port statistics struct */
138af75078fSIntel struct lsi_port_statistics {
139af75078fSIntel 	uint64_t tx;
140af75078fSIntel 	uint64_t rx;
141af75078fSIntel 	uint64_t dropped;
142af75078fSIntel } __rte_cache_aligned;
1431c17baf4SIntel struct lsi_port_statistics port_statistics[RTE_MAX_ETHPORTS];
144af75078fSIntel 
145af75078fSIntel /* A tsc-based timer responsible for triggering statistics printout */
146af75078fSIntel #define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */
147af75078fSIntel #define MAX_TIMER_PERIOD 86400 /* 1 day max */
148af75078fSIntel static int64_t timer_period = 10 * TIMER_MILLISECOND * 1000; /* default period is 10 seconds */
149af75078fSIntel 
150af75078fSIntel /* Print out statistics on packets dropped */
151af75078fSIntel static void
152af75078fSIntel print_stats(void)
153af75078fSIntel {
154af75078fSIntel 	struct rte_eth_link link;
155af75078fSIntel 	uint64_t total_packets_dropped, total_packets_tx, total_packets_rx;
156af75078fSIntel 	unsigned portid;
157af75078fSIntel 
158af75078fSIntel 	total_packets_dropped = 0;
159af75078fSIntel 	total_packets_tx = 0;
160af75078fSIntel 	total_packets_rx = 0;
161af75078fSIntel 
162af75078fSIntel 	const char clr[] = { 27, '[', '2', 'J', '\0' };
163af75078fSIntel 	const char topLeft[] = { 27, '[', '1', ';', '1', 'H','\0' };
164af75078fSIntel 
165af75078fSIntel 		/* Clear screen and move to top left */
166af75078fSIntel 	printf("%s%s", clr, topLeft);
167af75078fSIntel 
168af75078fSIntel 	printf("\nPort statistics ====================================");
169af75078fSIntel 
1701c17baf4SIntel 	for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {
171af75078fSIntel 		/* skip ports that are not enabled */
172af75078fSIntel 		if ((lsi_enabled_port_mask & (1 << portid)) == 0)
173af75078fSIntel 			continue;
174af75078fSIntel 
175af75078fSIntel 		memset(&link, 0, sizeof(link));
176af75078fSIntel 		rte_eth_link_get_nowait((uint8_t)portid, &link);
177af75078fSIntel 		printf("\nStatistics for port %u ------------------------------"
178af75078fSIntel 			   "\nLink status: %25s"
179af75078fSIntel 			   "\nLink speed: %26u"
180af75078fSIntel 			   "\nLink duplex: %25s"
181af75078fSIntel 			   "\nPackets sent: %24"PRIu64
182af75078fSIntel 			   "\nPackets received: %20"PRIu64
183af75078fSIntel 			   "\nPackets dropped: %21"PRIu64,
184af75078fSIntel 			   portid,
185af75078fSIntel 			   (link.link_status ? "Link up" : "Link down"),
186af75078fSIntel 			   (unsigned)link.link_speed,
187af75078fSIntel 			   (link.link_duplex == ETH_LINK_FULL_DUPLEX ? \
188af75078fSIntel 					"full-duplex" : "half-duplex"),
189af75078fSIntel 			   port_statistics[portid].tx,
190af75078fSIntel 			   port_statistics[portid].rx,
191af75078fSIntel 			   port_statistics[portid].dropped);
192af75078fSIntel 
193af75078fSIntel 		total_packets_dropped += port_statistics[portid].dropped;
194af75078fSIntel 		total_packets_tx += port_statistics[portid].tx;
195af75078fSIntel 		total_packets_rx += port_statistics[portid].rx;
196af75078fSIntel 	}
197af75078fSIntel 	printf("\nAggregate statistics ==============================="
198af75078fSIntel 		   "\nTotal packets sent: %18"PRIu64
199af75078fSIntel 		   "\nTotal packets received: %14"PRIu64
200af75078fSIntel 		   "\nTotal packets dropped: %15"PRIu64,
201af75078fSIntel 		   total_packets_tx,
202af75078fSIntel 		   total_packets_rx,
203af75078fSIntel 		   total_packets_dropped);
204af75078fSIntel 	printf("\n====================================================\n");
205af75078fSIntel }
206af75078fSIntel 
207af75078fSIntel /* Send the packet on an output interface */
208af75078fSIntel static int
209af75078fSIntel lsi_send_burst(struct lcore_queue_conf *qconf, unsigned n, uint8_t port)
210af75078fSIntel {
211af75078fSIntel 	struct rte_mbuf **m_table;
212af75078fSIntel 	unsigned ret;
213af75078fSIntel 	unsigned queueid;
214af75078fSIntel 
215af75078fSIntel 	queueid = (uint16_t) qconf->tx_queue_id;
216af75078fSIntel 	m_table = (struct rte_mbuf **)qconf->tx_mbufs[port].m_table;
217af75078fSIntel 
218af75078fSIntel 	ret = rte_eth_tx_burst(port, (uint16_t) queueid, m_table, (uint16_t) n);
219af75078fSIntel 	port_statistics[port].tx += ret;
220af75078fSIntel 	if (unlikely(ret < n)) {
221af75078fSIntel 		port_statistics[port].dropped += (n - ret);
222af75078fSIntel 		do {
223af75078fSIntel 			rte_pktmbuf_free(m_table[ret]);
224af75078fSIntel 		} while (++ret < n);
225af75078fSIntel 	}
226af75078fSIntel 
227af75078fSIntel 	return 0;
228af75078fSIntel }
229af75078fSIntel 
230af75078fSIntel /* Send the packet on an output interface */
231af75078fSIntel static int
232af75078fSIntel lsi_send_packet(struct rte_mbuf *m, uint8_t port)
233af75078fSIntel {
234af75078fSIntel 	unsigned lcore_id, len;
235af75078fSIntel 	struct lcore_queue_conf *qconf;
236af75078fSIntel 
237af75078fSIntel 	lcore_id = rte_lcore_id();
238af75078fSIntel 
239af75078fSIntel 	qconf = &lcore_queue_conf[lcore_id];
240af75078fSIntel 	len = qconf->tx_mbufs[port].len;
241af75078fSIntel 	qconf->tx_mbufs[port].m_table[len] = m;
242af75078fSIntel 	len++;
243af75078fSIntel 
244af75078fSIntel 	/* enough pkts to be sent */
245af75078fSIntel 	if (unlikely(len == MAX_PKT_BURST)) {
246af75078fSIntel 		lsi_send_burst(qconf, MAX_PKT_BURST, port);
247af75078fSIntel 		len = 0;
248af75078fSIntel 	}
249af75078fSIntel 
250af75078fSIntel 	qconf->tx_mbufs[port].len = len;
251af75078fSIntel 	return 0;
252af75078fSIntel }
253af75078fSIntel 
254af75078fSIntel static void
255af75078fSIntel lsi_simple_forward(struct rte_mbuf *m, unsigned portid)
256af75078fSIntel {
257af75078fSIntel 	struct ether_hdr *eth;
258af75078fSIntel 	void *tmp;
259af75078fSIntel 	unsigned dst_port = lsi_dst_ports[portid];
260af75078fSIntel 
261af75078fSIntel 	eth = rte_pktmbuf_mtod(m, struct ether_hdr *);
262af75078fSIntel 
2630c3d715cSIntel 	/* 02:00:00:00:00:xx */
264af75078fSIntel 	tmp = &eth->d_addr.addr_bytes[0];
2650c3d715cSIntel 	*((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40);
266af75078fSIntel 
267af75078fSIntel 	/* src addr */
268af75078fSIntel 	ether_addr_copy(&lsi_ports_eth_addr[dst_port], &eth->s_addr);
269af75078fSIntel 
270af75078fSIntel 	lsi_send_packet(m, (uint8_t) dst_port);
271af75078fSIntel }
272af75078fSIntel 
273af75078fSIntel /* main processing loop */
274af75078fSIntel static void
275af75078fSIntel lsi_main_loop(void)
276af75078fSIntel {
277af75078fSIntel 	struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
278af75078fSIntel 	struct rte_mbuf *m;
279af75078fSIntel 	unsigned lcore_id;
2805c95261dSIntel 	uint64_t prev_tsc, diff_tsc, cur_tsc, timer_tsc;
281af75078fSIntel 	unsigned i, j, portid, nb_rx;
282af75078fSIntel 	struct lcore_queue_conf *qconf;
2835c95261dSIntel 	const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * BURST_TX_DRAIN_US;
284af75078fSIntel 
2855c95261dSIntel 	prev_tsc = 0;
286af75078fSIntel 	timer_tsc = 0;
287af75078fSIntel 
288af75078fSIntel 	lcore_id = rte_lcore_id();
289af75078fSIntel 	qconf = &lcore_queue_conf[lcore_id];
290af75078fSIntel 
2910c3d715cSIntel 	if (qconf->n_rx_port == 0) {
292af75078fSIntel 		RTE_LOG(INFO, LSI, "lcore %u has nothing to do\n", lcore_id);
293cdfd5dbbSIntel 		return;
294af75078fSIntel 	}
295af75078fSIntel 
296af75078fSIntel 	RTE_LOG(INFO, LSI, "entering main loop on lcore %u\n", lcore_id);
297af75078fSIntel 
2980c3d715cSIntel 	for (i = 0; i < qconf->n_rx_port; i++) {
299af75078fSIntel 
3000c3d715cSIntel 		portid = qconf->rx_port_list[i];
301af75078fSIntel 		RTE_LOG(INFO, LSI, " -- lcoreid=%u portid=%u\n", lcore_id,
302af75078fSIntel 			portid);
303af75078fSIntel 	}
304af75078fSIntel 
305af75078fSIntel 	while (1) {
306af75078fSIntel 
307af75078fSIntel 		cur_tsc = rte_rdtsc();
308af75078fSIntel 
309af75078fSIntel 		/*
310af75078fSIntel 		 * TX burst queue drain
311af75078fSIntel 		 */
312af75078fSIntel 		diff_tsc = cur_tsc - prev_tsc;
3135c95261dSIntel 		if (unlikely(diff_tsc > drain_tsc)) {
314af75078fSIntel 
315af75078fSIntel 			/* this could be optimized (use queueid instead of
316af75078fSIntel 			 * portid), but it is not called so often */
3171c17baf4SIntel 			for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {
318af75078fSIntel 				if (qconf->tx_mbufs[portid].len == 0)
319af75078fSIntel 					continue;
320af75078fSIntel 				lsi_send_burst(&lcore_queue_conf[lcore_id],
321af75078fSIntel 						 qconf->tx_mbufs[portid].len,
322af75078fSIntel 						 (uint8_t) portid);
323af75078fSIntel 				qconf->tx_mbufs[portid].len = 0;
324af75078fSIntel 			}
325af75078fSIntel 
326af75078fSIntel 			/* if timer is enabled */
327af75078fSIntel 			if (timer_period > 0) {
328af75078fSIntel 
329af75078fSIntel 				/* advance the timer */
330af75078fSIntel 				timer_tsc += diff_tsc;
331af75078fSIntel 
332af75078fSIntel 				/* if timer has reached its timeout */
333af75078fSIntel 				if (unlikely(timer_tsc >= (uint64_t) timer_period)) {
334af75078fSIntel 
335af75078fSIntel 					/* do this only on master core */
336af75078fSIntel 					if (lcore_id == rte_get_master_lcore()) {
337af75078fSIntel 						print_stats();
338af75078fSIntel 						/* reset the timer */
339af75078fSIntel 						timer_tsc = 0;
340af75078fSIntel 					}
341af75078fSIntel 				}
342af75078fSIntel 			}
343af75078fSIntel 
344af75078fSIntel 			prev_tsc = cur_tsc;
345af75078fSIntel 		}
346af75078fSIntel 
347af75078fSIntel 		/*
348af75078fSIntel 		 * Read packet from RX queues
349af75078fSIntel 		 */
3500c3d715cSIntel 		for (i = 0; i < qconf->n_rx_port; i++) {
351af75078fSIntel 
3520c3d715cSIntel 			portid = qconf->rx_port_list[i];
353af75078fSIntel 			nb_rx = rte_eth_rx_burst((uint8_t) portid, 0,
354af75078fSIntel 						 pkts_burst, MAX_PKT_BURST);
355af75078fSIntel 
356af75078fSIntel 			port_statistics[portid].rx += nb_rx;
357af75078fSIntel 
358af75078fSIntel 			for (j = 0; j < nb_rx; j++) {
359af75078fSIntel 				m = pkts_burst[j];
360af75078fSIntel 				rte_prefetch0(rte_pktmbuf_mtod(m, void *));
361af75078fSIntel 				lsi_simple_forward(m, portid);
362af75078fSIntel 			}
363af75078fSIntel 		}
364af75078fSIntel 	}
365af75078fSIntel }
366af75078fSIntel 
367af75078fSIntel static int
368af75078fSIntel lsi_launch_one_lcore(__attribute__((unused)) void *dummy)
369af75078fSIntel {
370af75078fSIntel 	lsi_main_loop();
371af75078fSIntel 	return 0;
372af75078fSIntel }
373af75078fSIntel 
374af75078fSIntel /* display usage */
375af75078fSIntel static void
376af75078fSIntel lsi_usage(const char *prgname)
377af75078fSIntel {
378af75078fSIntel 	printf("%s [EAL options] -- -p PORTMASK [-q NQ]\n"
379af75078fSIntel 		"  -p PORTMASK: hexadecimal bitmask of ports to configure\n"
380af75078fSIntel 		"  -q NQ: number of queue (=ports) per lcore (default is 1)\n"
381af75078fSIntel 		"  -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default, 86400 maximum)\n",
382af75078fSIntel 			prgname);
383af75078fSIntel }
384af75078fSIntel 
385af75078fSIntel static int
386af75078fSIntel lsi_parse_portmask(const char *portmask)
387af75078fSIntel {
388af75078fSIntel 	char *end = NULL;
389af75078fSIntel 	unsigned long pm;
390af75078fSIntel 
391af75078fSIntel 	/* parse hexadecimal string */
392af75078fSIntel 	pm = strtoul(portmask, &end, 16);
393af75078fSIntel 	if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
394af75078fSIntel 		return -1;
395af75078fSIntel 
396af75078fSIntel 	if (pm == 0)
397af75078fSIntel 		return -1;
398af75078fSIntel 
399af75078fSIntel 	return pm;
400af75078fSIntel }
401af75078fSIntel 
402af75078fSIntel static unsigned int
403af75078fSIntel lsi_parse_nqueue(const char *q_arg)
404af75078fSIntel {
405af75078fSIntel 	char *end = NULL;
406af75078fSIntel 	unsigned long n;
407af75078fSIntel 
408af75078fSIntel 	/* parse hexadecimal string */
409af75078fSIntel 	n = strtoul(q_arg, &end, 10);
410af75078fSIntel 	if ((q_arg[0] == '\0') || (end == NULL) || (*end != '\0'))
411af75078fSIntel 		return 0;
412af75078fSIntel 	if (n == 0)
413af75078fSIntel 		return 0;
414af75078fSIntel 	if (n >= MAX_RX_QUEUE_PER_LCORE)
415af75078fSIntel 		return 0;
416af75078fSIntel 
417af75078fSIntel 	return n;
418af75078fSIntel }
419af75078fSIntel 
420af75078fSIntel static int
421af75078fSIntel lsi_parse_timer_period(const char *q_arg)
422af75078fSIntel {
423af75078fSIntel 	char *end = NULL;
424af75078fSIntel 	int n;
425af75078fSIntel 
426af75078fSIntel 	/* parse number string */
427af75078fSIntel 	n = strtol(q_arg, &end, 10);
428af75078fSIntel 	if ((q_arg[0] == '\0') || (end == NULL) || (*end != '\0'))
429af75078fSIntel 		return -1;
430af75078fSIntel 	if (n >= MAX_TIMER_PERIOD)
431af75078fSIntel 		return -1;
432af75078fSIntel 
433af75078fSIntel 	return n;
434af75078fSIntel }
435af75078fSIntel 
436af75078fSIntel /* Parse the argument given in the command line of the application */
437af75078fSIntel static int
438af75078fSIntel lsi_parse_args(int argc, char **argv)
439af75078fSIntel {
440af75078fSIntel 	int opt, ret;
441af75078fSIntel 	char **argvopt;
442af75078fSIntel 	int option_index;
443af75078fSIntel 	char *prgname = argv[0];
444af75078fSIntel 	static struct option lgopts[] = {
445af75078fSIntel 		{NULL, 0, 0, 0}
446af75078fSIntel 	};
447af75078fSIntel 
448af75078fSIntel 	argvopt = argv;
449af75078fSIntel 
450af75078fSIntel 	while ((opt = getopt_long(argc, argvopt, "p:q:T:",
451af75078fSIntel 				  lgopts, &option_index)) != EOF) {
452af75078fSIntel 
453af75078fSIntel 		switch (opt) {
454af75078fSIntel 		/* portmask */
455af75078fSIntel 		case 'p':
456af75078fSIntel 			lsi_enabled_port_mask = lsi_parse_portmask(optarg);
457af75078fSIntel 			if (lsi_enabled_port_mask == 0) {
458af75078fSIntel 				printf("invalid portmask\n");
459af75078fSIntel 				lsi_usage(prgname);
460af75078fSIntel 				return -1;
461af75078fSIntel 			}
462af75078fSIntel 			break;
463af75078fSIntel 
464af75078fSIntel 		/* nqueue */
465af75078fSIntel 		case 'q':
466af75078fSIntel 			lsi_rx_queue_per_lcore = lsi_parse_nqueue(optarg);
467af75078fSIntel 			if (lsi_rx_queue_per_lcore == 0) {
468af75078fSIntel 				printf("invalid queue number\n");
469af75078fSIntel 				lsi_usage(prgname);
470af75078fSIntel 				return -1;
471af75078fSIntel 			}
472af75078fSIntel 			break;
473af75078fSIntel 
474af75078fSIntel 		/* timer period */
475af75078fSIntel 		case 'T':
476af75078fSIntel 			timer_period = lsi_parse_timer_period(optarg) * 1000 * TIMER_MILLISECOND;
477af75078fSIntel 			if (timer_period < 0) {
478af75078fSIntel 				printf("invalid timer period\n");
479af75078fSIntel 				lsi_usage(prgname);
480af75078fSIntel 				return -1;
481af75078fSIntel 			}
482af75078fSIntel 			break;
483af75078fSIntel 
484af75078fSIntel 		/* long options */
485af75078fSIntel 		case 0:
486af75078fSIntel 			lsi_usage(prgname);
487af75078fSIntel 			return -1;
488af75078fSIntel 
489af75078fSIntel 		default:
490af75078fSIntel 			lsi_usage(prgname);
491af75078fSIntel 			return -1;
492af75078fSIntel 		}
493af75078fSIntel 	}
494af75078fSIntel 
495af75078fSIntel 	if (optind >= 0)
496af75078fSIntel 		argv[optind-1] = prgname;
497af75078fSIntel 
498af75078fSIntel 	ret = optind-1;
499af75078fSIntel 	optind = 0; /* reset getopt lib */
500af75078fSIntel 	return ret;
501af75078fSIntel }
502af75078fSIntel 
503af75078fSIntel /**
504af75078fSIntel  * It will be called as the callback for specified port after a LSI interrupt
505af75078fSIntel  * has been fully handled. This callback needs to be implemented carefully as
506af75078fSIntel  * it will be called in the interrupt host thread which is different from the
507af75078fSIntel  * application main thread.
508af75078fSIntel  *
509af75078fSIntel  * @param port_id
510af75078fSIntel  *  Port id.
511af75078fSIntel  * @param type
512af75078fSIntel  *  event type.
513af75078fSIntel  * @param param
514af75078fSIntel  *  Pointer to(address of) the parameters.
515af75078fSIntel  *
516af75078fSIntel  * @return
517af75078fSIntel  *  void.
518af75078fSIntel  */
519af75078fSIntel static void
520af75078fSIntel lsi_event_callback(uint8_t port_id, enum rte_eth_event_type type, void *param)
521af75078fSIntel {
522af75078fSIntel 	struct rte_eth_link link;
523af75078fSIntel 
524af75078fSIntel 	RTE_SET_USED(param);
525af75078fSIntel 
526af75078fSIntel 	printf("\n\nIn registered callback...\n");
527af75078fSIntel 	printf("Event type: %s\n", type == RTE_ETH_EVENT_INTR_LSC ? "LSC interrupt" : "unknown event");
528d3641ae8SIntel 	rte_eth_link_get_nowait(port_id, &link);
529af75078fSIntel 	if (link.link_status) {
530af75078fSIntel 		printf("Port %d Link Up - speed %u Mbps - %s\n\n",
531af75078fSIntel 				port_id, (unsigned)link.link_speed,
532af75078fSIntel 			(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
533af75078fSIntel 				("full-duplex") : ("half-duplex"));
534af75078fSIntel 	} else
535af75078fSIntel 		printf("Port %d Link Down\n\n", port_id);
536af75078fSIntel }
537af75078fSIntel 
538d3641ae8SIntel /* Check the link status of all ports in up to 9s, and print them finally */
539d3641ae8SIntel static void
540d3641ae8SIntel check_all_ports_link_status(uint8_t port_num, uint32_t port_mask)
541d3641ae8SIntel {
542d3641ae8SIntel #define CHECK_INTERVAL 100 /* 100ms */
543d3641ae8SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
544d3641ae8SIntel 	uint8_t portid, count, all_ports_up, print_flag = 0;
545d3641ae8SIntel 	struct rte_eth_link link;
546d3641ae8SIntel 
547d3641ae8SIntel 	printf("\nChecking link status");
548d3641ae8SIntel 	fflush(stdout);
549d3641ae8SIntel 	for (count = 0; count <= MAX_CHECK_TIME; count++) {
550d3641ae8SIntel 		all_ports_up = 1;
551d3641ae8SIntel 		for (portid = 0; portid < port_num; portid++) {
552d3641ae8SIntel 			if ((port_mask & (1 << portid)) == 0)
553d3641ae8SIntel 				continue;
554d3641ae8SIntel 			memset(&link, 0, sizeof(link));
555d3641ae8SIntel 			rte_eth_link_get_nowait(portid, &link);
556d3641ae8SIntel 			/* print link status if flag set */
557d3641ae8SIntel 			if (print_flag == 1) {
558d3641ae8SIntel 				if (link.link_status)
559d3641ae8SIntel 					printf("Port %d Link Up - speed %u "
560d3641ae8SIntel 						"Mbps - %s\n", (uint8_t)portid,
561d3641ae8SIntel 						(unsigned)link.link_speed,
562d3641ae8SIntel 				(link.link_duplex == ETH_LINK_FULL_DUPLEX) ?
563d3641ae8SIntel 					("full-duplex") : ("half-duplex\n"));
564d3641ae8SIntel 				else
565d3641ae8SIntel 					printf("Port %d Link Down\n",
566d3641ae8SIntel 							(uint8_t)portid);
567d3641ae8SIntel 				continue;
568d3641ae8SIntel 			}
569d3641ae8SIntel 			/* clear all_ports_up flag if any link down */
570d3641ae8SIntel 			if (link.link_status == 0) {
571d3641ae8SIntel 				all_ports_up = 0;
572d3641ae8SIntel 				break;
573d3641ae8SIntel 			}
574d3641ae8SIntel 		}
575d3641ae8SIntel 		/* after finally printing all link status, get out */
576d3641ae8SIntel 		if (print_flag == 1)
577d3641ae8SIntel 			break;
578d3641ae8SIntel 
579d3641ae8SIntel 		if (all_ports_up == 0) {
580d3641ae8SIntel 			printf(".");
581d3641ae8SIntel 			fflush(stdout);
582d3641ae8SIntel 			rte_delay_ms(CHECK_INTERVAL);
583d3641ae8SIntel 		}
584d3641ae8SIntel 
585d3641ae8SIntel 		/* set the print_flag if all ports up or timeout */
586d3641ae8SIntel 		if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {
587d3641ae8SIntel 			print_flag = 1;
588d3641ae8SIntel 			printf("done\n");
589d3641ae8SIntel 		}
590d3641ae8SIntel 	}
591d3641ae8SIntel }
592d3641ae8SIntel 
593af75078fSIntel int
594*98a16481SDavid Marchand main(int argc, char **argv)
595af75078fSIntel {
596af75078fSIntel 	struct lcore_queue_conf *qconf;
597af75078fSIntel 	struct rte_eth_dev_info dev_info;
598af75078fSIntel 	int ret;
599a974564bSIntel 	uint8_t nb_ports;
600a974564bSIntel 	uint8_t portid, portid_last = 0;
601af75078fSIntel 	unsigned lcore_id, rx_lcore_id;
602af75078fSIntel 	unsigned nb_ports_in_mask = 0;
603af75078fSIntel 
604af75078fSIntel 	/* init EAL */
605af75078fSIntel 	ret = rte_eal_init(argc, argv);
606af75078fSIntel 	if (ret < 0)
607af75078fSIntel 		rte_exit(EXIT_FAILURE, "rte_eal_init failed");
608af75078fSIntel 	argc -= ret;
609af75078fSIntel 	argv += ret;
610af75078fSIntel 
611af75078fSIntel 	/* parse application arguments (after the EAL ones) */
612af75078fSIntel 	ret = lsi_parse_args(argc, argv);
613af75078fSIntel 	if (ret < 0)
614af75078fSIntel 		rte_exit(EXIT_FAILURE, "Invalid arguments");
615af75078fSIntel 
616af75078fSIntel 	/* create the mbuf pool */
617af75078fSIntel 	lsi_pktmbuf_pool =
618af75078fSIntel 		rte_mempool_create("mbuf_pool", NB_MBUF,
619af75078fSIntel 				   MBUF_SIZE, 32,
620af75078fSIntel 				   sizeof(struct rte_pktmbuf_pool_private),
621af75078fSIntel 				   rte_pktmbuf_pool_init, NULL,
622af75078fSIntel 				   rte_pktmbuf_init, NULL,
623e60f71ebSIntel 				   rte_socket_id(), 0);
624af75078fSIntel 	if (lsi_pktmbuf_pool == NULL)
625af75078fSIntel 		rte_panic("Cannot init mbuf pool\n");
626af75078fSIntel 
627af75078fSIntel 	nb_ports = rte_eth_dev_count();
628af75078fSIntel 	if (nb_ports == 0)
629af75078fSIntel 		rte_panic("No Ethernet port - bye\n");
630af75078fSIntel 
6311c17baf4SIntel 	if (nb_ports > RTE_MAX_ETHPORTS)
6321c17baf4SIntel 		nb_ports = RTE_MAX_ETHPORTS;
633af75078fSIntel 
634af75078fSIntel 	/*
635af75078fSIntel 	 * Each logical core is assigned a dedicated TX queue on each port.
636af75078fSIntel 	 */
637af75078fSIntel 	for (portid = 0; portid < nb_ports; portid++) {
638af75078fSIntel 		/* skip ports that are not enabled */
639af75078fSIntel 		if ((lsi_enabled_port_mask & (1 << portid)) == 0)
640af75078fSIntel 			continue;
641af75078fSIntel 
642af75078fSIntel 		/* save the destination port id */
643af75078fSIntel 		if (nb_ports_in_mask % 2) {
644af75078fSIntel 			lsi_dst_ports[portid] = portid_last;
645af75078fSIntel 			lsi_dst_ports[portid_last] = portid;
646af75078fSIntel 		}
647af75078fSIntel 		else
648af75078fSIntel 			portid_last = portid;
649af75078fSIntel 
650af75078fSIntel 		nb_ports_in_mask++;
651af75078fSIntel 
652a974564bSIntel 		rte_eth_dev_info_get(portid, &dev_info);
653af75078fSIntel 	}
654af75078fSIntel 	if (nb_ports_in_mask < 2 || nb_ports_in_mask % 2)
655af75078fSIntel 		rte_exit(EXIT_FAILURE, "Current enabled port number is %u, "
656af75078fSIntel 				"but it should be even and at least 2\n",
657af75078fSIntel 				nb_ports_in_mask);
658af75078fSIntel 
659af75078fSIntel 	rx_lcore_id = 0;
660af75078fSIntel 	qconf = &lcore_queue_conf[rx_lcore_id];
661af75078fSIntel 
662af75078fSIntel 	/* Initialize the port/queue configuration of each logical core */
663af75078fSIntel 	for (portid = 0; portid < nb_ports; portid++) {
664af75078fSIntel 		/* skip ports that are not enabled */
665af75078fSIntel 		if ((lsi_enabled_port_mask & (1 << portid)) == 0)
666af75078fSIntel 			continue;
667af75078fSIntel 
668af75078fSIntel 		/* get the lcore_id for this port */
669af75078fSIntel 		while (rte_lcore_is_enabled(rx_lcore_id) == 0 ||
6700c3d715cSIntel 		       lcore_queue_conf[rx_lcore_id].n_rx_port ==
671af75078fSIntel 		       lsi_rx_queue_per_lcore) {
672af75078fSIntel 
673af75078fSIntel 			rx_lcore_id++;
674af75078fSIntel 			if (rx_lcore_id >= RTE_MAX_LCORE)
675af75078fSIntel 				rte_exit(EXIT_FAILURE, "Not enough cores\n");
676af75078fSIntel 		}
6770c3d715cSIntel 		if (qconf != &lcore_queue_conf[rx_lcore_id])
678af75078fSIntel 			/* Assigned a new logical core in the loop above. */
679af75078fSIntel 			qconf = &lcore_queue_conf[rx_lcore_id];
6800c3d715cSIntel 
6810c3d715cSIntel 		qconf->rx_port_list[qconf->n_rx_port] = portid;
6820c3d715cSIntel 		qconf->n_rx_port++;
683a974564bSIntel 		printf("Lcore %u: RX port %u\n",rx_lcore_id, (unsigned) portid);
684af75078fSIntel 	}
685af75078fSIntel 
686af75078fSIntel 	/* Initialise each port */
687af75078fSIntel 	for (portid = 0; portid < nb_ports; portid++) {
688af75078fSIntel 		/* skip ports that are not enabled */
689af75078fSIntel 		if ((lsi_enabled_port_mask & (1 << portid)) == 0) {
690a974564bSIntel 			printf("Skipping disabled port %u\n", (unsigned) portid);
691af75078fSIntel 			continue;
692af75078fSIntel 		}
693af75078fSIntel 		/* init port */
694a974564bSIntel 		printf("Initializing port %u... ", (unsigned) portid);
695af75078fSIntel 		fflush(stdout);
696a974564bSIntel 		ret = rte_eth_dev_configure(portid, 1, 1, &port_conf);
697af75078fSIntel 		if (ret < 0)
698af75078fSIntel 			rte_exit(EXIT_FAILURE, "Cannot configure device: err=%d, port=%u\n",
699a974564bSIntel 				  ret, (unsigned) portid);
700af75078fSIntel 
701af75078fSIntel 		/* register lsi interrupt callback, need to be after
702af75078fSIntel 		 * rte_eth_dev_configure(). if (intr_conf.lsc == 0), no
703af75078fSIntel 		 * lsc interrupt will be present, and below callback to
704af75078fSIntel 		 * be registered will never be called.
705af75078fSIntel 		 */
706a974564bSIntel 		rte_eth_dev_callback_register(portid,
707af75078fSIntel 			RTE_ETH_EVENT_INTR_LSC, lsi_event_callback, NULL);
708af75078fSIntel 
709a974564bSIntel 		rte_eth_macaddr_get(portid,
710af75078fSIntel 				    &lsi_ports_eth_addr[portid]);
711af75078fSIntel 
712af75078fSIntel 		/* init one RX queue */
713af75078fSIntel 		fflush(stdout);
714a974564bSIntel 		ret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,
71581f7ecd9SPablo de Lara 					     rte_eth_dev_socket_id(portid),
71681f7ecd9SPablo de Lara 					     NULL,
717af75078fSIntel 					     lsi_pktmbuf_pool);
718af75078fSIntel 		if (ret < 0)
719a974564bSIntel 			rte_exit(EXIT_FAILURE, "rte_eth_rx_queue_setup: err=%d, port=%u\n",
720a974564bSIntel 				  ret, (unsigned) portid);
721af75078fSIntel 
722af75078fSIntel 		/* init one TX queue logical core on each port */
723af75078fSIntel 		fflush(stdout);
724a974564bSIntel 		ret = rte_eth_tx_queue_setup(portid, 0, nb_txd,
72581f7ecd9SPablo de Lara 				rte_eth_dev_socket_id(portid),
72681f7ecd9SPablo de Lara 				NULL);
727af75078fSIntel 		if (ret < 0)
7280c3d715cSIntel 			rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d,port=%u\n",
729a974564bSIntel 				  ret, (unsigned) portid);
730af75078fSIntel 
731af75078fSIntel 		/* Start device */
732a974564bSIntel 		ret = rte_eth_dev_start(portid);
733af75078fSIntel 		if (ret < 0)
734af75078fSIntel 			rte_exit(EXIT_FAILURE, "rte_eth_dev_start: err=%d, port=%u\n",
735a974564bSIntel 				  ret, (unsigned) portid);
736d3641ae8SIntel 		printf("done:\n");
737af75078fSIntel 
738af75078fSIntel 		printf("Port %u, MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n\n",
739a974564bSIntel 				(unsigned) portid,
740af75078fSIntel 				lsi_ports_eth_addr[portid].addr_bytes[0],
741af75078fSIntel 				lsi_ports_eth_addr[portid].addr_bytes[1],
742af75078fSIntel 				lsi_ports_eth_addr[portid].addr_bytes[2],
743af75078fSIntel 				lsi_ports_eth_addr[portid].addr_bytes[3],
744af75078fSIntel 				lsi_ports_eth_addr[portid].addr_bytes[4],
745af75078fSIntel 				lsi_ports_eth_addr[portid].addr_bytes[5]);
746af75078fSIntel 
747af75078fSIntel 		/* initialize port stats */
748af75078fSIntel 		memset(&port_statistics, 0, sizeof(port_statistics));
749af75078fSIntel 	}
750af75078fSIntel 
751a974564bSIntel 	check_all_ports_link_status(nb_ports, lsi_enabled_port_mask);
752d3641ae8SIntel 
753af75078fSIntel 	/* launch per-lcore init on every lcore */
754af75078fSIntel 	rte_eal_mp_remote_launch(lsi_launch_one_lcore, NULL, CALL_MASTER);
755af75078fSIntel 	RTE_LCORE_FOREACH_SLAVE(lcore_id) {
756af75078fSIntel 		if (rte_eal_wait_lcore(lcore_id) < 0)
757af75078fSIntel 			return -1;
758af75078fSIntel 	}
759af75078fSIntel 
760af75078fSIntel 	return 0;
761af75078fSIntel }
762