13998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause 23998e2a0SBruce Richardson * Copyright(c) 2010-2016 Intel Corporation 3af75078fSIntel */ 4af75078fSIntel 5af75078fSIntel #include <stdio.h> 6af75078fSIntel #include <stdlib.h> 7af75078fSIntel #include <string.h> 8af75078fSIntel #include <stdint.h> 9af75078fSIntel #include <inttypes.h> 10af75078fSIntel #include <sys/types.h> 11af75078fSIntel #include <sys/queue.h> 12af75078fSIntel #include <netinet/in.h> 13af75078fSIntel #include <setjmp.h> 14af75078fSIntel #include <stdarg.h> 15af75078fSIntel #include <ctype.h> 16af75078fSIntel #include <errno.h> 17af75078fSIntel #include <getopt.h> 18af75078fSIntel 19af75078fSIntel #include <rte_common.h> 20af75078fSIntel #include <rte_log.h> 21e2366e74STomasz Kulasek #include <rte_malloc.h> 22af75078fSIntel #include <rte_memory.h> 23af75078fSIntel #include <rte_memcpy.h> 24af75078fSIntel #include <rte_eal.h> 25af75078fSIntel #include <rte_launch.h> 26af75078fSIntel #include <rte_atomic.h> 27af75078fSIntel #include <rte_cycles.h> 28af75078fSIntel #include <rte_prefetch.h> 29af75078fSIntel #include <rte_lcore.h> 30af75078fSIntel #include <rte_per_lcore.h> 31af75078fSIntel #include <rte_branch_prediction.h> 32af75078fSIntel #include <rte_interrupts.h> 33af75078fSIntel #include <rte_random.h> 34af75078fSIntel #include <rte_debug.h> 35af75078fSIntel #include <rte_ether.h> 36af75078fSIntel #include <rte_ethdev.h> 37af75078fSIntel #include <rte_mempool.h> 38af75078fSIntel #include <rte_mbuf.h> 39af75078fSIntel 40af75078fSIntel #define RTE_LOGTYPE_LSI RTE_LOGTYPE_USER1 41af75078fSIntel 42af75078fSIntel #define NB_MBUF 8192 43af75078fSIntel 44af75078fSIntel #define MAX_PKT_BURST 32 455c95261dSIntel #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */ 46af75078fSIntel 47af75078fSIntel /* 48af75078fSIntel * Configurable number of RX/TX ring descriptors 49af75078fSIntel */ 50867a6c66SKevin Laatz #define RTE_TEST_RX_DESC_DEFAULT 1024 51867a6c66SKevin Laatz #define RTE_TEST_TX_DESC_DEFAULT 1024 52af75078fSIntel static uint16_t nb_rxd = RTE_TEST_RX_DESC_DEFAULT; 53af75078fSIntel static uint16_t nb_txd = RTE_TEST_TX_DESC_DEFAULT; 54af75078fSIntel 55af75078fSIntel /* ethernet addresses of ports */ 566d13ea8eSOlivier Matz static struct rte_ether_addr lsi_ports_eth_addr[RTE_MAX_ETHPORTS]; 57af75078fSIntel 58af75078fSIntel /* mask of enabled ports */ 59af75078fSIntel static uint32_t lsi_enabled_port_mask = 0; 60af75078fSIntel 61af75078fSIntel static unsigned int lsi_rx_queue_per_lcore = 1; 62af75078fSIntel 63af75078fSIntel /* destination port for L2 forwarding */ 641c17baf4SIntel static unsigned lsi_dst_ports[RTE_MAX_ETHPORTS] = {0}; 65af75078fSIntel 66af75078fSIntel #define MAX_PKT_BURST 32 67af75078fSIntel 68af75078fSIntel #define MAX_RX_QUEUE_PER_LCORE 16 69af75078fSIntel #define MAX_TX_QUEUE_PER_PORT 16 70af75078fSIntel struct lcore_queue_conf { 710c3d715cSIntel unsigned n_rx_port; 720c3d715cSIntel unsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE]; 73af75078fSIntel unsigned tx_queue_id; 74af75078fSIntel } __rte_cache_aligned; 75af75078fSIntel struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE]; 76af75078fSIntel 77e2366e74STomasz Kulasek struct rte_eth_dev_tx_buffer *tx_buffer[RTE_MAX_ETHPORTS]; 78e2366e74STomasz Kulasek 79312967c3SShahaf Shuler static struct rte_eth_conf port_conf = { 80af75078fSIntel .rxmode = { 81af75078fSIntel .split_hdr_size = 0, 82af75078fSIntel }, 83af75078fSIntel .txmode = { 8432e7aa0bSIntel .mq_mode = ETH_MQ_TX_NONE, 85af75078fSIntel }, 86af75078fSIntel .intr_conf = { 87af75078fSIntel .lsc = 1, /**< lsc interrupt feature enabled */ 88af75078fSIntel }, 89af75078fSIntel }; 90af75078fSIntel 91af75078fSIntel struct rte_mempool * lsi_pktmbuf_pool = NULL; 92af75078fSIntel 93af75078fSIntel /* Per-port statistics struct */ 94af75078fSIntel struct lsi_port_statistics { 95af75078fSIntel uint64_t tx; 96af75078fSIntel uint64_t rx; 97af75078fSIntel uint64_t dropped; 98af75078fSIntel } __rte_cache_aligned; 991c17baf4SIntel struct lsi_port_statistics port_statistics[RTE_MAX_ETHPORTS]; 100af75078fSIntel 101af75078fSIntel /* A tsc-based timer responsible for triggering statistics printout */ 102af75078fSIntel #define TIMER_MILLISECOND 2000000ULL /* around 1ms at 2 Ghz */ 103af75078fSIntel #define MAX_TIMER_PERIOD 86400 /* 1 day max */ 104af75078fSIntel static int64_t timer_period = 10 * TIMER_MILLISECOND * 1000; /* default period is 10 seconds */ 105af75078fSIntel 106af75078fSIntel /* Print out statistics on packets dropped */ 107af75078fSIntel static void 108af75078fSIntel print_stats(void) 109af75078fSIntel { 110af75078fSIntel struct rte_eth_link link; 111af75078fSIntel uint64_t total_packets_dropped, total_packets_tx, total_packets_rx; 112f8244c63SZhiyong Yang uint16_t portid; 113af75078fSIntel 114af75078fSIntel total_packets_dropped = 0; 115af75078fSIntel total_packets_tx = 0; 116af75078fSIntel total_packets_rx = 0; 117af75078fSIntel 118af75078fSIntel const char clr[] = { 27, '[', '2', 'J', '\0' }; 119af75078fSIntel const char topLeft[] = { 27, '[', '1', ';', '1', 'H','\0' }; 120af75078fSIntel 121af75078fSIntel /* Clear screen and move to top left */ 122af75078fSIntel printf("%s%s", clr, topLeft); 123af75078fSIntel 124af75078fSIntel printf("\nPort statistics ===================================="); 125af75078fSIntel 1261c17baf4SIntel for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) { 127af75078fSIntel /* skip ports that are not enabled */ 128af75078fSIntel if ((lsi_enabled_port_mask & (1 << portid)) == 0) 129af75078fSIntel continue; 130af75078fSIntel 131af75078fSIntel memset(&link, 0, sizeof(link)); 132f8244c63SZhiyong Yang rte_eth_link_get_nowait(portid, &link); 133af75078fSIntel printf("\nStatistics for port %u ------------------------------" 134af75078fSIntel "\nLink status: %25s" 135af75078fSIntel "\nLink speed: %26u" 136af75078fSIntel "\nLink duplex: %25s" 137af75078fSIntel "\nPackets sent: %24"PRIu64 138af75078fSIntel "\nPackets received: %20"PRIu64 139af75078fSIntel "\nPackets dropped: %21"PRIu64, 140af75078fSIntel portid, 141af75078fSIntel (link.link_status ? "Link up" : "Link down"), 142af75078fSIntel (unsigned)link.link_speed, 143af75078fSIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX ? \ 144af75078fSIntel "full-duplex" : "half-duplex"), 145af75078fSIntel port_statistics[portid].tx, 146af75078fSIntel port_statistics[portid].rx, 147af75078fSIntel port_statistics[portid].dropped); 148af75078fSIntel 149af75078fSIntel total_packets_dropped += port_statistics[portid].dropped; 150af75078fSIntel total_packets_tx += port_statistics[portid].tx; 151af75078fSIntel total_packets_rx += port_statistics[portid].rx; 152af75078fSIntel } 153af75078fSIntel printf("\nAggregate statistics ===============================" 154af75078fSIntel "\nTotal packets sent: %18"PRIu64 155af75078fSIntel "\nTotal packets received: %14"PRIu64 156af75078fSIntel "\nTotal packets dropped: %15"PRIu64, 157af75078fSIntel total_packets_tx, 158af75078fSIntel total_packets_rx, 159af75078fSIntel total_packets_dropped); 160af75078fSIntel printf("\n====================================================\n"); 161af75078fSIntel } 162af75078fSIntel 163af75078fSIntel static void 164af75078fSIntel lsi_simple_forward(struct rte_mbuf *m, unsigned portid) 165af75078fSIntel { 1666d13ea8eSOlivier Matz struct rte_ether_hdr *eth; 167af75078fSIntel void *tmp; 168af75078fSIntel unsigned dst_port = lsi_dst_ports[portid]; 169e2366e74STomasz Kulasek int sent; 170e2366e74STomasz Kulasek struct rte_eth_dev_tx_buffer *buffer; 171af75078fSIntel 1726d13ea8eSOlivier Matz eth = rte_pktmbuf_mtod(m, struct rte_ether_hdr *); 173af75078fSIntel 1740c3d715cSIntel /* 02:00:00:00:00:xx */ 175af75078fSIntel tmp = ð->d_addr.addr_bytes[0]; 1760c3d715cSIntel *((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40); 177af75078fSIntel 178af75078fSIntel /* src addr */ 179538da7a1SOlivier Matz rte_ether_addr_copy(&lsi_ports_eth_addr[dst_port], ð->s_addr); 180af75078fSIntel 181e2366e74STomasz Kulasek buffer = tx_buffer[dst_port]; 182e2366e74STomasz Kulasek sent = rte_eth_tx_buffer(dst_port, 0, buffer, m); 183e2366e74STomasz Kulasek if (sent) 184e2366e74STomasz Kulasek port_statistics[dst_port].tx += sent; 185af75078fSIntel } 186af75078fSIntel 187af75078fSIntel /* main processing loop */ 188af75078fSIntel static void 189af75078fSIntel lsi_main_loop(void) 190af75078fSIntel { 191af75078fSIntel struct rte_mbuf *pkts_burst[MAX_PKT_BURST]; 192af75078fSIntel struct rte_mbuf *m; 193af75078fSIntel unsigned lcore_id; 194e2366e74STomasz Kulasek unsigned sent; 1955c95261dSIntel uint64_t prev_tsc, diff_tsc, cur_tsc, timer_tsc; 196af75078fSIntel unsigned i, j, portid, nb_rx; 197af75078fSIntel struct lcore_queue_conf *qconf; 198e2366e74STomasz Kulasek const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S * 199e2366e74STomasz Kulasek BURST_TX_DRAIN_US; 200e2366e74STomasz Kulasek struct rte_eth_dev_tx_buffer *buffer; 201af75078fSIntel 2025c95261dSIntel prev_tsc = 0; 203af75078fSIntel timer_tsc = 0; 204af75078fSIntel 205af75078fSIntel lcore_id = rte_lcore_id(); 206af75078fSIntel qconf = &lcore_queue_conf[lcore_id]; 207af75078fSIntel 2080c3d715cSIntel if (qconf->n_rx_port == 0) { 209af75078fSIntel RTE_LOG(INFO, LSI, "lcore %u has nothing to do\n", lcore_id); 210cdfd5dbbSIntel return; 211af75078fSIntel } 212af75078fSIntel 213af75078fSIntel RTE_LOG(INFO, LSI, "entering main loop on lcore %u\n", lcore_id); 214af75078fSIntel 2150c3d715cSIntel for (i = 0; i < qconf->n_rx_port; i++) { 216af75078fSIntel 2170c3d715cSIntel portid = qconf->rx_port_list[i]; 218af75078fSIntel RTE_LOG(INFO, LSI, " -- lcoreid=%u portid=%u\n", lcore_id, 219af75078fSIntel portid); 220af75078fSIntel } 221af75078fSIntel 222af75078fSIntel while (1) { 223af75078fSIntel 224af75078fSIntel cur_tsc = rte_rdtsc(); 225af75078fSIntel 226af75078fSIntel /* 227af75078fSIntel * TX burst queue drain 228af75078fSIntel */ 229af75078fSIntel diff_tsc = cur_tsc - prev_tsc; 2305c95261dSIntel if (unlikely(diff_tsc > drain_tsc)) { 231af75078fSIntel 232e2366e74STomasz Kulasek for (i = 0; i < qconf->n_rx_port; i++) { 233e2366e74STomasz Kulasek 234e2366e74STomasz Kulasek portid = lsi_dst_ports[qconf->rx_port_list[i]]; 235e2366e74STomasz Kulasek buffer = tx_buffer[portid]; 236e2366e74STomasz Kulasek 237e2366e74STomasz Kulasek sent = rte_eth_tx_buffer_flush(portid, 0, buffer); 238e2366e74STomasz Kulasek if (sent) 239e2366e74STomasz Kulasek port_statistics[portid].tx += sent; 240e2366e74STomasz Kulasek 241af75078fSIntel } 242af75078fSIntel 243af75078fSIntel /* if timer is enabled */ 244af75078fSIntel if (timer_period > 0) { 245af75078fSIntel 246af75078fSIntel /* advance the timer */ 247af75078fSIntel timer_tsc += diff_tsc; 248af75078fSIntel 249af75078fSIntel /* if timer has reached its timeout */ 250af75078fSIntel if (unlikely(timer_tsc >= (uint64_t) timer_period)) { 251af75078fSIntel 252af75078fSIntel /* do this only on master core */ 253af75078fSIntel if (lcore_id == rte_get_master_lcore()) { 254af75078fSIntel print_stats(); 255af75078fSIntel /* reset the timer */ 256af75078fSIntel timer_tsc = 0; 257af75078fSIntel } 258af75078fSIntel } 259af75078fSIntel } 260af75078fSIntel 261af75078fSIntel prev_tsc = cur_tsc; 262af75078fSIntel } 263af75078fSIntel 264af75078fSIntel /* 265af75078fSIntel * Read packet from RX queues 266af75078fSIntel */ 2670c3d715cSIntel for (i = 0; i < qconf->n_rx_port; i++) { 268af75078fSIntel 2690c3d715cSIntel portid = qconf->rx_port_list[i]; 270af75078fSIntel nb_rx = rte_eth_rx_burst((uint8_t) portid, 0, 271af75078fSIntel pkts_burst, MAX_PKT_BURST); 272af75078fSIntel 273af75078fSIntel port_statistics[portid].rx += nb_rx; 274af75078fSIntel 275af75078fSIntel for (j = 0; j < nb_rx; j++) { 276af75078fSIntel m = pkts_burst[j]; 277af75078fSIntel rte_prefetch0(rte_pktmbuf_mtod(m, void *)); 278af75078fSIntel lsi_simple_forward(m, portid); 279af75078fSIntel } 280af75078fSIntel } 281af75078fSIntel } 282af75078fSIntel } 283af75078fSIntel 284af75078fSIntel static int 285af75078fSIntel lsi_launch_one_lcore(__attribute__((unused)) void *dummy) 286af75078fSIntel { 287af75078fSIntel lsi_main_loop(); 288af75078fSIntel return 0; 289af75078fSIntel } 290af75078fSIntel 291af75078fSIntel /* display usage */ 292af75078fSIntel static void 293af75078fSIntel lsi_usage(const char *prgname) 294af75078fSIntel { 295af75078fSIntel printf("%s [EAL options] -- -p PORTMASK [-q NQ]\n" 296af75078fSIntel " -p PORTMASK: hexadecimal bitmask of ports to configure\n" 297af75078fSIntel " -q NQ: number of queue (=ports) per lcore (default is 1)\n" 298af75078fSIntel " -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default, 86400 maximum)\n", 299af75078fSIntel prgname); 300af75078fSIntel } 301af75078fSIntel 302af75078fSIntel static int 303af75078fSIntel lsi_parse_portmask(const char *portmask) 304af75078fSIntel { 305af75078fSIntel char *end = NULL; 306af75078fSIntel unsigned long pm; 307af75078fSIntel 308af75078fSIntel /* parse hexadecimal string */ 309af75078fSIntel pm = strtoul(portmask, &end, 16); 310af75078fSIntel if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0')) 311af75078fSIntel return -1; 312af75078fSIntel 313af75078fSIntel if (pm == 0) 314af75078fSIntel return -1; 315af75078fSIntel 316af75078fSIntel return pm; 317af75078fSIntel } 318af75078fSIntel 319af75078fSIntel static unsigned int 320af75078fSIntel lsi_parse_nqueue(const char *q_arg) 321af75078fSIntel { 322af75078fSIntel char *end = NULL; 323af75078fSIntel unsigned long n; 324af75078fSIntel 325af75078fSIntel /* parse hexadecimal string */ 326af75078fSIntel n = strtoul(q_arg, &end, 10); 327af75078fSIntel if ((q_arg[0] == '\0') || (end == NULL) || (*end != '\0')) 328af75078fSIntel return 0; 329af75078fSIntel if (n == 0) 330af75078fSIntel return 0; 331af75078fSIntel if (n >= MAX_RX_QUEUE_PER_LCORE) 332af75078fSIntel return 0; 333af75078fSIntel 334af75078fSIntel return n; 335af75078fSIntel } 336af75078fSIntel 337af75078fSIntel static int 338af75078fSIntel lsi_parse_timer_period(const char *q_arg) 339af75078fSIntel { 340af75078fSIntel char *end = NULL; 341af75078fSIntel int n; 342af75078fSIntel 343af75078fSIntel /* parse number string */ 344af75078fSIntel n = strtol(q_arg, &end, 10); 345af75078fSIntel if ((q_arg[0] == '\0') || (end == NULL) || (*end != '\0')) 346af75078fSIntel return -1; 347af75078fSIntel if (n >= MAX_TIMER_PERIOD) 348af75078fSIntel return -1; 349af75078fSIntel 350af75078fSIntel return n; 351af75078fSIntel } 352af75078fSIntel 353af75078fSIntel /* Parse the argument given in the command line of the application */ 354af75078fSIntel static int 355af75078fSIntel lsi_parse_args(int argc, char **argv) 356af75078fSIntel { 357af75078fSIntel int opt, ret; 358af75078fSIntel char **argvopt; 359af75078fSIntel int option_index; 360af75078fSIntel char *prgname = argv[0]; 361af75078fSIntel static struct option lgopts[] = { 362af75078fSIntel {NULL, 0, 0, 0} 363af75078fSIntel }; 364af75078fSIntel 365af75078fSIntel argvopt = argv; 366af75078fSIntel 367af75078fSIntel while ((opt = getopt_long(argc, argvopt, "p:q:T:", 368af75078fSIntel lgopts, &option_index)) != EOF) { 369af75078fSIntel 370af75078fSIntel switch (opt) { 371af75078fSIntel /* portmask */ 372af75078fSIntel case 'p': 373af75078fSIntel lsi_enabled_port_mask = lsi_parse_portmask(optarg); 374af75078fSIntel if (lsi_enabled_port_mask == 0) { 375af75078fSIntel printf("invalid portmask\n"); 376af75078fSIntel lsi_usage(prgname); 377af75078fSIntel return -1; 378af75078fSIntel } 379af75078fSIntel break; 380af75078fSIntel 381af75078fSIntel /* nqueue */ 382af75078fSIntel case 'q': 383af75078fSIntel lsi_rx_queue_per_lcore = lsi_parse_nqueue(optarg); 384af75078fSIntel if (lsi_rx_queue_per_lcore == 0) { 385af75078fSIntel printf("invalid queue number\n"); 386af75078fSIntel lsi_usage(prgname); 387af75078fSIntel return -1; 388af75078fSIntel } 389af75078fSIntel break; 390af75078fSIntel 391af75078fSIntel /* timer period */ 392af75078fSIntel case 'T': 393af75078fSIntel timer_period = lsi_parse_timer_period(optarg) * 1000 * TIMER_MILLISECOND; 394af75078fSIntel if (timer_period < 0) { 395af75078fSIntel printf("invalid timer period\n"); 396af75078fSIntel lsi_usage(prgname); 397af75078fSIntel return -1; 398af75078fSIntel } 399af75078fSIntel break; 400af75078fSIntel 401af75078fSIntel /* long options */ 402af75078fSIntel case 0: 403af75078fSIntel lsi_usage(prgname); 404af75078fSIntel return -1; 405af75078fSIntel 406af75078fSIntel default: 407af75078fSIntel lsi_usage(prgname); 408af75078fSIntel return -1; 409af75078fSIntel } 410af75078fSIntel } 411af75078fSIntel 412af75078fSIntel if (optind >= 0) 413af75078fSIntel argv[optind-1] = prgname; 414af75078fSIntel 415af75078fSIntel ret = optind-1; 4169d5ca532SKeith Wiles optind = 1; /* reset getopt lib */ 417af75078fSIntel return ret; 418af75078fSIntel } 419af75078fSIntel 420af75078fSIntel /** 421af75078fSIntel * It will be called as the callback for specified port after a LSI interrupt 422af75078fSIntel * has been fully handled. This callback needs to be implemented carefully as 423af75078fSIntel * it will be called in the interrupt host thread which is different from the 424af75078fSIntel * application main thread. 425af75078fSIntel * 426af75078fSIntel * @param port_id 427af75078fSIntel * Port id. 428af75078fSIntel * @param type 429af75078fSIntel * event type. 430af75078fSIntel * @param param 431af75078fSIntel * Pointer to(address of) the parameters. 432af75078fSIntel * 433af75078fSIntel * @return 434d6af1a13SBernard Iremonger * int. 435af75078fSIntel */ 436d6af1a13SBernard Iremonger static int 437f8244c63SZhiyong Yang lsi_event_callback(uint16_t port_id, enum rte_eth_event_type type, void *param, 438d6af1a13SBernard Iremonger void *ret_param) 439af75078fSIntel { 440af75078fSIntel struct rte_eth_link link; 441af75078fSIntel 442af75078fSIntel RTE_SET_USED(param); 443d6af1a13SBernard Iremonger RTE_SET_USED(ret_param); 444af75078fSIntel 445af75078fSIntel printf("\n\nIn registered callback...\n"); 446af75078fSIntel printf("Event type: %s\n", type == RTE_ETH_EVENT_INTR_LSC ? "LSC interrupt" : "unknown event"); 447d3641ae8SIntel rte_eth_link_get_nowait(port_id, &link); 448af75078fSIntel if (link.link_status) { 449af75078fSIntel printf("Port %d Link Up - speed %u Mbps - %s\n\n", 450af75078fSIntel port_id, (unsigned)link.link_speed, 451af75078fSIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 452af75078fSIntel ("full-duplex") : ("half-duplex")); 453af75078fSIntel } else 454af75078fSIntel printf("Port %d Link Down\n\n", port_id); 455d6af1a13SBernard Iremonger 456d6af1a13SBernard Iremonger return 0; 457af75078fSIntel } 458af75078fSIntel 459d3641ae8SIntel /* Check the link status of all ports in up to 9s, and print them finally */ 460d3641ae8SIntel static void 46147523597SZhiyong Yang check_all_ports_link_status(uint16_t port_num, uint32_t port_mask) 462d3641ae8SIntel { 463d3641ae8SIntel #define CHECK_INTERVAL 100 /* 100ms */ 464d3641ae8SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */ 465f8244c63SZhiyong Yang uint8_t count, all_ports_up, print_flag = 0; 466f8244c63SZhiyong Yang uint16_t portid; 467d3641ae8SIntel struct rte_eth_link link; 468d3641ae8SIntel 469d3641ae8SIntel printf("\nChecking link status"); 470d3641ae8SIntel fflush(stdout); 471d3641ae8SIntel for (count = 0; count <= MAX_CHECK_TIME; count++) { 472d3641ae8SIntel all_ports_up = 1; 473d3641ae8SIntel for (portid = 0; portid < port_num; portid++) { 474d3641ae8SIntel if ((port_mask & (1 << portid)) == 0) 475d3641ae8SIntel continue; 476d3641ae8SIntel memset(&link, 0, sizeof(link)); 477d3641ae8SIntel rte_eth_link_get_nowait(portid, &link); 478d3641ae8SIntel /* print link status if flag set */ 479d3641ae8SIntel if (print_flag == 1) { 480d3641ae8SIntel if (link.link_status) 48147523597SZhiyong Yang printf( 48247523597SZhiyong Yang "Port%d Link Up. Speed %u Mbps - %s\n", 48347523597SZhiyong Yang portid, link.link_speed, 484d3641ae8SIntel (link.link_duplex == ETH_LINK_FULL_DUPLEX) ? 485d3641ae8SIntel ("full-duplex") : ("half-duplex\n")); 486d3641ae8SIntel else 48747523597SZhiyong Yang printf("Port %d Link Down\n", portid); 488d3641ae8SIntel continue; 489d3641ae8SIntel } 490d3641ae8SIntel /* clear all_ports_up flag if any link down */ 49109419f23SThomas Monjalon if (link.link_status == ETH_LINK_DOWN) { 492d3641ae8SIntel all_ports_up = 0; 493d3641ae8SIntel break; 494d3641ae8SIntel } 495d3641ae8SIntel } 496d3641ae8SIntel /* after finally printing all link status, get out */ 497d3641ae8SIntel if (print_flag == 1) 498d3641ae8SIntel break; 499d3641ae8SIntel 500d3641ae8SIntel if (all_ports_up == 0) { 501d3641ae8SIntel printf("."); 502d3641ae8SIntel fflush(stdout); 503d3641ae8SIntel rte_delay_ms(CHECK_INTERVAL); 504d3641ae8SIntel } 505d3641ae8SIntel 506d3641ae8SIntel /* set the print_flag if all ports up or timeout */ 507d3641ae8SIntel if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) { 508d3641ae8SIntel print_flag = 1; 509d3641ae8SIntel printf("done\n"); 510d3641ae8SIntel } 511d3641ae8SIntel } 512d3641ae8SIntel } 513d3641ae8SIntel 514af75078fSIntel int 51598a16481SDavid Marchand main(int argc, char **argv) 516af75078fSIntel { 517af75078fSIntel struct lcore_queue_conf *qconf; 518af75078fSIntel int ret; 51947523597SZhiyong Yang uint16_t nb_ports; 52047523597SZhiyong Yang uint16_t portid, portid_last = 0; 521af75078fSIntel unsigned lcore_id, rx_lcore_id; 522af75078fSIntel unsigned nb_ports_in_mask = 0; 523af75078fSIntel 524af75078fSIntel /* init EAL */ 525af75078fSIntel ret = rte_eal_init(argc, argv); 526af75078fSIntel if (ret < 0) 527af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eal_init failed"); 528af75078fSIntel argc -= ret; 529af75078fSIntel argv += ret; 530af75078fSIntel 531af75078fSIntel /* parse application arguments (after the EAL ones) */ 532af75078fSIntel ret = lsi_parse_args(argc, argv); 533af75078fSIntel if (ret < 0) 534af75078fSIntel rte_exit(EXIT_FAILURE, "Invalid arguments"); 535af75078fSIntel 536af75078fSIntel /* create the mbuf pool */ 537af75078fSIntel lsi_pktmbuf_pool = 538ea0c20eaSOlivier Matz rte_pktmbuf_pool_create("mbuf_pool", NB_MBUF, 32, 0, 539824cb29cSKonstantin Ananyev RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id()); 540af75078fSIntel if (lsi_pktmbuf_pool == NULL) 541af75078fSIntel rte_panic("Cannot init mbuf pool\n"); 542af75078fSIntel 543d9a42a69SThomas Monjalon nb_ports = rte_eth_dev_count_avail(); 544af75078fSIntel if (nb_ports == 0) 545af75078fSIntel rte_panic("No Ethernet port - bye\n"); 546af75078fSIntel 547af75078fSIntel /* 548af75078fSIntel * Each logical core is assigned a dedicated TX queue on each port. 549af75078fSIntel */ 550af75078fSIntel for (portid = 0; portid < nb_ports; portid++) { 551af75078fSIntel /* skip ports that are not enabled */ 552af75078fSIntel if ((lsi_enabled_port_mask & (1 << portid)) == 0) 553af75078fSIntel continue; 554af75078fSIntel 555af75078fSIntel /* save the destination port id */ 556af75078fSIntel if (nb_ports_in_mask % 2) { 557af75078fSIntel lsi_dst_ports[portid] = portid_last; 558af75078fSIntel lsi_dst_ports[portid_last] = portid; 559af75078fSIntel } 560af75078fSIntel else 561af75078fSIntel portid_last = portid; 562af75078fSIntel 563af75078fSIntel nb_ports_in_mask++; 564af75078fSIntel } 565af75078fSIntel if (nb_ports_in_mask < 2 || nb_ports_in_mask % 2) 566af75078fSIntel rte_exit(EXIT_FAILURE, "Current enabled port number is %u, " 567af75078fSIntel "but it should be even and at least 2\n", 568af75078fSIntel nb_ports_in_mask); 569af75078fSIntel 570af75078fSIntel rx_lcore_id = 0; 571af75078fSIntel qconf = &lcore_queue_conf[rx_lcore_id]; 572af75078fSIntel 573af75078fSIntel /* Initialize the port/queue configuration of each logical core */ 574af75078fSIntel for (portid = 0; portid < nb_ports; portid++) { 575af75078fSIntel /* skip ports that are not enabled */ 576af75078fSIntel if ((lsi_enabled_port_mask & (1 << portid)) == 0) 577af75078fSIntel continue; 578af75078fSIntel 579af75078fSIntel /* get the lcore_id for this port */ 580af75078fSIntel while (rte_lcore_is_enabled(rx_lcore_id) == 0 || 5810c3d715cSIntel lcore_queue_conf[rx_lcore_id].n_rx_port == 582af75078fSIntel lsi_rx_queue_per_lcore) { 583af75078fSIntel 584af75078fSIntel rx_lcore_id++; 585af75078fSIntel if (rx_lcore_id >= RTE_MAX_LCORE) 586af75078fSIntel rte_exit(EXIT_FAILURE, "Not enough cores\n"); 587af75078fSIntel } 5880c3d715cSIntel if (qconf != &lcore_queue_conf[rx_lcore_id]) 589af75078fSIntel /* Assigned a new logical core in the loop above. */ 590af75078fSIntel qconf = &lcore_queue_conf[rx_lcore_id]; 5910c3d715cSIntel 5920c3d715cSIntel qconf->rx_port_list[qconf->n_rx_port] = portid; 5930c3d715cSIntel qconf->n_rx_port++; 594a974564bSIntel printf("Lcore %u: RX port %u\n",rx_lcore_id, (unsigned) portid); 595af75078fSIntel } 596af75078fSIntel 597af75078fSIntel /* Initialise each port */ 598af75078fSIntel for (portid = 0; portid < nb_ports; portid++) { 599312967c3SShahaf Shuler struct rte_eth_rxconf rxq_conf; 600312967c3SShahaf Shuler struct rte_eth_txconf txq_conf; 601312967c3SShahaf Shuler struct rte_eth_conf local_port_conf = port_conf; 602312967c3SShahaf Shuler struct rte_eth_dev_info dev_info; 603312967c3SShahaf Shuler 604af75078fSIntel /* skip ports that are not enabled */ 605af75078fSIntel if ((lsi_enabled_port_mask & (1 << portid)) == 0) { 606a974564bSIntel printf("Skipping disabled port %u\n", (unsigned) portid); 607af75078fSIntel continue; 608af75078fSIntel } 609af75078fSIntel /* init port */ 610a974564bSIntel printf("Initializing port %u... ", (unsigned) portid); 611af75078fSIntel fflush(stdout); 612*089e5ed7SIvan Ilchenko 613*089e5ed7SIvan Ilchenko ret = rte_eth_dev_info_get(portid, &dev_info); 614*089e5ed7SIvan Ilchenko if (ret != 0) 615*089e5ed7SIvan Ilchenko rte_exit(EXIT_FAILURE, 616*089e5ed7SIvan Ilchenko "Error during getting device (port %u) info: %s\n", 617*089e5ed7SIvan Ilchenko portid, strerror(-ret)); 618*089e5ed7SIvan Ilchenko 619312967c3SShahaf Shuler if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE) 620312967c3SShahaf Shuler local_port_conf.txmode.offloads |= 621312967c3SShahaf Shuler DEV_TX_OFFLOAD_MBUF_FAST_FREE; 622312967c3SShahaf Shuler ret = rte_eth_dev_configure(portid, 1, 1, &local_port_conf); 623af75078fSIntel if (ret < 0) 624af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot configure device: err=%d, port=%u\n", 625a974564bSIntel ret, (unsigned) portid); 626af75078fSIntel 62760efb44fSRoman Zhukov ret = rte_eth_dev_adjust_nb_rx_tx_desc(portid, &nb_rxd, 62860efb44fSRoman Zhukov &nb_txd); 62960efb44fSRoman Zhukov if (ret < 0) 63060efb44fSRoman Zhukov rte_exit(EXIT_FAILURE, 63160efb44fSRoman Zhukov "rte_eth_dev_adjust_nb_rx_tx_desc: err=%d, port=%u\n", 63260efb44fSRoman Zhukov ret, (unsigned) portid); 63360efb44fSRoman Zhukov 634af75078fSIntel /* register lsi interrupt callback, need to be after 635af75078fSIntel * rte_eth_dev_configure(). if (intr_conf.lsc == 0), no 636af75078fSIntel * lsc interrupt will be present, and below callback to 637af75078fSIntel * be registered will never be called. 638af75078fSIntel */ 639a974564bSIntel rte_eth_dev_callback_register(portid, 640af75078fSIntel RTE_ETH_EVENT_INTR_LSC, lsi_event_callback, NULL); 641af75078fSIntel 642a974564bSIntel rte_eth_macaddr_get(portid, 643af75078fSIntel &lsi_ports_eth_addr[portid]); 644af75078fSIntel 645af75078fSIntel /* init one RX queue */ 646af75078fSIntel fflush(stdout); 647312967c3SShahaf Shuler rxq_conf = dev_info.default_rxconf; 648312967c3SShahaf Shuler rxq_conf.offloads = local_port_conf.rxmode.offloads; 649a974564bSIntel ret = rte_eth_rx_queue_setup(portid, 0, nb_rxd, 65081f7ecd9SPablo de Lara rte_eth_dev_socket_id(portid), 651312967c3SShahaf Shuler &rxq_conf, 652af75078fSIntel lsi_pktmbuf_pool); 653af75078fSIntel if (ret < 0) 654a974564bSIntel rte_exit(EXIT_FAILURE, "rte_eth_rx_queue_setup: err=%d, port=%u\n", 655a974564bSIntel ret, (unsigned) portid); 656af75078fSIntel 657af75078fSIntel /* init one TX queue logical core on each port */ 658af75078fSIntel fflush(stdout); 659312967c3SShahaf Shuler txq_conf = dev_info.default_txconf; 660312967c3SShahaf Shuler txq_conf.offloads = local_port_conf.txmode.offloads; 661a974564bSIntel ret = rte_eth_tx_queue_setup(portid, 0, nb_txd, 66281f7ecd9SPablo de Lara rte_eth_dev_socket_id(portid), 663312967c3SShahaf Shuler &txq_conf); 664af75078fSIntel if (ret < 0) 6650c3d715cSIntel rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d,port=%u\n", 666a974564bSIntel ret, (unsigned) portid); 667af75078fSIntel 668e2366e74STomasz Kulasek /* Initialize TX buffers */ 669e2366e74STomasz Kulasek tx_buffer[portid] = rte_zmalloc_socket("tx_buffer", 670e2366e74STomasz Kulasek RTE_ETH_TX_BUFFER_SIZE(MAX_PKT_BURST), 0, 671e2366e74STomasz Kulasek rte_eth_dev_socket_id(portid)); 672e2366e74STomasz Kulasek if (tx_buffer[portid] == NULL) 673e2366e74STomasz Kulasek rte_exit(EXIT_FAILURE, "Cannot allocate buffer for tx on port %u\n", 674e2366e74STomasz Kulasek (unsigned) portid); 675e2366e74STomasz Kulasek 676e2366e74STomasz Kulasek rte_eth_tx_buffer_init(tx_buffer[portid], MAX_PKT_BURST); 677e2366e74STomasz Kulasek 678e2366e74STomasz Kulasek ret = rte_eth_tx_buffer_set_err_callback(tx_buffer[portid], 679e2366e74STomasz Kulasek rte_eth_tx_buffer_count_callback, 680e2366e74STomasz Kulasek &port_statistics[portid].dropped); 681e2366e74STomasz Kulasek if (ret < 0) 682e2366e74STomasz Kulasek rte_exit(EXIT_FAILURE, "Cannot set error callback for " 683e2366e74STomasz Kulasek "tx buffer on port %u\n", (unsigned) portid); 684e2366e74STomasz Kulasek 685af75078fSIntel /* Start device */ 686a974564bSIntel ret = rte_eth_dev_start(portid); 687af75078fSIntel if (ret < 0) 688af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eth_dev_start: err=%d, port=%u\n", 689a974564bSIntel ret, (unsigned) portid); 690d3641ae8SIntel printf("done:\n"); 691af75078fSIntel 692e2366e74STomasz Kulasek rte_eth_promiscuous_enable(portid); 693e2366e74STomasz Kulasek 694af75078fSIntel printf("Port %u, MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n\n", 695a974564bSIntel (unsigned) portid, 696af75078fSIntel lsi_ports_eth_addr[portid].addr_bytes[0], 697af75078fSIntel lsi_ports_eth_addr[portid].addr_bytes[1], 698af75078fSIntel lsi_ports_eth_addr[portid].addr_bytes[2], 699af75078fSIntel lsi_ports_eth_addr[portid].addr_bytes[3], 700af75078fSIntel lsi_ports_eth_addr[portid].addr_bytes[4], 701af75078fSIntel lsi_ports_eth_addr[portid].addr_bytes[5]); 702af75078fSIntel 703af75078fSIntel /* initialize port stats */ 704af75078fSIntel memset(&port_statistics, 0, sizeof(port_statistics)); 705af75078fSIntel } 706af75078fSIntel 707a974564bSIntel check_all_ports_link_status(nb_ports, lsi_enabled_port_mask); 708d3641ae8SIntel 709af75078fSIntel /* launch per-lcore init on every lcore */ 710af75078fSIntel rte_eal_mp_remote_launch(lsi_launch_one_lcore, NULL, CALL_MASTER); 711af75078fSIntel RTE_LCORE_FOREACH_SLAVE(lcore_id) { 712af75078fSIntel if (rte_eal_wait_lcore(lcore_id) < 0) 713af75078fSIntel return -1; 714af75078fSIntel } 715af75078fSIntel 716af75078fSIntel return 0; 717af75078fSIntel } 718