13998e2a0SBruce Richardson /* SPDX-License-Identifier: BSD-3-Clause
23998e2a0SBruce Richardson * Copyright(c) 2010-2016 Intel Corporation
3af75078fSIntel */
4af75078fSIntel
5af75078fSIntel #include <stdio.h>
6af75078fSIntel #include <stdlib.h>
7af75078fSIntel #include <string.h>
8af75078fSIntel #include <stdint.h>
9af75078fSIntel #include <inttypes.h>
10af75078fSIntel #include <sys/types.h>
11af75078fSIntel #include <sys/queue.h>
12af75078fSIntel #include <setjmp.h>
13af75078fSIntel #include <stdarg.h>
14af75078fSIntel #include <ctype.h>
15af75078fSIntel #include <errno.h>
16af75078fSIntel #include <getopt.h>
17af75078fSIntel
18af75078fSIntel #include <rte_common.h>
19af75078fSIntel #include <rte_log.h>
20e2366e74STomasz Kulasek #include <rte_malloc.h>
21af75078fSIntel #include <rte_memory.h>
22af75078fSIntel #include <rte_memcpy.h>
23af75078fSIntel #include <rte_eal.h>
24af75078fSIntel #include <rte_launch.h>
25af75078fSIntel #include <rte_cycles.h>
26af75078fSIntel #include <rte_prefetch.h>
27af75078fSIntel #include <rte_lcore.h>
28af75078fSIntel #include <rte_per_lcore.h>
29af75078fSIntel #include <rte_branch_prediction.h>
30af75078fSIntel #include <rte_interrupts.h>
31af75078fSIntel #include <rte_random.h>
32af75078fSIntel #include <rte_debug.h>
33af75078fSIntel #include <rte_ether.h>
34af75078fSIntel #include <rte_ethdev.h>
35af75078fSIntel #include <rte_mempool.h>
36af75078fSIntel #include <rte_mbuf.h>
37af75078fSIntel
38af75078fSIntel #define RTE_LOGTYPE_LSI RTE_LOGTYPE_USER1
39af75078fSIntel
40af75078fSIntel #define NB_MBUF 8192
41af75078fSIntel
42af75078fSIntel #define MAX_PKT_BURST 32
435c95261dSIntel #define BURST_TX_DRAIN_US 100 /* TX drain every ~100us */
44af75078fSIntel
45af75078fSIntel /*
46af75078fSIntel * Configurable number of RX/TX ring descriptors
47af75078fSIntel */
484ed89049SDavid Marchand #define RX_DESC_DEFAULT 1024
494ed89049SDavid Marchand #define TX_DESC_DEFAULT 1024
504ed89049SDavid Marchand static uint16_t nb_rxd = RX_DESC_DEFAULT;
514ed89049SDavid Marchand static uint16_t nb_txd = TX_DESC_DEFAULT;
52af75078fSIntel
53af75078fSIntel /* ethernet addresses of ports */
546d13ea8eSOlivier Matz static struct rte_ether_addr lsi_ports_eth_addr[RTE_MAX_ETHPORTS];
55af75078fSIntel
56af75078fSIntel /* mask of enabled ports */
57af75078fSIntel static uint32_t lsi_enabled_port_mask = 0;
58af75078fSIntel
59af75078fSIntel static unsigned int lsi_rx_queue_per_lcore = 1;
60af75078fSIntel
61af75078fSIntel /* destination port for L2 forwarding */
621c17baf4SIntel static unsigned lsi_dst_ports[RTE_MAX_ETHPORTS] = {0};
63af75078fSIntel
64af75078fSIntel #define MAX_PKT_BURST 32
65af75078fSIntel
66af75078fSIntel #define MAX_RX_QUEUE_PER_LCORE 16
67af75078fSIntel #define MAX_TX_QUEUE_PER_PORT 16
689a212dc0SConor Fogarty /* List of queues must be polled for a give lcore. 8< */
69*7e06c0deSTyler Retzlaff struct __rte_cache_aligned lcore_queue_conf {
700c3d715cSIntel unsigned n_rx_port;
710c3d715cSIntel unsigned rx_port_list[MAX_RX_QUEUE_PER_LCORE];
72af75078fSIntel unsigned tx_queue_id;
73*7e06c0deSTyler Retzlaff };
74af75078fSIntel struct lcore_queue_conf lcore_queue_conf[RTE_MAX_LCORE];
759a212dc0SConor Fogarty /* >8 End of list of queues to be polled. */
76af75078fSIntel
77e2366e74STomasz Kulasek struct rte_eth_dev_tx_buffer *tx_buffer[RTE_MAX_ETHPORTS];
78e2366e74STomasz Kulasek
799a212dc0SConor Fogarty /* Global configuration stored in a static structure. 8< */
80312967c3SShahaf Shuler static struct rte_eth_conf port_conf = {
81af75078fSIntel .txmode = {
82295968d1SFerruh Yigit .mq_mode = RTE_ETH_MQ_TX_NONE,
83af75078fSIntel },
84af75078fSIntel .intr_conf = {
85af75078fSIntel .lsc = 1, /**< lsc interrupt feature enabled */
86af75078fSIntel },
87af75078fSIntel };
889a212dc0SConor Fogarty /* >8 End of global configuration stored in a static structure. */
89af75078fSIntel
90af75078fSIntel struct rte_mempool * lsi_pktmbuf_pool = NULL;
91af75078fSIntel
92af75078fSIntel /* Per-port statistics struct */
93*7e06c0deSTyler Retzlaff struct __rte_cache_aligned lsi_port_statistics {
94af75078fSIntel uint64_t tx;
95af75078fSIntel uint64_t rx;
96af75078fSIntel uint64_t dropped;
97*7e06c0deSTyler Retzlaff };
981c17baf4SIntel struct lsi_port_statistics port_statistics[RTE_MAX_ETHPORTS];
99af75078fSIntel
100af75078fSIntel /* A tsc-based timer responsible for triggering statistics printout */
10114d460b8SRaja Zidane #define TIMER_MILLISECOND (rte_get_timer_hz() / 1000)
102af75078fSIntel #define MAX_TIMER_PERIOD 86400 /* 1 day max */
10314d460b8SRaja Zidane #define DEFAULT_TIMER_PERIOD 10UL /* default period is 10 seconds */
10414d460b8SRaja Zidane static int64_t timer_period;
105af75078fSIntel
106af75078fSIntel /* Print out statistics on packets dropped */
107af75078fSIntel static void
print_stats(void)108af75078fSIntel print_stats(void)
109af75078fSIntel {
110af75078fSIntel struct rte_eth_link link;
111af75078fSIntel uint64_t total_packets_dropped, total_packets_tx, total_packets_rx;
112f8244c63SZhiyong Yang uint16_t portid;
113af75078fSIntel
114af75078fSIntel total_packets_dropped = 0;
115af75078fSIntel total_packets_tx = 0;
116af75078fSIntel total_packets_rx = 0;
117af75078fSIntel
118af75078fSIntel const char clr[] = { 27, '[', '2', 'J', '\0' };
119af75078fSIntel const char topLeft[] = { 27, '[', '1', ';', '1', 'H','\0' };
12022e5c73bSIgor Romanov int link_get_err;
121af75078fSIntel
122af75078fSIntel /* Clear screen and move to top left */
123af75078fSIntel printf("%s%s", clr, topLeft);
124af75078fSIntel
125af75078fSIntel printf("\nPort statistics ====================================");
126af75078fSIntel
1271c17baf4SIntel for (portid = 0; portid < RTE_MAX_ETHPORTS; portid++) {
128af75078fSIntel /* skip ports that are not enabled */
129af75078fSIntel if ((lsi_enabled_port_mask & (1 << portid)) == 0)
130af75078fSIntel continue;
131af75078fSIntel
132af75078fSIntel memset(&link, 0, sizeof(link));
13322e5c73bSIgor Romanov link_get_err = rte_eth_link_get_nowait(portid, &link);
134af75078fSIntel printf("\nStatistics for port %u ------------------------------"
135af75078fSIntel "\nLink status: %25s"
136db4e8135SIvan Dyukov "\nLink speed: %26s"
137af75078fSIntel "\nLink duplex: %25s"
138af75078fSIntel "\nPackets sent: %24"PRIu64
139af75078fSIntel "\nPackets received: %20"PRIu64
140af75078fSIntel "\nPackets dropped: %21"PRIu64,
141af75078fSIntel portid,
14222e5c73bSIgor Romanov link_get_err < 0 ? "Link get failed" :
143af75078fSIntel (link.link_status ? "Link up" : "Link down"),
144db4e8135SIvan Dyukov link_get_err < 0 ? "0" :
145db4e8135SIvan Dyukov rte_eth_link_speed_to_str(link.link_speed),
14622e5c73bSIgor Romanov link_get_err < 0 ? "Link get failed" :
147295968d1SFerruh Yigit (link.link_duplex == RTE_ETH_LINK_FULL_DUPLEX ?
148af75078fSIntel "full-duplex" : "half-duplex"),
149af75078fSIntel port_statistics[portid].tx,
150af75078fSIntel port_statistics[portid].rx,
151af75078fSIntel port_statistics[portid].dropped);
152af75078fSIntel
153af75078fSIntel total_packets_dropped += port_statistics[portid].dropped;
154af75078fSIntel total_packets_tx += port_statistics[portid].tx;
155af75078fSIntel total_packets_rx += port_statistics[portid].rx;
156af75078fSIntel }
157af75078fSIntel printf("\nAggregate statistics ==============================="
158af75078fSIntel "\nTotal packets sent: %18"PRIu64
159af75078fSIntel "\nTotal packets received: %14"PRIu64
160af75078fSIntel "\nTotal packets dropped: %15"PRIu64,
161af75078fSIntel total_packets_tx,
162af75078fSIntel total_packets_rx,
163af75078fSIntel total_packets_dropped);
164af75078fSIntel printf("\n====================================================\n");
1653ee6f706SGeorgiy Levashov
1663ee6f706SGeorgiy Levashov fflush(stdout);
167af75078fSIntel }
168af75078fSIntel
1699a212dc0SConor Fogarty /* Replacing the source and destination MAC addresses. 8< */
170af75078fSIntel static void
lsi_simple_forward(struct rte_mbuf * m,unsigned portid)171af75078fSIntel lsi_simple_forward(struct rte_mbuf *m, unsigned portid)
172af75078fSIntel {
1736d13ea8eSOlivier Matz struct rte_ether_hdr *eth;
174af75078fSIntel void *tmp;
175af75078fSIntel unsigned dst_port = lsi_dst_ports[portid];
176e2366e74STomasz Kulasek int sent;
177e2366e74STomasz Kulasek struct rte_eth_dev_tx_buffer *buffer;
178af75078fSIntel
1796d13ea8eSOlivier Matz eth = rte_pktmbuf_mtod(m, struct rte_ether_hdr *);
180af75078fSIntel
1810c3d715cSIntel /* 02:00:00:00:00:xx */
18204d43857SDmitry Kozlyuk tmp = ð->dst_addr.addr_bytes[0];
1830c3d715cSIntel *((uint64_t *)tmp) = 0x000000000002 + ((uint64_t)dst_port << 40);
184af75078fSIntel
185af75078fSIntel /* src addr */
18604d43857SDmitry Kozlyuk rte_ether_addr_copy(&lsi_ports_eth_addr[dst_port], ð->src_addr);
187af75078fSIntel
188e2366e74STomasz Kulasek buffer = tx_buffer[dst_port];
189e2366e74STomasz Kulasek sent = rte_eth_tx_buffer(dst_port, 0, buffer, m);
190e2366e74STomasz Kulasek if (sent)
191e2366e74STomasz Kulasek port_statistics[dst_port].tx += sent;
192af75078fSIntel }
1939a212dc0SConor Fogarty /* >8 End of replacing the source and destination MAC addresses. */
194af75078fSIntel
195af75078fSIntel /* main processing loop */
196af75078fSIntel static void
lsi_main_loop(void)197af75078fSIntel lsi_main_loop(void)
198af75078fSIntel {
199af75078fSIntel struct rte_mbuf *pkts_burst[MAX_PKT_BURST];
200af75078fSIntel struct rte_mbuf *m;
201af75078fSIntel unsigned lcore_id;
202e2366e74STomasz Kulasek unsigned sent;
2035c95261dSIntel uint64_t prev_tsc, diff_tsc, cur_tsc, timer_tsc;
204af75078fSIntel unsigned i, j, portid, nb_rx;
205af75078fSIntel struct lcore_queue_conf *qconf;
206e2366e74STomasz Kulasek const uint64_t drain_tsc = (rte_get_tsc_hz() + US_PER_S - 1) / US_PER_S *
207e2366e74STomasz Kulasek BURST_TX_DRAIN_US;
208e2366e74STomasz Kulasek struct rte_eth_dev_tx_buffer *buffer;
209af75078fSIntel
2105c95261dSIntel prev_tsc = 0;
211af75078fSIntel timer_tsc = 0;
212af75078fSIntel
213af75078fSIntel lcore_id = rte_lcore_id();
214af75078fSIntel qconf = &lcore_queue_conf[lcore_id];
215af75078fSIntel
2160c3d715cSIntel if (qconf->n_rx_port == 0) {
217af75078fSIntel RTE_LOG(INFO, LSI, "lcore %u has nothing to do\n", lcore_id);
218cdfd5dbbSIntel return;
219af75078fSIntel }
220af75078fSIntel
221af75078fSIntel RTE_LOG(INFO, LSI, "entering main loop on lcore %u\n", lcore_id);
222af75078fSIntel
2230c3d715cSIntel for (i = 0; i < qconf->n_rx_port; i++) {
224af75078fSIntel
2250c3d715cSIntel portid = qconf->rx_port_list[i];
226af75078fSIntel RTE_LOG(INFO, LSI, " -- lcoreid=%u portid=%u\n", lcore_id,
227af75078fSIntel portid);
228af75078fSIntel }
229af75078fSIntel
230af75078fSIntel while (1) {
231af75078fSIntel
2329a212dc0SConor Fogarty /* Draining TX queue in its main loop. 8< */
233af75078fSIntel cur_tsc = rte_rdtsc();
234af75078fSIntel
235af75078fSIntel /*
236af75078fSIntel * TX burst queue drain
237af75078fSIntel */
238af75078fSIntel diff_tsc = cur_tsc - prev_tsc;
2395c95261dSIntel if (unlikely(diff_tsc > drain_tsc)) {
240af75078fSIntel
241e2366e74STomasz Kulasek for (i = 0; i < qconf->n_rx_port; i++) {
242e2366e74STomasz Kulasek
243e2366e74STomasz Kulasek portid = lsi_dst_ports[qconf->rx_port_list[i]];
244e2366e74STomasz Kulasek buffer = tx_buffer[portid];
245e2366e74STomasz Kulasek
246e2366e74STomasz Kulasek sent = rte_eth_tx_buffer_flush(portid, 0, buffer);
247e2366e74STomasz Kulasek if (sent)
248e2366e74STomasz Kulasek port_statistics[portid].tx += sent;
249e2366e74STomasz Kulasek
250af75078fSIntel }
251af75078fSIntel
252af75078fSIntel /* if timer is enabled */
253af75078fSIntel if (timer_period > 0) {
254af75078fSIntel
255af75078fSIntel /* advance the timer */
256af75078fSIntel timer_tsc += diff_tsc;
257af75078fSIntel
258af75078fSIntel /* if timer has reached its timeout */
259af75078fSIntel if (unlikely(timer_tsc >= (uint64_t) timer_period)) {
260af75078fSIntel
261cb056611SStephen Hemminger /* do this only on main core */
262cb056611SStephen Hemminger if (lcore_id == rte_get_main_lcore()) {
263af75078fSIntel print_stats();
264af75078fSIntel /* reset the timer */
265af75078fSIntel timer_tsc = 0;
266af75078fSIntel }
267af75078fSIntel }
268af75078fSIntel }
269af75078fSIntel
270af75078fSIntel prev_tsc = cur_tsc;
271af75078fSIntel }
2729a212dc0SConor Fogarty /* >8 End of draining TX queue in its main loop. */
273af75078fSIntel
2749a212dc0SConor Fogarty /* Read packet from RX queues. 8< */
2750c3d715cSIntel for (i = 0; i < qconf->n_rx_port; i++) {
276af75078fSIntel
2770c3d715cSIntel portid = qconf->rx_port_list[i];
278af75078fSIntel nb_rx = rte_eth_rx_burst((uint8_t) portid, 0,
279af75078fSIntel pkts_burst, MAX_PKT_BURST);
280af75078fSIntel
281af75078fSIntel port_statistics[portid].rx += nb_rx;
282af75078fSIntel
283af75078fSIntel for (j = 0; j < nb_rx; j++) {
284af75078fSIntel m = pkts_burst[j];
285af75078fSIntel rte_prefetch0(rte_pktmbuf_mtod(m, void *));
286af75078fSIntel lsi_simple_forward(m, portid);
287af75078fSIntel }
288af75078fSIntel }
2899a212dc0SConor Fogarty /* >8 End of reading packet from RX queues. */
290af75078fSIntel }
291af75078fSIntel }
292af75078fSIntel
293af75078fSIntel static int
lsi_launch_one_lcore(__rte_unused void * dummy)294f2fc83b4SThomas Monjalon lsi_launch_one_lcore(__rte_unused void *dummy)
295af75078fSIntel {
296af75078fSIntel lsi_main_loop();
297af75078fSIntel return 0;
298af75078fSIntel }
299af75078fSIntel
300af75078fSIntel /* display usage */
301af75078fSIntel static void
lsi_usage(const char * prgname)302af75078fSIntel lsi_usage(const char *prgname)
303af75078fSIntel {
304af75078fSIntel printf("%s [EAL options] -- -p PORTMASK [-q NQ]\n"
305af75078fSIntel " -p PORTMASK: hexadecimal bitmask of ports to configure\n"
306af75078fSIntel " -q NQ: number of queue (=ports) per lcore (default is 1)\n"
307af75078fSIntel " -T PERIOD: statistics will be refreshed each PERIOD seconds (0 to disable, 10 default, 86400 maximum)\n",
308af75078fSIntel prgname);
309af75078fSIntel }
310af75078fSIntel
311af75078fSIntel static int
lsi_parse_portmask(const char * portmask)312af75078fSIntel lsi_parse_portmask(const char *portmask)
313af75078fSIntel {
314af75078fSIntel char *end = NULL;
315af75078fSIntel unsigned long pm;
316af75078fSIntel
317af75078fSIntel /* parse hexadecimal string */
318af75078fSIntel pm = strtoul(portmask, &end, 16);
319af75078fSIntel if ((portmask[0] == '\0') || (end == NULL) || (*end != '\0'))
320ce6b8c31SSarosh Arif return 0;
321af75078fSIntel
322af75078fSIntel return pm;
323af75078fSIntel }
324af75078fSIntel
325af75078fSIntel static unsigned int
lsi_parse_nqueue(const char * q_arg)326af75078fSIntel lsi_parse_nqueue(const char *q_arg)
327af75078fSIntel {
328af75078fSIntel char *end = NULL;
329af75078fSIntel unsigned long n;
330af75078fSIntel
331af75078fSIntel /* parse hexadecimal string */
332af75078fSIntel n = strtoul(q_arg, &end, 10);
333af75078fSIntel if ((q_arg[0] == '\0') || (end == NULL) || (*end != '\0'))
334af75078fSIntel return 0;
335af75078fSIntel if (n == 0)
336af75078fSIntel return 0;
337af75078fSIntel if (n >= MAX_RX_QUEUE_PER_LCORE)
338af75078fSIntel return 0;
339af75078fSIntel
340af75078fSIntel return n;
341af75078fSIntel }
342af75078fSIntel
343af75078fSIntel static int
lsi_parse_timer_period(const char * q_arg)344af75078fSIntel lsi_parse_timer_period(const char *q_arg)
345af75078fSIntel {
346af75078fSIntel char *end = NULL;
347af75078fSIntel int n;
348af75078fSIntel
349af75078fSIntel /* parse number string */
350af75078fSIntel n = strtol(q_arg, &end, 10);
351af75078fSIntel if ((q_arg[0] == '\0') || (end == NULL) || (*end != '\0'))
352af75078fSIntel return -1;
353af75078fSIntel if (n >= MAX_TIMER_PERIOD)
354af75078fSIntel return -1;
355af75078fSIntel
356af75078fSIntel return n;
357af75078fSIntel }
358af75078fSIntel
359af75078fSIntel /* Parse the argument given in the command line of the application */
360af75078fSIntel static int
lsi_parse_args(int argc,char ** argv)361af75078fSIntel lsi_parse_args(int argc, char **argv)
362af75078fSIntel {
363af75078fSIntel int opt, ret;
364af75078fSIntel char **argvopt;
365af75078fSIntel int option_index;
366af75078fSIntel char *prgname = argv[0];
367af75078fSIntel static struct option lgopts[] = {
368af75078fSIntel {NULL, 0, 0, 0}
369af75078fSIntel };
370af75078fSIntel
37114d460b8SRaja Zidane timer_period = DEFAULT_TIMER_PERIOD * TIMER_MILLISECOND * 1000;
37214d460b8SRaja Zidane
373af75078fSIntel argvopt = argv;
374af75078fSIntel
375af75078fSIntel while ((opt = getopt_long(argc, argvopt, "p:q:T:",
376af75078fSIntel lgopts, &option_index)) != EOF) {
377af75078fSIntel
378af75078fSIntel switch (opt) {
379af75078fSIntel /* portmask */
380af75078fSIntel case 'p':
381af75078fSIntel lsi_enabled_port_mask = lsi_parse_portmask(optarg);
382af75078fSIntel if (lsi_enabled_port_mask == 0) {
383af75078fSIntel printf("invalid portmask\n");
384af75078fSIntel lsi_usage(prgname);
385af75078fSIntel return -1;
386af75078fSIntel }
387af75078fSIntel break;
388af75078fSIntel
389af75078fSIntel /* nqueue */
390af75078fSIntel case 'q':
391af75078fSIntel lsi_rx_queue_per_lcore = lsi_parse_nqueue(optarg);
392af75078fSIntel if (lsi_rx_queue_per_lcore == 0) {
393af75078fSIntel printf("invalid queue number\n");
394af75078fSIntel lsi_usage(prgname);
395af75078fSIntel return -1;
396af75078fSIntel }
397af75078fSIntel break;
398af75078fSIntel
399af75078fSIntel /* timer period */
400af75078fSIntel case 'T':
401af75078fSIntel timer_period = lsi_parse_timer_period(optarg) * 1000 * TIMER_MILLISECOND;
402af75078fSIntel if (timer_period < 0) {
403af75078fSIntel printf("invalid timer period\n");
404af75078fSIntel lsi_usage(prgname);
405af75078fSIntel return -1;
406af75078fSIntel }
407af75078fSIntel break;
408af75078fSIntel
409af75078fSIntel /* long options */
410af75078fSIntel case 0:
411af75078fSIntel lsi_usage(prgname);
412af75078fSIntel return -1;
413af75078fSIntel
414af75078fSIntel default:
415af75078fSIntel lsi_usage(prgname);
416af75078fSIntel return -1;
417af75078fSIntel }
418af75078fSIntel }
419af75078fSIntel
420af75078fSIntel if (optind >= 0)
421af75078fSIntel argv[optind-1] = prgname;
422af75078fSIntel
423af75078fSIntel ret = optind-1;
4249d5ca532SKeith Wiles optind = 1; /* reset getopt lib */
425af75078fSIntel return ret;
426af75078fSIntel }
427af75078fSIntel
428af75078fSIntel /**
429af75078fSIntel * It will be called as the callback for specified port after a LSI interrupt
430af75078fSIntel * has been fully handled. This callback needs to be implemented carefully as
431af75078fSIntel * it will be called in the interrupt host thread which is different from the
432af75078fSIntel * application main thread.
433af75078fSIntel *
434af75078fSIntel * @param port_id
435af75078fSIntel * Port id.
436af75078fSIntel * @param type
437af75078fSIntel * event type.
438af75078fSIntel * @param param
439af75078fSIntel * Pointer to(address of) the parameters.
440af75078fSIntel *
441af75078fSIntel * @return
442d6af1a13SBernard Iremonger * int.
443af75078fSIntel */
4449a212dc0SConor Fogarty
4459a212dc0SConor Fogarty /* lsi_event_callback 8< */
446d6af1a13SBernard Iremonger static int
lsi_event_callback(uint16_t port_id,enum rte_eth_event_type type,void * param,void * ret_param)447f8244c63SZhiyong Yang lsi_event_callback(uint16_t port_id, enum rte_eth_event_type type, void *param,
448d6af1a13SBernard Iremonger void *ret_param)
449af75078fSIntel {
450af75078fSIntel struct rte_eth_link link;
45122e5c73bSIgor Romanov int ret;
452db4e8135SIvan Dyukov char link_status_text[RTE_ETH_LINK_MAX_STR_LEN];
453af75078fSIntel
454af75078fSIntel RTE_SET_USED(param);
455d6af1a13SBernard Iremonger RTE_SET_USED(ret_param);
456af75078fSIntel
457af75078fSIntel printf("\n\nIn registered callback...\n");
458af75078fSIntel printf("Event type: %s\n", type == RTE_ETH_EVENT_INTR_LSC ? "LSC interrupt" : "unknown event");
45922e5c73bSIgor Romanov ret = rte_eth_link_get_nowait(port_id, &link);
46022e5c73bSIgor Romanov if (ret < 0) {
46122e5c73bSIgor Romanov printf("Failed link get on port %d: %s\n",
46222e5c73bSIgor Romanov port_id, rte_strerror(-ret));
46322e5c73bSIgor Romanov return ret;
46422e5c73bSIgor Romanov }
465db4e8135SIvan Dyukov rte_eth_link_to_str(link_status_text, sizeof(link_status_text), &link);
466db4e8135SIvan Dyukov printf("Port %d %s\n\n", port_id, link_status_text);
467d6af1a13SBernard Iremonger
468d6af1a13SBernard Iremonger return 0;
469af75078fSIntel }
4709a212dc0SConor Fogarty /* >8 End of registering one or more callbacks. */
471af75078fSIntel
472d3641ae8SIntel /* Check the link status of all ports in up to 9s, and print them finally */
473d3641ae8SIntel static void
check_all_ports_link_status(uint16_t port_num,uint32_t port_mask)47447523597SZhiyong Yang check_all_ports_link_status(uint16_t port_num, uint32_t port_mask)
475d3641ae8SIntel {
476d3641ae8SIntel #define CHECK_INTERVAL 100 /* 100ms */
477d3641ae8SIntel #define MAX_CHECK_TIME 90 /* 9s (90 * 100ms) in total */
478f8244c63SZhiyong Yang uint8_t count, all_ports_up, print_flag = 0;
479f8244c63SZhiyong Yang uint16_t portid;
480d3641ae8SIntel struct rte_eth_link link;
48122e5c73bSIgor Romanov int ret;
482db4e8135SIvan Dyukov char link_status_text[RTE_ETH_LINK_MAX_STR_LEN];
483d3641ae8SIntel
484d3641ae8SIntel printf("\nChecking link status");
485d3641ae8SIntel fflush(stdout);
486d3641ae8SIntel for (count = 0; count <= MAX_CHECK_TIME; count++) {
487d3641ae8SIntel all_ports_up = 1;
488d3641ae8SIntel for (portid = 0; portid < port_num; portid++) {
489d3641ae8SIntel if ((port_mask & (1 << portid)) == 0)
490d3641ae8SIntel continue;
491d3641ae8SIntel memset(&link, 0, sizeof(link));
49222e5c73bSIgor Romanov ret = rte_eth_link_get_nowait(portid, &link);
49322e5c73bSIgor Romanov if (ret < 0) {
49422e5c73bSIgor Romanov all_ports_up = 0;
49522e5c73bSIgor Romanov if (print_flag == 1)
49622e5c73bSIgor Romanov printf("Port %u link get failed: %s\n",
49722e5c73bSIgor Romanov portid, rte_strerror(-ret));
49822e5c73bSIgor Romanov continue;
49922e5c73bSIgor Romanov }
500d3641ae8SIntel /* print link status if flag set */
501d3641ae8SIntel if (print_flag == 1) {
502db4e8135SIvan Dyukov rte_eth_link_to_str(link_status_text,
503db4e8135SIvan Dyukov sizeof(link_status_text), &link);
504db4e8135SIvan Dyukov printf("Port %d %s", portid,
505db4e8135SIvan Dyukov link_status_text);
506d3641ae8SIntel continue;
507d3641ae8SIntel }
508d3641ae8SIntel /* clear all_ports_up flag if any link down */
509295968d1SFerruh Yigit if (link.link_status == RTE_ETH_LINK_DOWN) {
510d3641ae8SIntel all_ports_up = 0;
511d3641ae8SIntel break;
512d3641ae8SIntel }
513d3641ae8SIntel }
514d3641ae8SIntel /* after finally printing all link status, get out */
515d3641ae8SIntel if (print_flag == 1)
516d3641ae8SIntel break;
517d3641ae8SIntel
518d3641ae8SIntel if (all_ports_up == 0) {
519d3641ae8SIntel printf(".");
520d3641ae8SIntel fflush(stdout);
521d3641ae8SIntel rte_delay_ms(CHECK_INTERVAL);
522d3641ae8SIntel }
523d3641ae8SIntel
524d3641ae8SIntel /* set the print_flag if all ports up or timeout */
525d3641ae8SIntel if (all_ports_up == 1 || count == (MAX_CHECK_TIME - 1)) {
526d3641ae8SIntel print_flag = 1;
527d3641ae8SIntel printf("done\n");
528d3641ae8SIntel }
529d3641ae8SIntel }
530d3641ae8SIntel }
531d3641ae8SIntel
532af75078fSIntel int
main(int argc,char ** argv)53398a16481SDavid Marchand main(int argc, char **argv)
534af75078fSIntel {
535af75078fSIntel struct lcore_queue_conf *qconf;
536af75078fSIntel int ret;
53747523597SZhiyong Yang uint16_t nb_ports;
53847523597SZhiyong Yang uint16_t portid, portid_last = 0;
539af75078fSIntel unsigned lcore_id, rx_lcore_id;
540af75078fSIntel unsigned nb_ports_in_mask = 0;
541af75078fSIntel
542af75078fSIntel /* init EAL */
543af75078fSIntel ret = rte_eal_init(argc, argv);
544af75078fSIntel if (ret < 0)
545af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eal_init failed");
546af75078fSIntel argc -= ret;
547af75078fSIntel argv += ret;
548af75078fSIntel
549af75078fSIntel /* parse application arguments (after the EAL ones) */
550af75078fSIntel ret = lsi_parse_args(argc, argv);
551af75078fSIntel if (ret < 0)
552af75078fSIntel rte_exit(EXIT_FAILURE, "Invalid arguments");
553af75078fSIntel
554af75078fSIntel /* create the mbuf pool */
555af75078fSIntel lsi_pktmbuf_pool =
556ea0c20eaSOlivier Matz rte_pktmbuf_pool_create("mbuf_pool", NB_MBUF, 32, 0,
557824cb29cSKonstantin Ananyev RTE_MBUF_DEFAULT_BUF_SIZE, rte_socket_id());
558af75078fSIntel if (lsi_pktmbuf_pool == NULL)
559af75078fSIntel rte_panic("Cannot init mbuf pool\n");
560af75078fSIntel
561d9a42a69SThomas Monjalon nb_ports = rte_eth_dev_count_avail();
562af75078fSIntel if (nb_ports == 0)
563af75078fSIntel rte_panic("No Ethernet port - bye\n");
564af75078fSIntel
5659a212dc0SConor Fogarty /* Each logical core is assigned a dedicated TX queue on each port. 8< */
566af75078fSIntel for (portid = 0; portid < nb_ports; portid++) {
567af75078fSIntel /* skip ports that are not enabled */
568af75078fSIntel if ((lsi_enabled_port_mask & (1 << portid)) == 0)
569af75078fSIntel continue;
570af75078fSIntel
571af75078fSIntel /* save the destination port id */
572af75078fSIntel if (nb_ports_in_mask % 2) {
573af75078fSIntel lsi_dst_ports[portid] = portid_last;
574af75078fSIntel lsi_dst_ports[portid_last] = portid;
575af75078fSIntel }
576af75078fSIntel else
577af75078fSIntel portid_last = portid;
578af75078fSIntel
579af75078fSIntel nb_ports_in_mask++;
580af75078fSIntel }
5819a212dc0SConor Fogarty /* >8 End of assigning logical core. */
582af75078fSIntel if (nb_ports_in_mask < 2 || nb_ports_in_mask % 2)
583af75078fSIntel rte_exit(EXIT_FAILURE, "Current enabled port number is %u, "
584af75078fSIntel "but it should be even and at least 2\n",
585af75078fSIntel nb_ports_in_mask);
586af75078fSIntel
587af75078fSIntel rx_lcore_id = 0;
588af75078fSIntel qconf = &lcore_queue_conf[rx_lcore_id];
589af75078fSIntel
590af75078fSIntel /* Initialize the port/queue configuration of each logical core */
591af75078fSIntel for (portid = 0; portid < nb_ports; portid++) {
592af75078fSIntel /* skip ports that are not enabled */
593af75078fSIntel if ((lsi_enabled_port_mask & (1 << portid)) == 0)
594af75078fSIntel continue;
595af75078fSIntel
596af75078fSIntel /* get the lcore_id for this port */
597af75078fSIntel while (rte_lcore_is_enabled(rx_lcore_id) == 0 ||
5980c3d715cSIntel lcore_queue_conf[rx_lcore_id].n_rx_port ==
599af75078fSIntel lsi_rx_queue_per_lcore) {
600af75078fSIntel
601af75078fSIntel rx_lcore_id++;
602af75078fSIntel if (rx_lcore_id >= RTE_MAX_LCORE)
603af75078fSIntel rte_exit(EXIT_FAILURE, "Not enough cores\n");
604af75078fSIntel }
6050c3d715cSIntel if (qconf != &lcore_queue_conf[rx_lcore_id])
606af75078fSIntel /* Assigned a new logical core in the loop above. */
607af75078fSIntel qconf = &lcore_queue_conf[rx_lcore_id];
6080c3d715cSIntel
6090c3d715cSIntel qconf->rx_port_list[qconf->n_rx_port] = portid;
6100c3d715cSIntel qconf->n_rx_port++;
611a974564bSIntel printf("Lcore %u: RX port %u\n",rx_lcore_id, (unsigned) portid);
612af75078fSIntel }
613af75078fSIntel
614af75078fSIntel /* Initialise each port */
615af75078fSIntel for (portid = 0; portid < nb_ports; portid++) {
616312967c3SShahaf Shuler struct rte_eth_rxconf rxq_conf;
617312967c3SShahaf Shuler struct rte_eth_txconf txq_conf;
618312967c3SShahaf Shuler struct rte_eth_conf local_port_conf = port_conf;
619312967c3SShahaf Shuler struct rte_eth_dev_info dev_info;
620312967c3SShahaf Shuler
621af75078fSIntel /* skip ports that are not enabled */
622af75078fSIntel if ((lsi_enabled_port_mask & (1 << portid)) == 0) {
623a974564bSIntel printf("Skipping disabled port %u\n", (unsigned) portid);
624af75078fSIntel continue;
625af75078fSIntel }
626af75078fSIntel /* init port */
627a974564bSIntel printf("Initializing port %u... ", (unsigned) portid);
628af75078fSIntel fflush(stdout);
629089e5ed7SIvan Ilchenko
630089e5ed7SIvan Ilchenko ret = rte_eth_dev_info_get(portid, &dev_info);
631089e5ed7SIvan Ilchenko if (ret != 0)
632089e5ed7SIvan Ilchenko rte_exit(EXIT_FAILURE,
633089e5ed7SIvan Ilchenko "Error during getting device (port %u) info: %s\n",
634089e5ed7SIvan Ilchenko portid, strerror(-ret));
635089e5ed7SIvan Ilchenko
636295968d1SFerruh Yigit if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)
637312967c3SShahaf Shuler local_port_conf.txmode.offloads |=
638295968d1SFerruh Yigit RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
6399a212dc0SConor Fogarty /* Configure RX and TX queues. 8< */
640312967c3SShahaf Shuler ret = rte_eth_dev_configure(portid, 1, 1, &local_port_conf);
641af75078fSIntel if (ret < 0)
642af75078fSIntel rte_exit(EXIT_FAILURE, "Cannot configure device: err=%d, port=%u\n",
643a974564bSIntel ret, (unsigned) portid);
6449a212dc0SConor Fogarty /* >8 End of configure RX and TX queues. */
645af75078fSIntel
64660efb44fSRoman Zhukov ret = rte_eth_dev_adjust_nb_rx_tx_desc(portid, &nb_rxd,
64760efb44fSRoman Zhukov &nb_txd);
64860efb44fSRoman Zhukov if (ret < 0)
64960efb44fSRoman Zhukov rte_exit(EXIT_FAILURE,
65060efb44fSRoman Zhukov "rte_eth_dev_adjust_nb_rx_tx_desc: err=%d, port=%u\n",
65160efb44fSRoman Zhukov ret, (unsigned) portid);
65260efb44fSRoman Zhukov
653af75078fSIntel /* register lsi interrupt callback, need to be after
654af75078fSIntel * rte_eth_dev_configure(). if (intr_conf.lsc == 0), no
655af75078fSIntel * lsc interrupt will be present, and below callback to
656af75078fSIntel * be registered will never be called.
657af75078fSIntel */
6589a212dc0SConor Fogarty
6599a212dc0SConor Fogarty /* RTE callback register. 8< */
660a974564bSIntel rte_eth_dev_callback_register(portid,
661af75078fSIntel RTE_ETH_EVENT_INTR_LSC, lsi_event_callback, NULL);
6629a212dc0SConor Fogarty /* >8 End of registering lsi interrupt callback. */
663af75078fSIntel
66470febdcfSIgor Romanov ret = rte_eth_macaddr_get(portid,
665af75078fSIntel &lsi_ports_eth_addr[portid]);
66670febdcfSIgor Romanov if (ret < 0)
66770febdcfSIgor Romanov rte_exit(EXIT_FAILURE,
66870febdcfSIgor Romanov "rte_eth_macaddr_get: err=%d, port=%u\n",
66970febdcfSIgor Romanov ret, (unsigned int)portid);
670af75078fSIntel
671af75078fSIntel /* init one RX queue */
672af75078fSIntel fflush(stdout);
673312967c3SShahaf Shuler rxq_conf = dev_info.default_rxconf;
674312967c3SShahaf Shuler rxq_conf.offloads = local_port_conf.rxmode.offloads;
6759a212dc0SConor Fogarty /* RX queue initialization. 8< */
676a974564bSIntel ret = rte_eth_rx_queue_setup(portid, 0, nb_rxd,
67781f7ecd9SPablo de Lara rte_eth_dev_socket_id(portid),
678312967c3SShahaf Shuler &rxq_conf,
679af75078fSIntel lsi_pktmbuf_pool);
680af75078fSIntel if (ret < 0)
681a974564bSIntel rte_exit(EXIT_FAILURE, "rte_eth_rx_queue_setup: err=%d, port=%u\n",
682a974564bSIntel ret, (unsigned) portid);
6839a212dc0SConor Fogarty /* >8 End of RX queue initialization. */
684af75078fSIntel
6859a212dc0SConor Fogarty /* init one TX queue logical core on each port. 8< */
686af75078fSIntel fflush(stdout);
687312967c3SShahaf Shuler txq_conf = dev_info.default_txconf;
688312967c3SShahaf Shuler txq_conf.offloads = local_port_conf.txmode.offloads;
689a974564bSIntel ret = rte_eth_tx_queue_setup(portid, 0, nb_txd,
69081f7ecd9SPablo de Lara rte_eth_dev_socket_id(portid),
691312967c3SShahaf Shuler &txq_conf);
692af75078fSIntel if (ret < 0)
6930c3d715cSIntel rte_exit(EXIT_FAILURE, "rte_eth_tx_queue_setup: err=%d,port=%u\n",
694a974564bSIntel ret, (unsigned) portid);
6959a212dc0SConor Fogarty /* >8 End of init one TX queue. */
696af75078fSIntel
697e2366e74STomasz Kulasek /* Initialize TX buffers */
698e2366e74STomasz Kulasek tx_buffer[portid] = rte_zmalloc_socket("tx_buffer",
699e2366e74STomasz Kulasek RTE_ETH_TX_BUFFER_SIZE(MAX_PKT_BURST), 0,
700e2366e74STomasz Kulasek rte_eth_dev_socket_id(portid));
701e2366e74STomasz Kulasek if (tx_buffer[portid] == NULL)
702e2366e74STomasz Kulasek rte_exit(EXIT_FAILURE, "Cannot allocate buffer for tx on port %u\n",
703e2366e74STomasz Kulasek (unsigned) portid);
704e2366e74STomasz Kulasek
705e2366e74STomasz Kulasek rte_eth_tx_buffer_init(tx_buffer[portid], MAX_PKT_BURST);
706e2366e74STomasz Kulasek
707e2366e74STomasz Kulasek ret = rte_eth_tx_buffer_set_err_callback(tx_buffer[portid],
708e2366e74STomasz Kulasek rte_eth_tx_buffer_count_callback,
709e2366e74STomasz Kulasek &port_statistics[portid].dropped);
710e2366e74STomasz Kulasek if (ret < 0)
711e2366e74STomasz Kulasek rte_exit(EXIT_FAILURE, "Cannot set error callback for "
712e2366e74STomasz Kulasek "tx buffer on port %u\n", (unsigned) portid);
713e2366e74STomasz Kulasek
714af75078fSIntel /* Start device */
715a974564bSIntel ret = rte_eth_dev_start(portid);
716af75078fSIntel if (ret < 0)
717af75078fSIntel rte_exit(EXIT_FAILURE, "rte_eth_dev_start: err=%d, port=%u\n",
718a974564bSIntel ret, (unsigned) portid);
719d3641ae8SIntel printf("done:\n");
720af75078fSIntel
721f430bbceSIvan Ilchenko ret = rte_eth_promiscuous_enable(portid);
722f430bbceSIvan Ilchenko if (ret != 0)
723f430bbceSIvan Ilchenko rte_exit(EXIT_FAILURE,
724f430bbceSIvan Ilchenko "rte_eth_promiscuous_enable: err=%s, port=%u\n",
725f430bbceSIvan Ilchenko rte_strerror(-ret), portid);
726e2366e74STomasz Kulasek
727c2c4f87bSAman Deep Singh printf("Port %u, MAC address: " RTE_ETHER_ADDR_PRT_FMT "\n\n",
728a974564bSIntel (unsigned) portid,
729a7db3afcSAman Deep Singh RTE_ETHER_ADDR_BYTES(&lsi_ports_eth_addr[portid]));
730af75078fSIntel
731af75078fSIntel /* initialize port stats */
732af75078fSIntel memset(&port_statistics, 0, sizeof(port_statistics));
733af75078fSIntel }
734af75078fSIntel
735a974564bSIntel check_all_ports_link_status(nb_ports, lsi_enabled_port_mask);
736d3641ae8SIntel
737af75078fSIntel /* launch per-lcore init on every lcore */
738cb056611SStephen Hemminger rte_eal_mp_remote_launch(lsi_launch_one_lcore, NULL, CALL_MAIN);
739cb056611SStephen Hemminger RTE_LCORE_FOREACH_WORKER(lcore_id) {
740af75078fSIntel if (rte_eal_wait_lcore(lcore_id) < 0)
741af75078fSIntel return -1;
742af75078fSIntel }
743af75078fSIntel
74410aa3757SChengchang Tang /* clean up the EAL */
74510aa3757SChengchang Tang rte_eal_cleanup();
74610aa3757SChengchang Tang
747af75078fSIntel return 0;
748af75078fSIntel }
749