1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2016-2017 Intel Corporation 3 */ 4 5 #include <getopt.h> 6 #include <stdint.h> 7 #include <stdio.h> 8 #include <signal.h> 9 #include <sched.h> 10 11 #include "pipeline_common.h" 12 13 struct config_data cdata = { 14 .num_packets = (1L << 25), /* do ~32M packets */ 15 .num_fids = 512, 16 .queue_type = RTE_SCHED_TYPE_ATOMIC, 17 .next_qid = {-1}, 18 .qid = {-1}, 19 .num_stages = 1, 20 .worker_cq_depth = 16 21 }; 22 23 static bool 24 core_in_use(unsigned int lcore_id) { 25 return (fdata->rx_core[lcore_id] || fdata->sched_core[lcore_id] || 26 fdata->tx_core[lcore_id] || fdata->worker_core[lcore_id]); 27 } 28 29 /* 30 * Parse the coremask given as argument (hexadecimal string) and fill 31 * the global configuration (core role and core count) with the parsed 32 * value. 33 */ 34 static int xdigit2val(unsigned char c) 35 { 36 int val; 37 38 if (isdigit(c)) 39 val = c - '0'; 40 else if (isupper(c)) 41 val = c - 'A' + 10; 42 else 43 val = c - 'a' + 10; 44 return val; 45 } 46 47 static uint64_t 48 parse_coremask(const char *coremask) 49 { 50 int i, j, idx = 0; 51 unsigned int count = 0; 52 char c; 53 int val; 54 uint64_t mask = 0; 55 const int32_t BITS_HEX = 4; 56 57 if (coremask == NULL) 58 return -1; 59 /* Remove all blank characters ahead and after . 60 * Remove 0x/0X if exists. 61 */ 62 while (isblank(*coremask)) 63 coremask++; 64 if (coremask[0] == '0' && ((coremask[1] == 'x') 65 || (coremask[1] == 'X'))) 66 coremask += 2; 67 i = strlen(coremask); 68 while ((i > 0) && isblank(coremask[i - 1])) 69 i--; 70 if (i == 0) 71 return -1; 72 73 for (i = i - 1; i >= 0 && idx < MAX_NUM_CORE; i--) { 74 c = coremask[i]; 75 if (isxdigit(c) == 0) { 76 /* invalid characters */ 77 return -1; 78 } 79 val = xdigit2val(c); 80 for (j = 0; j < BITS_HEX && idx < MAX_NUM_CORE; j++, idx++) { 81 if ((1 << j) & val) { 82 mask |= (1UL << idx); 83 count++; 84 } 85 } 86 } 87 for (; i >= 0; i--) 88 if (coremask[i] != '0') 89 return -1; 90 if (count == 0) 91 return -1; 92 return mask; 93 } 94 95 static struct option long_options[] = { 96 {"workers", required_argument, 0, 'w'}, 97 {"packets", required_argument, 0, 'n'}, 98 {"atomic-flows", required_argument, 0, 'f'}, 99 {"num_stages", required_argument, 0, 's'}, 100 {"rx-mask", required_argument, 0, 'r'}, 101 {"tx-mask", required_argument, 0, 't'}, 102 {"sched-mask", required_argument, 0, 'e'}, 103 {"cq-depth", required_argument, 0, 'c'}, 104 {"work-cycles", required_argument, 0, 'W'}, 105 {"mempool-size", required_argument, 0, 'm'}, 106 {"queue-priority", no_argument, 0, 'P'}, 107 {"parallel", no_argument, 0, 'p'}, 108 {"ordered", no_argument, 0, 'o'}, 109 {"quiet", no_argument, 0, 'q'}, 110 {"use-atq", no_argument, 0, 'a'}, 111 {"dump", no_argument, 0, 'D'}, 112 {0, 0, 0, 0} 113 }; 114 115 static void 116 usage(void) 117 { 118 const char *usage_str = 119 " Usage: eventdev_demo [options]\n" 120 " Options:\n" 121 " -n, --packets=N Send N packets (default ~32M), 0 implies no limit\n" 122 " -f, --atomic-flows=N Use N random flows from 1 to N (default 16)\n" 123 " -s, --num_stages=N Use N atomic stages (default 1)\n" 124 " -r, --rx-mask=core mask Run NIC rx on CPUs in core mask\n" 125 " -w, --worker-mask=core mask Run worker on CPUs in core mask\n" 126 " -t, --tx-mask=core mask Run NIC tx on CPUs in core mask\n" 127 " -e --sched-mask=core mask Run scheduler on CPUs in core mask\n" 128 " -c --cq-depth=N Worker CQ depth (default 16)\n" 129 " -W --work-cycles=N Worker cycles (default 0)\n" 130 " -P --queue-priority Enable scheduler queue prioritization\n" 131 " -o, --ordered Use ordered scheduling\n" 132 " -p, --parallel Use parallel scheduling\n" 133 " -q, --quiet Minimize printed output\n" 134 " -a, --use-atq Use all type queues\n" 135 " -m, --mempool-size=N Dictate the mempool size\n" 136 " -D, --dump Print detailed statistics before exit" 137 "\n"; 138 fprintf(stderr, "%s", usage_str); 139 exit(1); 140 } 141 142 static void 143 parse_app_args(int argc, char **argv) 144 { 145 /* Parse cli options*/ 146 int option_index; 147 int c; 148 opterr = 0; 149 uint64_t rx_lcore_mask = 0; 150 uint64_t tx_lcore_mask = 0; 151 uint64_t sched_lcore_mask = 0; 152 uint64_t worker_lcore_mask = 0; 153 int i; 154 155 for (;;) { 156 c = getopt_long(argc, argv, "r:t:e:c:w:n:f:s:m:paoPqDW:", 157 long_options, &option_index); 158 if (c == -1) 159 break; 160 161 int popcnt = 0; 162 switch (c) { 163 case 'n': 164 cdata.num_packets = (int64_t)atol(optarg); 165 if (cdata.num_packets == 0) 166 cdata.num_packets = INT64_MAX; 167 break; 168 case 'f': 169 cdata.num_fids = (unsigned int)atoi(optarg); 170 break; 171 case 's': 172 cdata.num_stages = (unsigned int)atoi(optarg); 173 break; 174 case 'c': 175 cdata.worker_cq_depth = (unsigned int)atoi(optarg); 176 break; 177 case 'W': 178 cdata.worker_cycles = (unsigned int)atoi(optarg); 179 break; 180 case 'P': 181 cdata.enable_queue_priorities = 1; 182 break; 183 case 'o': 184 cdata.queue_type = RTE_SCHED_TYPE_ORDERED; 185 break; 186 case 'p': 187 cdata.queue_type = RTE_SCHED_TYPE_PARALLEL; 188 break; 189 case 'a': 190 cdata.all_type_queues = 1; 191 break; 192 case 'q': 193 cdata.quiet = 1; 194 break; 195 case 'D': 196 cdata.dump_dev = 1; 197 break; 198 case 'w': 199 worker_lcore_mask = parse_coremask(optarg); 200 break; 201 case 'r': 202 rx_lcore_mask = parse_coremask(optarg); 203 popcnt = __builtin_popcountll(rx_lcore_mask); 204 fdata->rx_single = (popcnt == 1); 205 break; 206 case 't': 207 tx_lcore_mask = parse_coremask(optarg); 208 popcnt = __builtin_popcountll(tx_lcore_mask); 209 fdata->tx_single = (popcnt == 1); 210 break; 211 case 'e': 212 sched_lcore_mask = parse_coremask(optarg); 213 popcnt = __builtin_popcountll(sched_lcore_mask); 214 fdata->sched_single = (popcnt == 1); 215 break; 216 case 'm': 217 cdata.num_mbuf = (uint64_t)atol(optarg); 218 break; 219 default: 220 usage(); 221 } 222 } 223 224 cdata.worker_lcore_mask = worker_lcore_mask; 225 cdata.sched_lcore_mask = sched_lcore_mask; 226 cdata.rx_lcore_mask = rx_lcore_mask; 227 cdata.tx_lcore_mask = tx_lcore_mask; 228 229 if (cdata.num_stages == 0 || cdata.num_stages > MAX_NUM_STAGES) 230 usage(); 231 232 for (i = 0; i < MAX_NUM_CORE; i++) { 233 fdata->rx_core[i] = !!(rx_lcore_mask & (1UL << i)); 234 fdata->tx_core[i] = !!(tx_lcore_mask & (1UL << i)); 235 fdata->sched_core[i] = !!(sched_lcore_mask & (1UL << i)); 236 fdata->worker_core[i] = !!(worker_lcore_mask & (1UL << i)); 237 238 if (fdata->worker_core[i]) 239 cdata.num_workers++; 240 if (core_in_use(i)) 241 cdata.active_cores++; 242 } 243 } 244 245 /* 246 * Initializes a given port using global settings and with the RX buffers 247 * coming from the mbuf_pool passed as a parameter. 248 */ 249 static inline int 250 port_init(uint8_t port, struct rte_mempool *mbuf_pool) 251 { 252 struct rte_eth_rxconf rx_conf; 253 static const struct rte_eth_conf port_conf_default = { 254 .rxmode = { 255 .mq_mode = ETH_MQ_RX_RSS, 256 .max_rx_pkt_len = RTE_ETHER_MAX_LEN, 257 }, 258 .rx_adv_conf = { 259 .rss_conf = { 260 .rss_hf = ETH_RSS_IP | 261 ETH_RSS_TCP | 262 ETH_RSS_UDP, 263 } 264 } 265 }; 266 const uint16_t rx_rings = 1, tx_rings = 1; 267 const uint16_t rx_ring_size = 512, tx_ring_size = 512; 268 struct rte_eth_conf port_conf = port_conf_default; 269 int retval; 270 uint16_t q; 271 struct rte_eth_dev_info dev_info; 272 struct rte_eth_txconf txconf; 273 274 if (!rte_eth_dev_is_valid_port(port)) 275 return -1; 276 277 retval = rte_eth_dev_info_get(port, &dev_info); 278 if (retval != 0) { 279 printf("Error during getting device (port %u) info: %s\n", 280 port, strerror(-retval)); 281 return retval; 282 } 283 284 if (dev_info.tx_offload_capa & DEV_TX_OFFLOAD_MBUF_FAST_FREE) 285 port_conf.txmode.offloads |= 286 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 287 rx_conf = dev_info.default_rxconf; 288 rx_conf.offloads = port_conf.rxmode.offloads; 289 290 port_conf.rx_adv_conf.rss_conf.rss_hf &= 291 dev_info.flow_type_rss_offloads; 292 if (port_conf.rx_adv_conf.rss_conf.rss_hf != 293 port_conf_default.rx_adv_conf.rss_conf.rss_hf) { 294 printf("Port %u modified RSS hash function based on hardware support," 295 "requested:%#"PRIx64" configured:%#"PRIx64"\n", 296 port, 297 port_conf_default.rx_adv_conf.rss_conf.rss_hf, 298 port_conf.rx_adv_conf.rss_conf.rss_hf); 299 } 300 301 /* Configure the Ethernet device. */ 302 retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf); 303 if (retval != 0) 304 return retval; 305 306 /* Allocate and set up 1 RX queue per Ethernet port. */ 307 for (q = 0; q < rx_rings; q++) { 308 retval = rte_eth_rx_queue_setup(port, q, rx_ring_size, 309 rte_eth_dev_socket_id(port), &rx_conf, 310 mbuf_pool); 311 if (retval < 0) 312 return retval; 313 } 314 315 txconf = dev_info.default_txconf; 316 txconf.offloads = port_conf_default.txmode.offloads; 317 /* Allocate and set up 1 TX queue per Ethernet port. */ 318 for (q = 0; q < tx_rings; q++) { 319 retval = rte_eth_tx_queue_setup(port, q, tx_ring_size, 320 rte_eth_dev_socket_id(port), &txconf); 321 if (retval < 0) 322 return retval; 323 } 324 325 /* Display the port MAC address. */ 326 struct rte_ether_addr addr; 327 rte_eth_macaddr_get(port, &addr); 328 printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8 329 " %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n", 330 (unsigned int)port, 331 addr.addr_bytes[0], addr.addr_bytes[1], 332 addr.addr_bytes[2], addr.addr_bytes[3], 333 addr.addr_bytes[4], addr.addr_bytes[5]); 334 335 /* Enable RX in promiscuous mode for the Ethernet device. */ 336 rte_eth_promiscuous_enable(port); 337 338 return 0; 339 } 340 341 static int 342 init_ports(uint16_t num_ports) 343 { 344 uint16_t portid; 345 346 if (!cdata.num_mbuf) 347 cdata.num_mbuf = 16384 * num_ports; 348 349 struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool", 350 /* mbufs */ cdata.num_mbuf, 351 /* cache_size */ 512, 352 /* priv_size*/ 0, 353 /* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE, 354 rte_socket_id()); 355 356 RTE_ETH_FOREACH_DEV(portid) 357 if (port_init(portid, mp) != 0) 358 rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu16 "\n", 359 portid); 360 361 return 0; 362 } 363 364 static void 365 do_capability_setup(uint8_t eventdev_id) 366 { 367 int ret; 368 uint16_t i; 369 uint8_t generic_pipeline = 0; 370 uint8_t burst = 0; 371 372 RTE_ETH_FOREACH_DEV(i) { 373 uint32_t caps = 0; 374 375 ret = rte_event_eth_tx_adapter_caps_get(eventdev_id, i, &caps); 376 if (ret) 377 rte_exit(EXIT_FAILURE, 378 "Invalid capability for Tx adptr port %d\n", i); 379 generic_pipeline |= !(caps & 380 RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT); 381 } 382 383 struct rte_event_dev_info eventdev_info; 384 memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info)); 385 386 rte_event_dev_info_get(eventdev_id, &eventdev_info); 387 burst = eventdev_info.event_dev_cap & RTE_EVENT_DEV_CAP_BURST_MODE ? 1 : 388 0; 389 390 if (generic_pipeline) 391 set_worker_generic_setup_data(&fdata->cap, burst); 392 else 393 set_worker_tx_enq_setup_data(&fdata->cap, burst); 394 } 395 396 static void 397 signal_handler(int signum) 398 { 399 static uint8_t once; 400 uint16_t portid; 401 402 if (fdata->done) 403 rte_exit(1, "Exiting on signal %d\n", signum); 404 if ((signum == SIGINT || signum == SIGTERM) && !once) { 405 printf("\n\nSignal %d received, preparing to exit...\n", 406 signum); 407 if (cdata.dump_dev) 408 rte_event_dev_dump(0, stdout); 409 once = 1; 410 fdata->done = 1; 411 rte_smp_wmb(); 412 413 RTE_ETH_FOREACH_DEV(portid) { 414 rte_event_eth_rx_adapter_stop(portid); 415 rte_event_eth_tx_adapter_stop(portid); 416 rte_eth_dev_stop(portid); 417 } 418 419 rte_eal_mp_wait_lcore(); 420 421 RTE_ETH_FOREACH_DEV(portid) { 422 rte_eth_dev_close(portid); 423 } 424 425 rte_event_dev_stop(0); 426 rte_event_dev_close(0); 427 } 428 if (signum == SIGTSTP) 429 rte_event_dev_dump(0, stdout); 430 } 431 432 static inline uint64_t 433 port_stat(int dev_id, int32_t p) 434 { 435 char statname[64]; 436 snprintf(statname, sizeof(statname), "port_%u_rx", p); 437 return rte_event_dev_xstats_by_name_get(dev_id, statname, NULL); 438 } 439 440 int 441 main(int argc, char **argv) 442 { 443 struct worker_data *worker_data; 444 uint16_t num_ports; 445 uint16_t portid; 446 int lcore_id; 447 int err; 448 449 signal(SIGINT, signal_handler); 450 signal(SIGTERM, signal_handler); 451 signal(SIGTSTP, signal_handler); 452 453 err = rte_eal_init(argc, argv); 454 if (err < 0) 455 rte_panic("Invalid EAL arguments\n"); 456 457 argc -= err; 458 argv += err; 459 460 fdata = rte_malloc(NULL, sizeof(struct fastpath_data), 0); 461 if (fdata == NULL) 462 rte_panic("Out of memory\n"); 463 464 /* Parse cli options*/ 465 parse_app_args(argc, argv); 466 467 num_ports = rte_eth_dev_count_avail(); 468 if (num_ports == 0) 469 rte_panic("No ethernet ports found\n"); 470 471 const unsigned int cores_needed = cdata.active_cores; 472 473 if (!cdata.quiet) { 474 printf(" Config:\n"); 475 printf("\tports: %u\n", num_ports); 476 printf("\tworkers: %u\n", cdata.num_workers); 477 printf("\tpackets: %"PRIi64"\n", cdata.num_packets); 478 printf("\tQueue-prio: %u\n", cdata.enable_queue_priorities); 479 if (cdata.queue_type == RTE_SCHED_TYPE_ORDERED) 480 printf("\tqid0 type: ordered\n"); 481 if (cdata.queue_type == RTE_SCHED_TYPE_ATOMIC) 482 printf("\tqid0 type: atomic\n"); 483 printf("\tCores available: %u\n", rte_lcore_count()); 484 printf("\tCores used: %u\n", cores_needed); 485 } 486 487 if (rte_lcore_count() < cores_needed) 488 rte_panic("Too few cores (%d < %d)\n", rte_lcore_count(), 489 cores_needed); 490 491 const unsigned int ndevs = rte_event_dev_count(); 492 if (ndevs == 0) 493 rte_panic("No dev_id devs found. Pasl in a --vdev eventdev.\n"); 494 if (ndevs > 1) 495 fprintf(stderr, "Warning: More than one eventdev, using idx 0"); 496 497 498 do_capability_setup(0); 499 fdata->cap.check_opt(); 500 501 worker_data = rte_calloc(0, cdata.num_workers, 502 sizeof(worker_data[0]), 0); 503 if (worker_data == NULL) 504 rte_panic("rte_calloc failed\n"); 505 506 int dev_id = fdata->cap.evdev_setup(worker_data); 507 if (dev_id < 0) 508 rte_exit(EXIT_FAILURE, "Error setting up eventdev\n"); 509 510 init_ports(num_ports); 511 fdata->cap.adptr_setup(num_ports); 512 513 /* Start the Ethernet port. */ 514 RTE_ETH_FOREACH_DEV(portid) { 515 err = rte_eth_dev_start(portid); 516 if (err < 0) 517 rte_exit(EXIT_FAILURE, "Error starting ethdev %d\n", 518 portid); 519 } 520 521 int worker_idx = 0; 522 RTE_LCORE_FOREACH_SLAVE(lcore_id) { 523 if (lcore_id >= MAX_NUM_CORE) 524 break; 525 526 if (!fdata->rx_core[lcore_id] && 527 !fdata->worker_core[lcore_id] && 528 !fdata->tx_core[lcore_id] && 529 !fdata->sched_core[lcore_id]) 530 continue; 531 532 if (fdata->rx_core[lcore_id]) 533 printf( 534 "[%s()] lcore %d executing NIC Rx\n", 535 __func__, lcore_id); 536 537 if (fdata->tx_core[lcore_id]) 538 printf( 539 "[%s()] lcore %d executing NIC Tx\n", 540 __func__, lcore_id); 541 542 if (fdata->sched_core[lcore_id]) 543 printf("[%s()] lcore %d executing scheduler\n", 544 __func__, lcore_id); 545 546 if (fdata->worker_core[lcore_id]) 547 printf( 548 "[%s()] lcore %d executing worker, using eventdev port %u\n", 549 __func__, lcore_id, 550 worker_data[worker_idx].port_id); 551 552 err = rte_eal_remote_launch(fdata->cap.worker, 553 &worker_data[worker_idx], lcore_id); 554 if (err) { 555 rte_panic("Failed to launch worker on core %d\n", 556 lcore_id); 557 continue; 558 } 559 if (fdata->worker_core[lcore_id]) 560 worker_idx++; 561 } 562 563 lcore_id = rte_lcore_id(); 564 565 if (core_in_use(lcore_id)) 566 fdata->cap.worker(&worker_data[worker_idx++]); 567 568 rte_eal_mp_wait_lcore(); 569 570 if (!cdata.quiet && (port_stat(dev_id, worker_data[0].port_id) != 571 (uint64_t)-ENOTSUP)) { 572 printf("\nPort Workload distribution:\n"); 573 uint32_t i; 574 uint64_t tot_pkts = 0; 575 uint64_t pkts_per_wkr[RTE_MAX_LCORE] = {0}; 576 for (i = 0; i < cdata.num_workers; i++) { 577 pkts_per_wkr[i] = 578 port_stat(dev_id, worker_data[i].port_id); 579 tot_pkts += pkts_per_wkr[i]; 580 } 581 for (i = 0; i < cdata.num_workers; i++) { 582 float pc = pkts_per_wkr[i] * 100 / 583 ((float)tot_pkts); 584 printf("worker %i :\t%.1f %% (%"PRIu64" pkts)\n", 585 i, pc, pkts_per_wkr[i]); 586 } 587 588 } 589 590 return 0; 591 } 592