1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2020 Mellanox Technologies, Ltd 3 */ 4 5 #include <unistd.h> 6 #include <strings.h> 7 #include <stdint.h> 8 #include <sys/mman.h> 9 10 #include <rte_malloc.h> 11 #include <rte_log.h> 12 #include <rte_errno.h> 13 #include <rte_bus_pci.h> 14 #include <rte_pci.h> 15 #include <rte_regexdev_driver.h> 16 #include <rte_mbuf.h> 17 18 #include <infiniband/mlx5dv.h> 19 #include <mlx5_glue.h> 20 #include <mlx5_common.h> 21 #include <mlx5_prm.h> 22 23 #include "mlx5_regex_utils.h" 24 #include "mlx5_rxp.h" 25 #include "mlx5_regex.h" 26 27 #define MLX5_REGEX_MAX_WQE_INDEX 0xffff 28 #define MLX5_REGEX_METADATA_SIZE UINT32_C(64) 29 #define MLX5_REGEX_MAX_OUTPUT RTE_BIT32(11) 30 #define MLX5_REGEX_WQE_CTRL_OFFSET 12 31 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 32 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 33 #define MLX5_REGEX_WQE_SCATTER_OFFSET 48 34 #define MLX5_REGEX_METADATA_OFF 32 35 36 static inline uint32_t 37 sq_size_get(struct mlx5_regex_sq *sq) 38 { 39 return (1U << sq->log_nb_desc); 40 } 41 42 static inline uint32_t 43 cq_size_get(struct mlx5_regex_cq *cq) 44 { 45 return (1U << cq->log_nb_desc); 46 } 47 48 struct mlx5_regex_job { 49 uint64_t user_id; 50 volatile uint8_t *output; 51 volatile uint8_t *metadata; 52 } __rte_cached_aligned; 53 54 static inline void 55 set_data_seg(struct mlx5_wqe_data_seg *seg, 56 uint32_t length, uint32_t lkey, 57 uintptr_t address) 58 { 59 seg->byte_count = rte_cpu_to_be_32(length); 60 seg->lkey = rte_cpu_to_be_32(lkey); 61 seg->addr = rte_cpu_to_be_64(address); 62 } 63 64 static inline void 65 set_metadata_seg(struct mlx5_wqe_metadata_seg *seg, 66 uint32_t mmo_control_31_0, uint32_t lkey, 67 uintptr_t address) 68 { 69 seg->mmo_control_31_0 = htobe32(mmo_control_31_0); 70 seg->lkey = rte_cpu_to_be_32(lkey); 71 seg->addr = rte_cpu_to_be_64(address); 72 } 73 74 static inline void 75 set_regex_ctrl_seg(void *seg, uint8_t le, uint16_t subset_id0, 76 uint16_t subset_id1, uint16_t subset_id2, 77 uint16_t subset_id3, uint8_t ctrl) 78 { 79 MLX5_SET(regexp_mmo_control, seg, le, le); 80 MLX5_SET(regexp_mmo_control, seg, ctrl, ctrl); 81 MLX5_SET(regexp_mmo_control, seg, subset_id_0, subset_id0); 82 MLX5_SET(regexp_mmo_control, seg, subset_id_1, subset_id1); 83 MLX5_SET(regexp_mmo_control, seg, subset_id_2, subset_id2); 84 MLX5_SET(regexp_mmo_control, seg, subset_id_3, subset_id3); 85 } 86 87 static inline void 88 set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, 89 uint8_t opmod, uint32_t qp_num, uint8_t fm_ce_se, uint8_t ds, 90 uint8_t signature, uint32_t imm) 91 { 92 seg->opmod_idx_opcode = rte_cpu_to_be_32(((uint32_t)opmod << 24) | 93 ((uint32_t)pi << 8) | 94 opcode); 95 seg->qpn_ds = rte_cpu_to_be_32((qp_num << 8) | ds); 96 seg->fm_ce_se = fm_ce_se; 97 seg->signature = signature; 98 seg->imm = imm; 99 } 100 101 static inline void 102 prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, 103 struct mlx5_regex_sq *sq, struct rte_regex_ops *op, 104 struct mlx5_regex_job *job) 105 { 106 size_t wqe_offset = (sq->pi & (sq_size_get(sq) - 1)) * MLX5_SEND_WQE_BB; 107 uint32_t lkey; 108 uint16_t group0 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F ? 109 op->group_id0 : 0; 110 uint16_t group1 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F ? 111 op->group_id1 : 0; 112 uint16_t group2 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F ? 113 op->group_id2 : 0; 114 uint16_t group3 = op->req_flags & RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F ? 115 op->group_id3 : 0; 116 117 /* For backward compatibility. */ 118 if (!(op->req_flags & (RTE_REGEX_OPS_REQ_GROUP_ID0_VALID_F | 119 RTE_REGEX_OPS_REQ_GROUP_ID1_VALID_F | 120 RTE_REGEX_OPS_REQ_GROUP_ID2_VALID_F | 121 RTE_REGEX_OPS_REQ_GROUP_ID3_VALID_F))) 122 group0 = op->group_id0; 123 lkey = mlx5_mr_addr2mr_bh(priv->pd, 0, 124 &priv->mr_scache, &qp->mr_ctrl, 125 rte_pktmbuf_mtod(op->mbuf, uintptr_t), 126 !!(op->mbuf->ol_flags & EXT_ATTACHED_MBUF)); 127 uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes + wqe_offset; 128 int ds = 4; /* ctrl + meta + input + output */ 129 130 set_wqe_ctrl_seg((struct mlx5_wqe_ctrl_seg *)wqe, sq->pi, 131 MLX5_OPCODE_MMO, MLX5_OPC_MOD_MMO_REGEX, 132 sq->sq_obj.sq->id, 0, ds, 0, 0); 133 set_regex_ctrl_seg(wqe + 12, 0, group0, group1, group2, group3, 134 0); 135 struct mlx5_wqe_data_seg *input_seg = 136 (struct mlx5_wqe_data_seg *)(wqe + 137 MLX5_REGEX_WQE_GATHER_OFFSET); 138 input_seg->byte_count = 139 rte_cpu_to_be_32(rte_pktmbuf_data_len(op->mbuf)); 140 input_seg->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(op->mbuf, 141 uintptr_t)); 142 input_seg->lkey = lkey; 143 job->user_id = op->user_id; 144 sq->db_pi = sq->pi; 145 sq->pi = (sq->pi + 1) & MLX5_REGEX_MAX_WQE_INDEX; 146 } 147 148 static inline void 149 send_doorbell(struct mlx5dv_devx_uar *uar, struct mlx5_regex_sq *sq) 150 { 151 size_t wqe_offset = (sq->db_pi & (sq_size_get(sq) - 1)) * 152 MLX5_SEND_WQE_BB; 153 uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes + wqe_offset; 154 ((struct mlx5_wqe_ctrl_seg *)wqe)->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; 155 uint64_t *doorbell_addr = 156 (uint64_t *)((uint8_t *)uar->base_addr + 0x800); 157 rte_io_wmb(); 158 sq->sq_obj.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32((sq->db_pi + 1) & 159 MLX5_REGEX_MAX_WQE_INDEX); 160 rte_wmb(); 161 *doorbell_addr = *(volatile uint64_t *)wqe; 162 rte_wmb(); 163 } 164 165 static inline int 166 can_send(struct mlx5_regex_sq *sq) { 167 return ((uint16_t)(sq->pi - sq->ci) < sq_size_get(sq)); 168 } 169 170 static inline uint32_t 171 job_id_get(uint32_t qid, size_t sq_size, size_t index) { 172 return qid * sq_size + (index & (sq_size - 1)); 173 } 174 175 uint16_t 176 mlx5_regexdev_enqueue(struct rte_regexdev *dev, uint16_t qp_id, 177 struct rte_regex_ops **ops, uint16_t nb_ops) 178 { 179 struct mlx5_regex_priv *priv = dev->data->dev_private; 180 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 181 struct mlx5_regex_sq *sq; 182 size_t sqid, job_id, i = 0; 183 184 while ((sqid = ffs(queue->free_sqs))) { 185 sqid--; /* ffs returns 1 for bit 0 */ 186 sq = &queue->sqs[sqid]; 187 while (can_send(sq)) { 188 job_id = job_id_get(sqid, sq_size_get(sq), sq->pi); 189 prep_one(priv, queue, sq, ops[i], &queue->jobs[job_id]); 190 i++; 191 if (unlikely(i == nb_ops)) { 192 send_doorbell(priv->uar, sq); 193 goto out; 194 } 195 } 196 queue->free_sqs &= ~(1 << sqid); 197 send_doorbell(priv->uar, sq); 198 } 199 200 out: 201 queue->pi += i; 202 return i; 203 } 204 205 #define MLX5_REGEX_RESP_SZ 8 206 207 static inline void 208 extract_result(struct rte_regex_ops *op, struct mlx5_regex_job *job) 209 { 210 size_t j; 211 size_t offset; 212 uint16_t status; 213 214 op->user_id = job->user_id; 215 op->nb_matches = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 216 MLX5_REGEX_METADATA_OFF, 217 match_count); 218 op->nb_actual_matches = MLX5_GET_VOLATILE(regexp_metadata, 219 job->metadata + 220 MLX5_REGEX_METADATA_OFF, 221 detected_match_count); 222 for (j = 0; j < op->nb_matches; j++) { 223 offset = MLX5_REGEX_RESP_SZ * j; 224 op->matches[j].rule_id = 225 MLX5_GET_VOLATILE(regexp_match_tuple, 226 (job->output + offset), rule_id); 227 op->matches[j].start_offset = 228 MLX5_GET_VOLATILE(regexp_match_tuple, 229 (job->output + offset), start_ptr); 230 op->matches[j].len = 231 MLX5_GET_VOLATILE(regexp_match_tuple, 232 (job->output + offset), length); 233 } 234 status = MLX5_GET_VOLATILE(regexp_metadata, job->metadata + 235 MLX5_REGEX_METADATA_OFF, 236 status); 237 op->rsp_flags = 0; 238 if (status & MLX5_RXP_RESP_STATUS_PMI_SOJ) 239 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_SOJ_F; 240 if (status & MLX5_RXP_RESP_STATUS_PMI_EOJ) 241 op->rsp_flags |= RTE_REGEX_OPS_RSP_PMI_EOJ_F; 242 if (status & MLX5_RXP_RESP_STATUS_MAX_LATENCY) 243 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_SCAN_TIMEOUT_F; 244 if (status & MLX5_RXP_RESP_STATUS_MAX_MATCH) 245 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_MATCH_F; 246 if (status & MLX5_RXP_RESP_STATUS_MAX_PREFIX) 247 op->rsp_flags |= RTE_REGEX_OPS_RSP_MAX_PREFIX_F; 248 if (status & MLX5_RXP_RESP_STATUS_MAX_PRI_THREADS) 249 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F; 250 if (status & MLX5_RXP_RESP_STATUS_MAX_SEC_THREADS) 251 op->rsp_flags |= RTE_REGEX_OPS_RSP_RESOURCE_LIMIT_REACHED_F; 252 } 253 254 static inline volatile struct mlx5_cqe * 255 poll_one(struct mlx5_regex_cq *cq) 256 { 257 volatile struct mlx5_cqe *cqe; 258 size_t next_cqe_offset; 259 260 next_cqe_offset = (cq->ci & (cq_size_get(cq) - 1)); 261 cqe = (volatile struct mlx5_cqe *)(cq->cq_obj.cqes + next_cqe_offset); 262 rte_io_wmb(); 263 264 int ret = check_cqe(cqe, cq_size_get(cq), cq->ci); 265 266 if (unlikely(ret == MLX5_CQE_STATUS_ERR)) { 267 DRV_LOG(ERR, "Completion with error on qp 0x%x", 0); 268 return NULL; 269 } 270 271 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) 272 return NULL; 273 274 return cqe; 275 } 276 277 278 /** 279 * DPDK callback for dequeue. 280 * 281 * @param dev 282 * Pointer to the regex dev structure. 283 * @param qp_id 284 * The queue to enqueue the traffic to. 285 * @param ops 286 * List of regex ops to dequeue. 287 * @param nb_ops 288 * Number of ops in ops parameter. 289 * 290 * @return 291 * Number of packets successfully dequeued (<= pkts_n). 292 */ 293 uint16_t 294 mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id, 295 struct rte_regex_ops **ops, uint16_t nb_ops) 296 { 297 struct mlx5_regex_priv *priv = dev->data->dev_private; 298 struct mlx5_regex_qp *queue = &priv->qps[qp_id]; 299 struct mlx5_regex_cq *cq = &queue->cq; 300 volatile struct mlx5_cqe *cqe; 301 size_t i = 0; 302 303 while ((cqe = poll_one(cq))) { 304 uint16_t wq_counter 305 = (rte_be_to_cpu_16(cqe->wqe_counter) + 1) & 306 MLX5_REGEX_MAX_WQE_INDEX; 307 size_t sqid = cqe->rsvd3[2]; 308 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 309 while (sq->ci != wq_counter) { 310 if (unlikely(i == nb_ops)) { 311 /* Return without updating cq->ci */ 312 goto out; 313 } 314 uint32_t job_id = job_id_get(sqid, sq_size_get(sq), 315 sq->ci); 316 extract_result(ops[i], &queue->jobs[job_id]); 317 sq->ci = (sq->ci + 1) & MLX5_REGEX_MAX_WQE_INDEX; 318 i++; 319 } 320 cq->ci = (cq->ci + 1) & 0xffffff; 321 rte_wmb(); 322 cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->ci); 323 queue->free_sqs |= (1 << sqid); 324 } 325 326 out: 327 queue->ci += i; 328 return i; 329 } 330 331 static void 332 setup_sqs(struct mlx5_regex_qp *queue) 333 { 334 size_t sqid, entry; 335 uint32_t job_id; 336 for (sqid = 0; sqid < queue->nb_obj; sqid++) { 337 struct mlx5_regex_sq *sq = &queue->sqs[sqid]; 338 uint8_t *wqe = (uint8_t *)(uintptr_t)sq->sq_obj.wqes; 339 for (entry = 0 ; entry < sq_size_get(sq); entry++) { 340 job_id = sqid * sq_size_get(sq) + entry; 341 struct mlx5_regex_job *job = &queue->jobs[job_id]; 342 343 set_metadata_seg((struct mlx5_wqe_metadata_seg *) 344 (wqe + MLX5_REGEX_WQE_METADATA_OFFSET), 345 0, queue->metadata->lkey, 346 (uintptr_t)job->metadata); 347 set_data_seg((struct mlx5_wqe_data_seg *) 348 (wqe + MLX5_REGEX_WQE_SCATTER_OFFSET), 349 MLX5_REGEX_MAX_OUTPUT, 350 queue->outputs->lkey, 351 (uintptr_t)job->output); 352 wqe += 64; 353 } 354 queue->free_sqs |= 1 << sqid; 355 } 356 } 357 358 static int 359 setup_buffers(struct mlx5_regex_qp *qp, struct ibv_pd *pd) 360 { 361 uint32_t i; 362 int err; 363 364 void *ptr = rte_calloc(__func__, qp->nb_desc, 365 MLX5_REGEX_METADATA_SIZE, 366 MLX5_REGEX_METADATA_SIZE); 367 if (!ptr) 368 return -ENOMEM; 369 370 qp->metadata = mlx5_glue->reg_mr(pd, ptr, 371 MLX5_REGEX_METADATA_SIZE * qp->nb_desc, 372 IBV_ACCESS_LOCAL_WRITE); 373 if (!qp->metadata) { 374 DRV_LOG(ERR, "Failed to register metadata"); 375 rte_free(ptr); 376 return -EINVAL; 377 } 378 379 ptr = rte_calloc(__func__, qp->nb_desc, 380 MLX5_REGEX_MAX_OUTPUT, 381 MLX5_REGEX_MAX_OUTPUT); 382 if (!ptr) { 383 err = -ENOMEM; 384 goto err_output; 385 } 386 qp->outputs = mlx5_glue->reg_mr(pd, ptr, 387 MLX5_REGEX_MAX_OUTPUT * qp->nb_desc, 388 IBV_ACCESS_LOCAL_WRITE); 389 if (!qp->outputs) { 390 rte_free(ptr); 391 DRV_LOG(ERR, "Failed to register output"); 392 err = -EINVAL; 393 goto err_output; 394 } 395 396 /* distribute buffers to jobs */ 397 for (i = 0; i < qp->nb_desc; i++) { 398 qp->jobs[i].output = 399 (uint8_t *)qp->outputs->addr + 400 (i % qp->nb_desc) * MLX5_REGEX_MAX_OUTPUT; 401 qp->jobs[i].metadata = 402 (uint8_t *)qp->metadata->addr + 403 (i % qp->nb_desc) * MLX5_REGEX_METADATA_SIZE; 404 } 405 return 0; 406 407 err_output: 408 ptr = qp->metadata->addr; 409 rte_free(ptr); 410 mlx5_glue->dereg_mr(qp->metadata); 411 return err; 412 } 413 414 int 415 mlx5_regexdev_setup_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 416 { 417 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 418 int err; 419 420 qp->jobs = rte_calloc(__func__, qp->nb_desc, sizeof(*qp->jobs), 64); 421 if (!qp->jobs) 422 return -ENOMEM; 423 err = setup_buffers(qp, priv->pd); 424 if (err) { 425 rte_free(qp->jobs); 426 return err; 427 } 428 setup_sqs(qp); 429 return 0; 430 } 431 432 static void 433 free_buffers(struct mlx5_regex_qp *qp) 434 { 435 if (qp->metadata) { 436 mlx5_glue->dereg_mr(qp->metadata); 437 rte_free(qp->metadata->addr); 438 } 439 if (qp->outputs) { 440 mlx5_glue->dereg_mr(qp->outputs); 441 rte_free(qp->outputs->addr); 442 } 443 } 444 445 void 446 mlx5_regexdev_teardown_fastpath(struct mlx5_regex_priv *priv, uint32_t qp_id) 447 { 448 struct mlx5_regex_qp *qp = &priv->qps[qp_id]; 449 450 if (qp) { 451 free_buffers(qp); 452 if (qp->jobs) 453 rte_free(qp->jobs); 454 } 455 } 456