17d63899aSWei Huang /* SPDX-License-Identifier: BSD-3-Clause 27d63899aSWei Huang * Copyright 2022 Intel Corporation 37d63899aSWei Huang */ 47d63899aSWei Huang 57d63899aSWei Huang #ifndef RTE_PMD_AFU_H 67d63899aSWei Huang #define RTE_PMD_AFU_H 77d63899aSWei Huang 87d63899aSWei Huang /** 97d63899aSWei Huang * @file rte_pmd_afu.h 107d63899aSWei Huang * 117d63899aSWei Huang * AFU PMD specific definitions. 127d63899aSWei Huang * 137d63899aSWei Huang * @b EXPERIMENTAL: this API may change, or be removed, without prior notice 147d63899aSWei Huang * 157d63899aSWei Huang */ 167d63899aSWei Huang 17*719834a6SMattias Rönnblom #include <stdint.h> 18*719834a6SMattias Rönnblom 197d63899aSWei Huang #ifdef __cplusplus 207d63899aSWei Huang extern "C" { 217d63899aSWei Huang #endif 227d63899aSWei Huang 237d63899aSWei Huang #define RTE_PMD_AFU_N3000_NLB 1 247d63899aSWei Huang #define RTE_PMD_AFU_N3000_DMA 2 257d63899aSWei Huang 267d63899aSWei Huang #define NLB_MODE_LPBK 0 277d63899aSWei Huang #define NLB_MODE_READ 1 287d63899aSWei Huang #define NLB_MODE_WRITE 2 297d63899aSWei Huang #define NLB_MODE_TRPUT 3 307d63899aSWei Huang 317d63899aSWei Huang #define NLB_VC_AUTO 0 327d63899aSWei Huang #define NLB_VC_VL0 1 337d63899aSWei Huang #define NLB_VC_VH0 2 347d63899aSWei Huang #define NLB_VC_VH1 3 357d63899aSWei Huang #define NLB_VC_RANDOM 4 367d63899aSWei Huang 377d63899aSWei Huang #define NLB_WRLINE_M 0 387d63899aSWei Huang #define NLB_WRLINE_I 1 397d63899aSWei Huang #define NLB_WRPUSH_I 2 407d63899aSWei Huang 417d63899aSWei Huang #define NLB_RDLINE_S 0 427d63899aSWei Huang #define NLB_RDLINE_I 1 437d63899aSWei Huang #define NLB_RDLINE_MIXED 2 447d63899aSWei Huang 457d63899aSWei Huang #define MIN_CACHE_LINES 1 467d63899aSWei Huang #define MAX_CACHE_LINES 1024 477d63899aSWei Huang 487d63899aSWei Huang #define MIN_DMA_BUF_SIZE 64 497d63899aSWei Huang #define MAX_DMA_BUF_SIZE (1023 * 1024) 507d63899aSWei Huang 517d63899aSWei Huang /** 527d63899aSWei Huang * NLB AFU configuration data structure. 537d63899aSWei Huang */ 547d63899aSWei Huang struct rte_pmd_afu_nlb_cfg { 557d63899aSWei Huang uint32_t mode; 567d63899aSWei Huang uint32_t begin; 577d63899aSWei Huang uint32_t end; 587d63899aSWei Huang uint32_t multi_cl; 597d63899aSWei Huang uint32_t cont; 607d63899aSWei Huang uint32_t timeout; 617d63899aSWei Huang uint32_t cache_policy; 627d63899aSWei Huang uint32_t cache_hint; 637d63899aSWei Huang uint32_t read_vc; 647d63899aSWei Huang uint32_t write_vc; 657d63899aSWei Huang uint32_t wrfence_vc; 667d63899aSWei Huang uint32_t freq_mhz; 677d63899aSWei Huang }; 687d63899aSWei Huang 697d63899aSWei Huang /** 707d63899aSWei Huang * DMA AFU configuration data structure. 717d63899aSWei Huang */ 727d63899aSWei Huang struct rte_pmd_afu_dma_cfg { 737d63899aSWei Huang uint32_t index; /* index of DMA controller */ 747d63899aSWei Huang uint32_t length; /* total length of data to DMA */ 757d63899aSWei Huang uint32_t offset; /* address offset of target memory */ 767d63899aSWei Huang uint32_t size; /* size of transfer buffer */ 777d63899aSWei Huang uint32_t pattern; /* data pattern to fill in test buffer */ 787d63899aSWei Huang uint32_t unaligned; /* use unaligned address or length in sweep test */ 797d63899aSWei Huang uint32_t verbose; /* enable verbose error information in test */ 807d63899aSWei Huang }; 817d63899aSWei Huang 827d63899aSWei Huang /** 837d63899aSWei Huang * N3000 AFU configuration data structure. 847d63899aSWei Huang */ 857d63899aSWei Huang struct rte_pmd_afu_n3000_cfg { 867d63899aSWei Huang int type; /* RTE_PMD_AFU_N3000_NLB or RTE_PMD_AFU_N3000_DMA */ 877d63899aSWei Huang union { 887d63899aSWei Huang struct rte_pmd_afu_nlb_cfg nlb_cfg; 897d63899aSWei Huang struct rte_pmd_afu_dma_cfg dma_cfg; 907d63899aSWei Huang }; 917d63899aSWei Huang }; 927d63899aSWei Huang 93a84edb50SWei Huang /** 94a84edb50SWei Huang * HE-LPBK & HE-MEM-LPBK AFU configuration data structure. 95a84edb50SWei Huang */ 96a84edb50SWei Huang struct rte_pmd_afu_he_lpbk_cfg { 97a84edb50SWei Huang uint32_t mode; 98a84edb50SWei Huang uint32_t begin; 99a84edb50SWei Huang uint32_t end; 100a84edb50SWei Huang uint32_t multi_cl; 101a84edb50SWei Huang uint32_t cont; 102a84edb50SWei Huang uint32_t timeout; 103a84edb50SWei Huang uint32_t trput_interleave; 104a84edb50SWei Huang uint32_t freq_mhz; 105a84edb50SWei Huang }; 106a84edb50SWei Huang 10772dbdec4SWei Huang /** 10872dbdec4SWei Huang * HE-MEM-TG AFU configuration data structure. 10972dbdec4SWei Huang */ 11072dbdec4SWei Huang struct rte_pmd_afu_he_mem_tg_cfg { 11172dbdec4SWei Huang uint32_t channel_mask; /* mask of traffic generator channel */ 11272dbdec4SWei Huang }; 11372dbdec4SWei Huang 1148b594728SWei Huang #define NUM_RND_SEEDS 3 1158b594728SWei Huang 1168b594728SWei Huang /** 1178b594728SWei Huang * HE-HSSI AFU configuration data structure. 1188b594728SWei Huang */ 1198b594728SWei Huang struct rte_pmd_afu_he_hssi_cfg { 1208b594728SWei Huang uint32_t port; 1218b594728SWei Huang uint32_t timeout; 1228b594728SWei Huang uint32_t num_packets; 1238b594728SWei Huang uint32_t random_length; 1248b594728SWei Huang uint32_t packet_length; 1258b594728SWei Huang uint32_t random_payload; 1268b594728SWei Huang uint32_t rnd_seed[NUM_RND_SEEDS]; 1278b594728SWei Huang uint64_t src_addr; 1288b594728SWei Huang uint64_t dest_addr; 1298b594728SWei Huang int he_loopback; 1308b594728SWei Huang }; 1318b594728SWei Huang 1327d63899aSWei Huang #ifdef __cplusplus 1337d63899aSWei Huang } 1347d63899aSWei Huang #endif 1357d63899aSWei Huang 1367d63899aSWei Huang #endif /* RTE_PMD_AFU_H */ 137