16dd52083SGagandeep Singh /* SPDX-License-Identifier: BSD-3-Clause 2*f513f620SSachin Saxena * Copyright 2018-2019 NXP 36dd52083SGagandeep Singh */ 46dd52083SGagandeep Singh 56dd52083SGagandeep Singh #ifndef _HIF_H_ 66dd52083SGagandeep Singh #define _HIF_H_ 76dd52083SGagandeep Singh 86dd52083SGagandeep Singh /* @file hif.h. 96dd52083SGagandeep Singh * hif - PFE hif block control and status register. 106dd52083SGagandeep Singh * Mapped on CBUS and accessible from all PE's and ARM. 116dd52083SGagandeep Singh */ 126dd52083SGagandeep Singh #define HIF_VERSION (HIF_BASE_ADDR + 0x00) 136dd52083SGagandeep Singh #define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04) 146dd52083SGagandeep Singh #define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08) 156dd52083SGagandeep Singh #define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c) 166dd52083SGagandeep Singh #define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10) 176dd52083SGagandeep Singh #define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14) 186dd52083SGagandeep Singh #define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20) 196dd52083SGagandeep Singh #define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24) 206dd52083SGagandeep Singh #define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30) 216dd52083SGagandeep Singh #define HIF_INT_SRC (HIF_BASE_ADDR + 0x34) 226dd52083SGagandeep Singh #define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38) 236dd52083SGagandeep Singh #define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c) 246dd52083SGagandeep Singh #define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40) 256dd52083SGagandeep Singh #define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44) 266dd52083SGagandeep Singh #define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48) 276dd52083SGagandeep Singh #define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c) 286dd52083SGagandeep Singh #define HIF_INT_COAL (HIF_BASE_ADDR + 0x50) 296dd52083SGagandeep Singh 306dd52083SGagandeep Singh /* HIF_INT_SRC/ HIF_INT_ENABLE control bits */ 316dd52083SGagandeep Singh #define HIF_INT BIT(0) 326dd52083SGagandeep Singh #define HIF_RXBD_INT BIT(1) 336dd52083SGagandeep Singh #define HIF_RXPKT_INT BIT(2) 346dd52083SGagandeep Singh #define HIF_TXBD_INT BIT(3) 356dd52083SGagandeep Singh #define HIF_TXPKT_INT BIT(4) 366dd52083SGagandeep Singh 376dd52083SGagandeep Singh /* HIF_TX_CTRL bits */ 386dd52083SGagandeep Singh #define HIF_CTRL_DMA_EN BIT(0) 396dd52083SGagandeep Singh #define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1) 406dd52083SGagandeep Singh #define HIF_CTRL_BDP_CH_START_WSTB BIT(2) 416dd52083SGagandeep Singh 426dd52083SGagandeep Singh /* HIF_RX_STATUS bits */ 436dd52083SGagandeep Singh #define BDP_CSR_RX_DMA_ACTV BIT(16) 446dd52083SGagandeep Singh 456dd52083SGagandeep Singh /* HIF_INT_ENABLE bits */ 466dd52083SGagandeep Singh #define HIF_INT_EN BIT(0) 476dd52083SGagandeep Singh #define HIF_RXBD_INT_EN BIT(1) 486dd52083SGagandeep Singh #define HIF_RXPKT_INT_EN BIT(2) 496dd52083SGagandeep Singh #define HIF_TXBD_INT_EN BIT(3) 506dd52083SGagandeep Singh #define HIF_TXPKT_INT_EN BIT(4) 516dd52083SGagandeep Singh 526dd52083SGagandeep Singh /* HIF_POLL_CTRL bits*/ 536dd52083SGagandeep Singh #define HIF_RX_POLL_CTRL_CYCLE 0x0400 546dd52083SGagandeep Singh #define HIF_TX_POLL_CTRL_CYCLE 0x0400 556dd52083SGagandeep Singh 566dd52083SGagandeep Singh /* HIF_INT_COAL bits*/ 576dd52083SGagandeep Singh #define HIF_INT_COAL_ENABLE BIT(31) 586dd52083SGagandeep Singh 596dd52083SGagandeep Singh /* Buffer descriptor control bits */ 606dd52083SGagandeep Singh #define BD_CTRL_BUFLEN_MASK 0x3fff 616dd52083SGagandeep Singh #define BD_BUF_LEN(x) ((x) & BD_CTRL_BUFLEN_MASK) 626dd52083SGagandeep Singh #define BD_CTRL_CBD_INT_EN BIT(16) 636dd52083SGagandeep Singh #define BD_CTRL_PKT_INT_EN BIT(17) 646dd52083SGagandeep Singh #define BD_CTRL_LIFM BIT(18) 656dd52083SGagandeep Singh #define BD_CTRL_LAST_BD BIT(19) 666dd52083SGagandeep Singh #define BD_CTRL_DIR BIT(20) 676dd52083SGagandeep Singh #define BD_CTRL_LMEM_CPY BIT(21) /* Valid only for HIF_NOCPY */ 686dd52083SGagandeep Singh #define BD_CTRL_PKT_XFER BIT(24) 696dd52083SGagandeep Singh #define BD_CTRL_DESC_EN BIT(31) 706dd52083SGagandeep Singh #define BD_CTRL_PARSE_DISABLE BIT(25) 716dd52083SGagandeep Singh #define BD_CTRL_BRFETCH_DISABLE BIT(26) 726dd52083SGagandeep Singh #define BD_CTRL_RTFETCH_DISABLE BIT(27) 736dd52083SGagandeep Singh 746dd52083SGagandeep Singh /* Buffer descriptor status bits*/ 756dd52083SGagandeep Singh #define BD_STATUS_CONN_ID(x) ((x) & 0xffff) 766dd52083SGagandeep Singh #define BD_STATUS_DIR_PROC_ID BIT(16) 776dd52083SGagandeep Singh #define BD_STATUS_CONN_ID_EN BIT(17) 786dd52083SGagandeep Singh #define BD_STATUS_PE2PROC_ID(x) (((x) & 7) << 18) 796dd52083SGagandeep Singh #define BD_STATUS_LE_DATA BIT(21) 806dd52083SGagandeep Singh #define BD_STATUS_CHKSUM_EN BIT(22) 816dd52083SGagandeep Singh 826dd52083SGagandeep Singh /* HIF Buffer descriptor status bits */ 836dd52083SGagandeep Singh #define DIR_PROC_ID BIT(16) 846dd52083SGagandeep Singh #define PROC_ID(id) ((id) << 18) 856dd52083SGagandeep Singh 866dd52083SGagandeep Singh #endif /* _HIF_H_ */ 87