16dd52083SGagandeep Singh /* SPDX-License-Identifier: BSD-3-Clause 2f513f620SSachin Saxena * Copyright 2018-2019 NXP 36dd52083SGagandeep Singh */ 46dd52083SGagandeep Singh 56dd52083SGagandeep Singh #ifndef _CBUS_H_ 66dd52083SGagandeep Singh #define _CBUS_H_ 76dd52083SGagandeep Singh 86dd52083SGagandeep Singh #include <compat.h> 96dd52083SGagandeep Singh 106dd52083SGagandeep Singh #define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) 116dd52083SGagandeep Singh #define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) 126dd52083SGagandeep Singh #define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) 136dd52083SGagandeep Singh #define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) 146dd52083SGagandeep Singh #define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) 156dd52083SGagandeep Singh #define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) 166dd52083SGagandeep Singh #define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) 176dd52083SGagandeep Singh #define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) 186dd52083SGagandeep Singh #define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) 196dd52083SGagandeep Singh #define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) 206dd52083SGagandeep Singh #define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) 216dd52083SGagandeep Singh #define LMEM_SIZE 0x10000 226dd52083SGagandeep Singh #define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) 236dd52083SGagandeep Singh #define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) 246dd52083SGagandeep Singh #define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) 256dd52083SGagandeep Singh #define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) 266dd52083SGagandeep Singh #define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) 276dd52083SGagandeep Singh #define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) 286dd52083SGagandeep Singh 296dd52083SGagandeep Singh /* 306dd52083SGagandeep Singh * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR 316dd52083SGagandeep Singh * XXX_MEM_ACCESS_ADDR register bit definitions. 326dd52083SGagandeep Singh */ 336dd52083SGagandeep Singh #define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */ 346dd52083SGagandeep Singh #define PE_MEM_ACCESS_IMEM BIT(15) 356dd52083SGagandeep Singh #define PE_MEM_ACCESS_DMEM BIT(16) 366dd52083SGagandeep Singh 376dd52083SGagandeep Singh /* Byte Enables of the Internal memory access. These are interpred in BE */ 386dd52083SGagandeep Singh #define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) \ 39*93998f3cSTyler Retzlaff __extension__ ({ typeof(size) size_ = (size); \ 406dd52083SGagandeep Singh (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; }) 416dd52083SGagandeep Singh 426dd52083SGagandeep Singh #include "cbus/emac_mtip.h" 436dd52083SGagandeep Singh #include "cbus/gpi.h" 446dd52083SGagandeep Singh #include "cbus/bmu.h" 456dd52083SGagandeep Singh #include "cbus/hif.h" 466dd52083SGagandeep Singh #include "cbus/tmu_csr.h" 476dd52083SGagandeep Singh #include "cbus/class_csr.h" 486dd52083SGagandeep Singh #include "cbus/hif_nocpy.h" 496dd52083SGagandeep Singh #include "cbus/util_csr.h" 506dd52083SGagandeep Singh 516dd52083SGagandeep Singh /* PFE cores states */ 526dd52083SGagandeep Singh #define CORE_DISABLE 0x00000000 536dd52083SGagandeep Singh #define CORE_ENABLE 0x00000001 546dd52083SGagandeep Singh #define CORE_SW_RESET 0x00000002 556dd52083SGagandeep Singh 566dd52083SGagandeep Singh /* LMEM defines */ 576dd52083SGagandeep Singh #define LMEM_HDR_SIZE 0x0010 586dd52083SGagandeep Singh #define LMEM_BUF_SIZE_LN2 0x7 596dd52083SGagandeep Singh #define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2) 606dd52083SGagandeep Singh 616dd52083SGagandeep Singh /* DDR defines */ 626dd52083SGagandeep Singh #define DDR_HDR_SIZE 0x0100 636dd52083SGagandeep Singh #define DDR_BUF_SIZE_LN2 0xb 646dd52083SGagandeep Singh #define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2) 656dd52083SGagandeep Singh 666dd52083SGagandeep Singh #endif /* _CBUS_H_ */ 67