1*05aa6305SSerhii Iliushyk /* 2*05aa6305SSerhii Iliushyk * SPDX-License-Identifier: BSD-3-Clause 3*05aa6305SSerhii Iliushyk * Copyright(c) 2023 Napatech A/S 4*05aa6305SSerhii Iliushyk */ 5*05aa6305SSerhii Iliushyk 6*05aa6305SSerhii Iliushyk #ifndef _FPGA_MODEL_H_ 7*05aa6305SSerhii Iliushyk #define _FPGA_MODEL_H_ 8*05aa6305SSerhii Iliushyk 9*05aa6305SSerhii Iliushyk #include <unistd.h> 10*05aa6305SSerhii Iliushyk #include <stdint.h> 11*05aa6305SSerhii Iliushyk #include <inttypes.h> 12*05aa6305SSerhii Iliushyk 13*05aa6305SSerhii Iliushyk typedef uint32_t nthw_id_t; 14*05aa6305SSerhii Iliushyk 15*05aa6305SSerhii Iliushyk enum nthw_fpga_bus_type { 16*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_UNKNOWN = 17*05aa6305SSerhii Iliushyk 0, /* Unknown/uninitialized - keep this as the first enum element */ 18*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_BAR, 19*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_PCI, 20*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_CCIP, 21*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_RAB0, 22*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_RAB1, 23*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_RAB2, 24*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_NMB, 25*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_NDM, 26*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_SPI0, 27*05aa6305SSerhii Iliushyk NTHW_FPGA_BUS_TYPE_SPI = NTHW_FPGA_BUS_TYPE_SPI0, 28*05aa6305SSerhii Iliushyk }; 29*05aa6305SSerhii Iliushyk 30*05aa6305SSerhii Iliushyk typedef enum nthw_fpga_bus_type nthw_fpga_bus_type_e; 31*05aa6305SSerhii Iliushyk 32*05aa6305SSerhii Iliushyk enum nthw_fpga_register_type { 33*05aa6305SSerhii Iliushyk NTHW_FPGA_REG_TYPE_UNKNOWN = 34*05aa6305SSerhii Iliushyk 0, /* Unknown/uninitialized - keep this as the first enum element */ 35*05aa6305SSerhii Iliushyk NTHW_FPGA_REG_TYPE_RW, 36*05aa6305SSerhii Iliushyk NTHW_FPGA_REG_TYPE_RO, 37*05aa6305SSerhii Iliushyk NTHW_FPGA_REG_TYPE_WO, 38*05aa6305SSerhii Iliushyk NTHW_FPGA_REG_TYPE_RC1, 39*05aa6305SSerhii Iliushyk NTHW_FPGA_REG_TYPE_MIXED, 40*05aa6305SSerhii Iliushyk }; 41*05aa6305SSerhii Iliushyk 42*05aa6305SSerhii Iliushyk typedef enum nthw_fpga_register_type nthw_fpga_register_type_e; 43*05aa6305SSerhii Iliushyk 44*05aa6305SSerhii Iliushyk struct nthw_fpga_field_init { 45*05aa6305SSerhii Iliushyk nthw_id_t id; 46*05aa6305SSerhii Iliushyk uint16_t bw; 47*05aa6305SSerhii Iliushyk uint16_t low; 48*05aa6305SSerhii Iliushyk uint64_t reset_val; 49*05aa6305SSerhii Iliushyk }; 50*05aa6305SSerhii Iliushyk 51*05aa6305SSerhii Iliushyk typedef struct nthw_fpga_field_init nthw_fpga_field_init_s; 52*05aa6305SSerhii Iliushyk 53*05aa6305SSerhii Iliushyk struct nthw_fpga_register_init { 54*05aa6305SSerhii Iliushyk nthw_id_t id; 55*05aa6305SSerhii Iliushyk uint32_t addr_rel; 56*05aa6305SSerhii Iliushyk uint16_t bw; 57*05aa6305SSerhii Iliushyk nthw_fpga_register_type_e type; 58*05aa6305SSerhii Iliushyk uint64_t reset_val; 59*05aa6305SSerhii Iliushyk int nb_fields; 60*05aa6305SSerhii Iliushyk struct nthw_fpga_field_init *fields; 61*05aa6305SSerhii Iliushyk }; 62*05aa6305SSerhii Iliushyk 63*05aa6305SSerhii Iliushyk typedef struct nthw_fpga_register_init nthw_fpga_register_init_s; 64*05aa6305SSerhii Iliushyk 65*05aa6305SSerhii Iliushyk struct nthw_fpga_module_init { 66*05aa6305SSerhii Iliushyk nthw_id_t id; 67*05aa6305SSerhii Iliushyk int instance; 68*05aa6305SSerhii Iliushyk nthw_id_t def_id; 69*05aa6305SSerhii Iliushyk int major_version; 70*05aa6305SSerhii Iliushyk int minor_version; 71*05aa6305SSerhii Iliushyk nthw_fpga_bus_type_e bus_id; 72*05aa6305SSerhii Iliushyk uint32_t addr_base; 73*05aa6305SSerhii Iliushyk int nb_registers; 74*05aa6305SSerhii Iliushyk struct nthw_fpga_register_init *registers; 75*05aa6305SSerhii Iliushyk }; 76*05aa6305SSerhii Iliushyk 77*05aa6305SSerhii Iliushyk typedef struct nthw_fpga_module_init nthw_fpga_module_init_s; 78*05aa6305SSerhii Iliushyk 79*05aa6305SSerhii Iliushyk struct nthw_fpga_prod_param { 80*05aa6305SSerhii Iliushyk const nthw_id_t id; 81*05aa6305SSerhii Iliushyk const int value; 82*05aa6305SSerhii Iliushyk }; 83*05aa6305SSerhii Iliushyk 84*05aa6305SSerhii Iliushyk typedef struct nthw_fpga_prod_param nthw_fpga_prod_param_s; 85*05aa6305SSerhii Iliushyk 86*05aa6305SSerhii Iliushyk struct nthw_fpga_prod_init { 87*05aa6305SSerhii Iliushyk int fpga_item_id; 88*05aa6305SSerhii Iliushyk int fpga_product_id; 89*05aa6305SSerhii Iliushyk int fpga_version; 90*05aa6305SSerhii Iliushyk int fpga_revision; 91*05aa6305SSerhii Iliushyk int fpga_patch_no; 92*05aa6305SSerhii Iliushyk int fpga_build_no; 93*05aa6305SSerhii Iliushyk uint32_t fpga_build_time; 94*05aa6305SSerhii Iliushyk int nb_prod_params; 95*05aa6305SSerhii Iliushyk struct nthw_fpga_prod_param *product_params; 96*05aa6305SSerhii Iliushyk int nb_modules; 97*05aa6305SSerhii Iliushyk struct nthw_fpga_module_init *modules; 98*05aa6305SSerhii Iliushyk }; 99*05aa6305SSerhii Iliushyk 100*05aa6305SSerhii Iliushyk typedef struct nthw_fpga_prod_init nthw_fpga_prod_init_s; 101*05aa6305SSerhii Iliushyk 102*05aa6305SSerhii Iliushyk #endif /* _FPGA_MODEL_H_ */ 103