xref: /dpdk/drivers/net/ngbe/base/ngbe_phy_rtl.h (revision 21f702d556fabbc50e5e8d43c7ad3dfbe9dac1bd)
144e97550SJiawen Wu /* SPDX-License-Identifier: BSD-3-Clause
244e97550SJiawen Wu  * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.
344e97550SJiawen Wu  */
444e97550SJiawen Wu 
544e97550SJiawen Wu #include "ngbe_phy.h"
644e97550SJiawen Wu 
744e97550SJiawen Wu #ifndef _NGBE_PHY_RTL_H_
844e97550SJiawen Wu #define _NGBE_PHY_RTL_H_
944e97550SJiawen Wu 
1044e97550SJiawen Wu #define NGBE_PHYID_RTL			0x001CC800U
1144e97550SJiawen Wu 
1244e97550SJiawen Wu /* Page 0 */
1344e97550SJiawen Wu #define RTL_DEV_ZERO			0
1444e97550SJiawen Wu #define RTL_BMCR			0x0
1544e97550SJiawen Wu #define   RTL_BMCR_RESET		MS16(15, 0x1)
1644e97550SJiawen Wu #define	  RTL_BMCR_SPEED_SELECT0	MS16(13, 0x1)
1744e97550SJiawen Wu #define   RTL_BMCR_ANE			MS16(12, 0x1)
18abea8974SJiawen Wu #define   RTL_BMCR_PWDN			MS16(11, 0x1)
1944e97550SJiawen Wu #define   RTL_BMCR_RESTART_AN		MS16(9, 0x1)
2044e97550SJiawen Wu #define   RTL_BMCR_DUPLEX		MS16(8, 0x1)
2144e97550SJiawen Wu #define   RTL_BMCR_SPEED_SELECT1	MS16(6, 0x1)
2244e97550SJiawen Wu #define RTL_BMSR			0x1
2344e97550SJiawen Wu #define   RTL_BMSR_ANC			MS16(5, 0x1)
2444e97550SJiawen Wu #define RTL_ID1_OFFSET			0x2
2544e97550SJiawen Wu #define RTL_ID2_OFFSET			0x3
2644e97550SJiawen Wu #define RTL_ID_MASK			0xFFFFFC00U
2744e97550SJiawen Wu #define RTL_ANAR			0x4
2844e97550SJiawen Wu #define   RTL_ANAR_APAUSE		MS16(11, 0x1)
2944e97550SJiawen Wu #define   RTL_ANAR_PAUSE		MS16(10, 0x1)
3044e97550SJiawen Wu #define   RTL_ANAR_100F			MS16(8, 0x1)
3144e97550SJiawen Wu #define   RTL_ANAR_100H			MS16(7, 0x1)
3244e97550SJiawen Wu #define   RTL_ANAR_10F			MS16(6, 0x1)
3344e97550SJiawen Wu #define   RTL_ANAR_10H			MS16(5, 0x1)
3444e97550SJiawen Wu #define RTL_ANLPAR			0x5
3544e97550SJiawen Wu #define   RTL_ANLPAR_LP			MS16(10, 0x3)
3644e97550SJiawen Wu #define RTL_GBCR			0x9
3744e97550SJiawen Wu #define   RTL_GBCR_1000F		MS16(9, 0x1)
38*21f702d5SJiawen Wu #define RTL_GBSR			0xA
39*21f702d5SJiawen Wu #define   RTL_GBSR_LRS			MS16(13, 0x1)
4044e97550SJiawen Wu /* Page 0xa42*/
4144e97550SJiawen Wu #define RTL_GSR				0x10
4244e97550SJiawen Wu #define   RTL_GSR_ST			MS16(0, 0x7)
4344e97550SJiawen Wu #define   RTL_GSR_ST_LANON		MS16(0, 0x3)
4444e97550SJiawen Wu #define RTL_INER			0x12
4544e97550SJiawen Wu #define   RTL_INER_LSC			MS16(4, 0x1)
4644e97550SJiawen Wu #define   RTL_INER_ANC			MS16(3, 0x1)
4744e97550SJiawen Wu /* Page 0xa43*/
4844e97550SJiawen Wu #define RTL_PHYSR			0x1A
4944e97550SJiawen Wu #define   RTL_PHYSR_SPEED_MASK		MS16(4, 0x3)
5044e97550SJiawen Wu #define     RTL_PHYSR_SPEED_RES		LS16(3, 4, 0x3)
5144e97550SJiawen Wu #define     RTL_PHYSR_SPEED_1000M	LS16(2, 4, 0x3)
5244e97550SJiawen Wu #define     RTL_PHYSR_SPEED_100M	LS16(1, 4, 0x3)
5344e97550SJiawen Wu #define     RTL_PHYSR_SPEED_10M		LS16(0, 4, 0x3)
5444e97550SJiawen Wu #define   RTL_PHYSR_DP			MS16(3, 0x1)
5544e97550SJiawen Wu #define   RTL_PHYSR_RTLS		MS16(2, 0x1)
5644e97550SJiawen Wu #define RTL_INSR			0x1D
5744e97550SJiawen Wu #define   RTL_INSR_ACCESS		MS16(5, 0x1)
5844e97550SJiawen Wu #define   RTL_INSR_LSC			MS16(4, 0x1)
5944e97550SJiawen Wu #define   RTL_INSR_ANC			MS16(3, 0x1)
6044e97550SJiawen Wu /* Page 0xa46*/
6144e97550SJiawen Wu #define RTL_SCR				0x14
6244e97550SJiawen Wu #define   RTL_SCR_EXTINI		MS16(1, 0x1)
6344e97550SJiawen Wu #define   RTL_SCR_EFUSE			MS16(0, 0x1)
6444e97550SJiawen Wu /* Page 0xa47*/
6544e97550SJiawen Wu /* Page 0xd04*/
6644e97550SJiawen Wu #define RTL_LCR				0x10
6744e97550SJiawen Wu #define RTL_EEELCR			0x11
6844e97550SJiawen Wu #define RTL_LPCR			0x12
6944e97550SJiawen Wu 
7044e97550SJiawen Wu /* INTERNAL PHY CONTROL */
7144e97550SJiawen Wu #define RTL_PAGE_SELECT			31
7244e97550SJiawen Wu #define NGBE_INTERNAL_PHY_OFFSET_MAX	32
7344e97550SJiawen Wu #define NGBE_INTERNAL_PHY_ID		0x000732
7444e97550SJiawen Wu 
7544e97550SJiawen Wu #define NGBE_INTPHY_LED0		0x0010
7644e97550SJiawen Wu #define NGBE_INTPHY_LED1		0x0040
7744e97550SJiawen Wu #define NGBE_INTPHY_LED2		0x2000
7844e97550SJiawen Wu 
7944e97550SJiawen Wu s32 ngbe_read_phy_reg_rtl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
8044e97550SJiawen Wu 			u16 *phy_data);
8144e97550SJiawen Wu s32 ngbe_write_phy_reg_rtl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,
8244e97550SJiawen Wu 			u16 phy_data);
8344e97550SJiawen Wu 
843d0af706SJiawen Wu s32 ngbe_setup_phy_link_rtl(struct ngbe_hw *hw,
853d0af706SJiawen Wu 		u32 speed, bool autoneg_wait_to_complete);
863518df57SJiawen Wu 
873518df57SJiawen Wu s32 ngbe_init_phy_rtl(struct ngbe_hw *hw);
8844e97550SJiawen Wu s32 ngbe_reset_phy_rtl(struct ngbe_hw *hw);
89f40e9f0eSJiawen Wu s32 ngbe_get_phy_advertised_pause_rtl(struct ngbe_hw *hw, u8 *pause_bit);
90f40e9f0eSJiawen Wu s32 ngbe_get_phy_lp_advertised_pause_rtl(struct ngbe_hw *hw, u8 *pause_bit);
91f40e9f0eSJiawen Wu s32 ngbe_set_phy_pause_adv_rtl(struct ngbe_hw *hw, u16 pause_bit);
923d0af706SJiawen Wu s32 ngbe_check_phy_link_rtl(struct ngbe_hw *hw,
933d0af706SJiawen Wu 			u32 *speed, bool *link_up);
94abea8974SJiawen Wu s32 ngbe_set_phy_power_rtl(struct ngbe_hw *hw, bool on);
9544e97550SJiawen Wu 
9644e97550SJiawen Wu #endif /* _NGBE_PHY_RTL_H_ */
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