1f501a195SJiawen Wu /* SPDX-License-Identifier: BSD-3-Clause 2f501a195SJiawen Wu * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd. 3f501a195SJiawen Wu * Copyright(c) 2010-2017 Intel Corporation 4f501a195SJiawen Wu */ 5f501a195SJiawen Wu 6f501a195SJiawen Wu #ifndef _NGBE_MNG_H_ 7f501a195SJiawen Wu #define _NGBE_MNG_H_ 8f501a195SJiawen Wu 9f501a195SJiawen Wu #include "ngbe_type.h" 10f501a195SJiawen Wu 11f501a195SJiawen Wu #define NGBE_PMMBX_QSIZE 64 /* Num of dwords in range */ 12f501a195SJiawen Wu #define NGBE_PMMBX_BSIZE (NGBE_PMMBX_QSIZE * 4) 13506abd4aSJiawen Wu #define NGBE_PMMBX_DATA_SIZE (NGBE_PMMBX_BSIZE - FW_NVM_DATA_OFFSET * 4) 14f501a195SJiawen Wu #define NGBE_HI_COMMAND_TIMEOUT 5000 /* Process HI command limit */ 15f501a195SJiawen Wu 16f501a195SJiawen Wu /* CEM Support */ 17f501a195SJiawen Wu #define FW_CEM_MAX_RETRIES 3 18f501a195SJiawen Wu #define FW_CEM_RESP_STATUS_SUCCESS 0x1 19506abd4aSJiawen Wu #define FW_READ_SHADOW_RAM_CMD 0x31 20506abd4aSJiawen Wu #define FW_READ_SHADOW_RAM_LEN 0x6 219459ea29SJiawen Wu #define FW_WRITE_SHADOW_RAM_CMD 0x33 229459ea29SJiawen Wu #define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ 23ac6c5e9aSJiawen Wu #define FW_PCIE_READ_CMD 0xEC 24ac6c5e9aSJiawen Wu #define FW_PCIE_WRITE_CMD 0xED 25ac6c5e9aSJiawen Wu #define FW_PCIE_BUSMASTER_OFFSET 2 26f501a195SJiawen Wu #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 27506abd4aSJiawen Wu #define FW_NVM_DATA_OFFSET 3 28f501a195SJiawen Wu #define FW_EEPROM_CHECK_STATUS 0xE9 29fbd5ceb0SJiawen Wu #define FW_PHY_LED_CONF 0xF1 305f1ab0d5SJiawen Wu #define FW_READ_SHADOW_RAM_GPIO 0xB4 31*91e64c0eSJiawen Wu #define FW_LLDP_GET_CMD 0xF5 32*91e64c0eSJiawen Wu #define FW_LLDP_SET_CMD_OFF 0xF3 33*91e64c0eSJiawen Wu #define FW_LLDP_SET_CMD_ON 0xF2 34*91e64c0eSJiawen Wu #define FW_CEM_CMD_RESERVED 0X0 35f501a195SJiawen Wu 36f501a195SJiawen Wu #define FW_CHECKSUM_CAP_ST_PASS 0x80658383 37f501a195SJiawen Wu #define FW_CHECKSUM_CAP_ST_FAIL 0x70657376 38f501a195SJiawen Wu 39f501a195SJiawen Wu /* Host Interface Command Structures */ 40f501a195SJiawen Wu struct ngbe_hic_hdr { 41f501a195SJiawen Wu u8 cmd; 42f501a195SJiawen Wu u8 buf_len; 43f501a195SJiawen Wu union { 44f501a195SJiawen Wu u8 cmd_resv; 45f501a195SJiawen Wu u8 ret_status; 46f501a195SJiawen Wu } cmd_or_resp; 47f501a195SJiawen Wu u8 checksum; 48f501a195SJiawen Wu }; 49f501a195SJiawen Wu 50f501a195SJiawen Wu struct ngbe_hic_hdr2_req { 51f501a195SJiawen Wu u8 cmd; 52f501a195SJiawen Wu u8 buf_lenh; 53f501a195SJiawen Wu u8 buf_lenl; 54f501a195SJiawen Wu u8 checksum; 55f501a195SJiawen Wu }; 56f501a195SJiawen Wu 57f501a195SJiawen Wu struct ngbe_hic_hdr2_rsp { 58f501a195SJiawen Wu u8 cmd; 59f501a195SJiawen Wu u8 buf_lenl; 60f501a195SJiawen Wu u8 ret_status; /* 7-5: high bits of buf_len, 4-0: status */ 61f501a195SJiawen Wu u8 checksum; 62f501a195SJiawen Wu }; 63f501a195SJiawen Wu 64f501a195SJiawen Wu union ngbe_hic_hdr2 { 65f501a195SJiawen Wu struct ngbe_hic_hdr2_req req; 66f501a195SJiawen Wu struct ngbe_hic_hdr2_rsp rsp; 67f501a195SJiawen Wu }; 68f501a195SJiawen Wu 69f501a195SJiawen Wu /* These need to be dword aligned */ 70f501a195SJiawen Wu struct ngbe_hic_read_shadow_ram { 71f501a195SJiawen Wu union ngbe_hic_hdr2 hdr; 72f501a195SJiawen Wu u32 address; 73f501a195SJiawen Wu u16 length; 74f501a195SJiawen Wu u16 pad2; 75f501a195SJiawen Wu u16 data; 76f501a195SJiawen Wu u16 pad3; 77f501a195SJiawen Wu }; 78f501a195SJiawen Wu 799459ea29SJiawen Wu struct ngbe_hic_write_shadow_ram { 809459ea29SJiawen Wu union ngbe_hic_hdr2 hdr; 819459ea29SJiawen Wu u32 address; 829459ea29SJiawen Wu u16 length; 839459ea29SJiawen Wu u16 pad2; 849459ea29SJiawen Wu u16 data; 859459ea29SJiawen Wu u16 pad3; 869459ea29SJiawen Wu }; 879459ea29SJiawen Wu 88ac6c5e9aSJiawen Wu struct ngbe_hic_read_pcie { 89ac6c5e9aSJiawen Wu struct ngbe_hic_hdr hdr; 90ac6c5e9aSJiawen Wu u8 lan_id; 91ac6c5e9aSJiawen Wu u8 rsvd; 92ac6c5e9aSJiawen Wu u16 addr; 93ac6c5e9aSJiawen Wu u32 data; 94ac6c5e9aSJiawen Wu }; 95ac6c5e9aSJiawen Wu 96ac6c5e9aSJiawen Wu struct ngbe_hic_write_pcie { 97ac6c5e9aSJiawen Wu struct ngbe_hic_hdr hdr; 98ac6c5e9aSJiawen Wu u8 lan_id; 99ac6c5e9aSJiawen Wu u8 rsvd; 100ac6c5e9aSJiawen Wu u16 addr; 101ac6c5e9aSJiawen Wu u32 data; 102ac6c5e9aSJiawen Wu }; 103ac6c5e9aSJiawen Wu 104*91e64c0eSJiawen Wu struct ngbe_hic_write_lldp { 105*91e64c0eSJiawen Wu struct ngbe_hic_hdr hdr; 106*91e64c0eSJiawen Wu u8 func; 107*91e64c0eSJiawen Wu u8 pad2; 108*91e64c0eSJiawen Wu u16 pad3; 109*91e64c0eSJiawen Wu }; 110*91e64c0eSJiawen Wu 111506abd4aSJiawen Wu s32 ngbe_hic_sr_read(struct ngbe_hw *hw, u32 addr, u8 *buf, int len); 1129459ea29SJiawen Wu s32 ngbe_hic_sr_write(struct ngbe_hw *hw, u32 addr, u8 *buf, int len); 113ac6c5e9aSJiawen Wu s32 ngbe_hic_pcie_read(struct ngbe_hw *hw, u16 addr, u32 *buf, int len); 114ac6c5e9aSJiawen Wu s32 ngbe_hic_pcie_write(struct ngbe_hw *hw, u16 addr, u32 *buf, int len); 1159459ea29SJiawen Wu 116f501a195SJiawen Wu s32 ngbe_hic_check_cap(struct ngbe_hw *hw); 117fbd5ceb0SJiawen Wu s32 ngbe_phy_led_oem_chk(struct ngbe_hw *hw, u32 *data); 118*91e64c0eSJiawen Wu s32 ngbe_hic_get_lldp(struct ngbe_hw *hw); 119*91e64c0eSJiawen Wu s32 ngbe_hic_set_lldp(struct ngbe_hw *hw, bool on); 120fbd5ceb0SJiawen Wu 121f501a195SJiawen Wu #endif /* _NGBE_MNG_H_ */ 122