1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #include <rte_ethdev.h> 6 #include <ethdev_driver.h> 7 #include <rte_malloc.h> 8 9 #include "ionic_logs.h" 10 #include "ionic.h" 11 #include "ionic_dev.h" 12 #include "ionic_mac_api.h" 13 #include "ionic_lif.h" 14 #include "ionic_ethdev.h" 15 #include "ionic_rxtx.h" 16 17 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 18 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 19 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 20 struct rte_eth_dev_info *dev_info); 21 static int ionic_dev_configure(struct rte_eth_dev *dev); 22 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 23 static int ionic_dev_start(struct rte_eth_dev *dev); 24 static int ionic_dev_stop(struct rte_eth_dev *dev); 25 static int ionic_dev_close(struct rte_eth_dev *dev); 26 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 27 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 28 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 29 struct rte_eth_fc_conf *fc_conf); 30 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 31 struct rte_eth_fc_conf *fc_conf); 32 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 33 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 34 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 35 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 36 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 37 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 38 struct rte_eth_rss_conf *rss_conf); 39 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 40 struct rte_eth_rss_conf *rss_conf); 41 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 42 struct rte_eth_stats *stats); 43 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 44 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 45 struct rte_eth_xstat *xstats, unsigned int n); 46 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 47 const uint64_t *ids, uint64_t *values, unsigned int n); 48 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 49 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 50 struct rte_eth_xstat_name *xstats_names, unsigned int size); 51 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 52 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 53 unsigned int limit); 54 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 55 char *fw_version, size_t fw_size); 56 57 static const struct rte_eth_desc_lim rx_desc_lim = { 58 .nb_max = IONIC_MAX_RING_DESC, 59 .nb_min = IONIC_MIN_RING_DESC, 60 .nb_align = 1, 61 }; 62 63 static const struct rte_eth_desc_lim tx_desc_lim_v1 = { 64 .nb_max = IONIC_MAX_RING_DESC, 65 .nb_min = IONIC_MIN_RING_DESC, 66 .nb_align = 1, 67 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 68 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 69 }; 70 71 static const struct eth_dev_ops ionic_eth_dev_ops = { 72 .dev_infos_get = ionic_dev_info_get, 73 .dev_supported_ptypes_get = ionic_dev_supported_ptypes_get, 74 .dev_configure = ionic_dev_configure, 75 .mtu_set = ionic_dev_mtu_set, 76 .dev_start = ionic_dev_start, 77 .dev_stop = ionic_dev_stop, 78 .dev_close = ionic_dev_close, 79 .link_update = ionic_dev_link_update, 80 .dev_set_link_up = ionic_dev_set_link_up, 81 .dev_set_link_down = ionic_dev_set_link_down, 82 .mac_addr_add = ionic_dev_add_mac, 83 .mac_addr_remove = ionic_dev_remove_mac, 84 .mac_addr_set = ionic_dev_set_mac, 85 .vlan_filter_set = ionic_dev_vlan_filter_set, 86 .promiscuous_enable = ionic_dev_promiscuous_enable, 87 .promiscuous_disable = ionic_dev_promiscuous_disable, 88 .allmulticast_enable = ionic_dev_allmulticast_enable, 89 .allmulticast_disable = ionic_dev_allmulticast_disable, 90 .flow_ctrl_get = ionic_flow_ctrl_get, 91 .flow_ctrl_set = ionic_flow_ctrl_set, 92 .rxq_info_get = ionic_rxq_info_get, 93 .txq_info_get = ionic_txq_info_get, 94 .rx_queue_setup = ionic_dev_rx_queue_setup, 95 .rx_queue_release = ionic_dev_rx_queue_release, 96 .rx_queue_start = ionic_dev_rx_queue_start, 97 .rx_queue_stop = ionic_dev_rx_queue_stop, 98 .tx_queue_setup = ionic_dev_tx_queue_setup, 99 .tx_queue_release = ionic_dev_tx_queue_release, 100 .tx_queue_start = ionic_dev_tx_queue_start, 101 .tx_queue_stop = ionic_dev_tx_queue_stop, 102 .vlan_offload_set = ionic_vlan_offload_set, 103 .reta_update = ionic_dev_rss_reta_update, 104 .reta_query = ionic_dev_rss_reta_query, 105 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 106 .rss_hash_update = ionic_dev_rss_hash_update, 107 .stats_get = ionic_dev_stats_get, 108 .stats_reset = ionic_dev_stats_reset, 109 .xstats_get = ionic_dev_xstats_get, 110 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 111 .xstats_reset = ionic_dev_xstats_reset, 112 .xstats_get_names = ionic_dev_xstats_get_names, 113 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 114 .fw_version_get = ionic_dev_fw_version_get, 115 }; 116 117 struct rte_ionic_xstats_name_off { 118 char name[RTE_ETH_XSTATS_NAME_SIZE]; 119 unsigned int offset; 120 }; 121 122 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 123 /* RX */ 124 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 125 rx_ucast_bytes)}, 126 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 127 rx_ucast_packets)}, 128 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 129 rx_mcast_bytes)}, 130 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 131 rx_mcast_packets)}, 132 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 133 rx_bcast_bytes)}, 134 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 135 rx_bcast_packets)}, 136 /* RX drops */ 137 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 138 rx_ucast_drop_bytes)}, 139 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 140 rx_ucast_drop_packets)}, 141 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 142 rx_mcast_drop_bytes)}, 143 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 144 rx_mcast_drop_packets)}, 145 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 146 rx_bcast_drop_bytes)}, 147 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 148 rx_bcast_drop_packets)}, 149 {"rx_dma_error", offsetof(struct ionic_lif_stats, 150 rx_dma_error)}, 151 /* TX */ 152 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 153 tx_ucast_bytes)}, 154 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 155 tx_ucast_packets)}, 156 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 157 tx_mcast_bytes)}, 158 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 159 tx_mcast_packets)}, 160 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 161 tx_bcast_bytes)}, 162 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 163 tx_bcast_packets)}, 164 /* TX drops */ 165 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 166 tx_ucast_drop_bytes)}, 167 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 168 tx_ucast_drop_packets)}, 169 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 170 tx_mcast_drop_bytes)}, 171 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 172 tx_mcast_drop_packets)}, 173 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 174 tx_bcast_drop_bytes)}, 175 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 176 tx_bcast_drop_packets)}, 177 {"tx_dma_error", offsetof(struct ionic_lif_stats, 178 tx_dma_error)}, 179 /* Rx Queue/Ring drops */ 180 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 181 rx_queue_disabled)}, 182 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 183 rx_queue_empty)}, 184 {"rx_queue_error", offsetof(struct ionic_lif_stats, 185 rx_queue_error)}, 186 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 187 rx_desc_fetch_error)}, 188 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 189 rx_desc_data_error)}, 190 /* Tx Queue/Ring drops */ 191 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 192 tx_queue_disabled)}, 193 {"tx_queue_error", offsetof(struct ionic_lif_stats, 194 tx_queue_error)}, 195 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 tx_desc_fetch_error)}, 197 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 198 tx_desc_data_error)}, 199 }; 200 201 #define IONIC_NB_HW_STATS RTE_DIM(rte_ionic_xstats_strings) 202 203 static int 204 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 205 char *fw_version, size_t fw_size) 206 { 207 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 208 struct ionic_adapter *adapter = lif->adapter; 209 int ret; 210 211 ret = snprintf(fw_version, fw_size, "%s", 212 adapter->fw_version); 213 if (ret < 0) 214 return -EINVAL; 215 216 ret += 1; /* add the size of '\0' */ 217 if (fw_size < (size_t)ret) 218 return ret; 219 else 220 return 0; 221 } 222 223 /* 224 * Set device link up, enable tx. 225 */ 226 static int 227 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 228 { 229 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 230 int err; 231 232 IONIC_PRINT_CALL(); 233 234 err = ionic_lif_start(lif); 235 if (err) 236 IONIC_PRINT(ERR, "Could not start lif to set link up"); 237 238 ionic_dev_link_update(lif->eth_dev, 0); 239 240 return err; 241 } 242 243 /* 244 * Set device link down, disable tx. 245 */ 246 static int 247 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 248 { 249 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 250 251 IONIC_PRINT_CALL(); 252 253 ionic_lif_stop(lif); 254 255 ionic_dev_link_update(lif->eth_dev, 0); 256 257 return 0; 258 } 259 260 int 261 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 262 int wait_to_complete __rte_unused) 263 { 264 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 265 struct ionic_adapter *adapter = lif->adapter; 266 struct rte_eth_link link; 267 268 IONIC_PRINT_CALL(); 269 270 /* Initialize */ 271 memset(&link, 0, sizeof(link)); 272 273 if (adapter->idev.port_info->config.an_enable) { 274 link.link_autoneg = RTE_ETH_LINK_AUTONEG; 275 } 276 277 if (!adapter->link_up || 278 !(lif->state & IONIC_LIF_F_UP)) { 279 /* Interface is down */ 280 link.link_status = RTE_ETH_LINK_DOWN; 281 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 282 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 283 } else { 284 /* Interface is up */ 285 link.link_status = RTE_ETH_LINK_UP; 286 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 287 switch (adapter->link_speed) { 288 case 1000: 289 link.link_speed = RTE_ETH_SPEED_NUM_1G; 290 break; 291 case 10000: 292 link.link_speed = RTE_ETH_SPEED_NUM_10G; 293 break; 294 case 25000: 295 link.link_speed = RTE_ETH_SPEED_NUM_25G; 296 break; 297 case 40000: 298 link.link_speed = RTE_ETH_SPEED_NUM_40G; 299 break; 300 case 50000: 301 link.link_speed = RTE_ETH_SPEED_NUM_50G; 302 break; 303 case 100000: 304 link.link_speed = RTE_ETH_SPEED_NUM_100G; 305 break; 306 case 200000: 307 link.link_speed = RTE_ETH_SPEED_NUM_200G; 308 break; 309 default: 310 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 311 break; 312 } 313 } 314 315 return rte_eth_linkstatus_set(eth_dev, &link); 316 } 317 318 /** 319 * Interrupt handler triggered by NIC for handling 320 * specific interrupt. 321 * 322 * @param param 323 * The address of parameter registered before. 324 * 325 * @return 326 * void 327 */ 328 void 329 ionic_dev_interrupt_handler(void *param) 330 { 331 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 332 333 IONIC_PRINT(DEBUG, "->"); 334 335 if (adapter->lif) 336 ionic_notifyq_handler(adapter->lif, -1); 337 } 338 339 static int 340 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 341 { 342 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 343 344 if (lif->state & IONIC_LIF_F_UP) { 345 IONIC_PRINT(ERR, "Stop %s before setting mtu", lif->name); 346 return -EBUSY; 347 } 348 349 /* Note: mtu check against min/max is done by the API */ 350 IONIC_PRINT(INFO, "Setting mtu %u", mtu); 351 352 /* Update the frame size used by the Rx path */ 353 lif->frame_size = mtu + IONIC_ETH_OVERHEAD; 354 355 return 0; 356 } 357 358 static int 359 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 360 struct rte_eth_dev_info *dev_info) 361 { 362 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 363 struct ionic_adapter *adapter = lif->adapter; 364 struct ionic_identity *ident = &adapter->ident; 365 union ionic_lif_config *cfg = &ident->lif.eth.config; 366 367 IONIC_PRINT_CALL(); 368 369 dev_info->max_rx_queues = (uint16_t) 370 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 371 dev_info->max_tx_queues = (uint16_t) 372 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 373 374 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 375 dev_info->min_mtu = RTE_MAX((uint32_t)IONIC_MIN_MTU, 376 rte_le_to_cpu_32(ident->lif.eth.min_mtu)); 377 dev_info->max_mtu = RTE_MIN((uint32_t)IONIC_MAX_MTU, 378 rte_le_to_cpu_32(ident->lif.eth.max_mtu)); 379 dev_info->min_rx_bufsize = dev_info->min_mtu + IONIC_ETH_OVERHEAD; 380 dev_info->max_rx_pktlen = dev_info->max_mtu + IONIC_ETH_OVERHEAD; 381 dev_info->max_lro_pkt_size = 382 eth_dev->data->dev_conf.rxmode.max_lro_pkt_size; 383 384 dev_info->max_mac_addrs = adapter->max_mac_addrs; 385 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 386 dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 387 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 388 389 dev_info->speed_capa = 390 RTE_ETH_LINK_SPEED_10G | 391 RTE_ETH_LINK_SPEED_25G | 392 RTE_ETH_LINK_SPEED_40G | 393 RTE_ETH_LINK_SPEED_50G | 394 RTE_ETH_LINK_SPEED_100G; 395 396 /* 397 * Per-queue capabilities 398 * RTE does not support disabling a feature on a queue if it is 399 * enabled globally on the device. Thus the driver does not advertise 400 * capabilities like RTE_ETH_TX_OFFLOAD_IPV4_CKSUM as per-queue even 401 * though the driver would be otherwise capable of disabling it on 402 * a per-queue basis. 403 */ 404 405 dev_info->rx_queue_offload_capa = 0; 406 dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 407 408 /* 409 * Per-port capabilities 410 * See ionic_set_features to request and check supported features 411 */ 412 413 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 414 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 415 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 416 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 417 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 418 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 419 RTE_ETH_RX_OFFLOAD_SCATTER | 420 RTE_ETH_RX_OFFLOAD_RSS_HASH | 421 0; 422 423 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 424 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 425 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 426 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 427 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 428 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | 429 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 430 RTE_ETH_TX_OFFLOAD_TCP_TSO | 431 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 432 0; 433 434 dev_info->rx_desc_lim = rx_desc_lim; 435 dev_info->tx_desc_lim = tx_desc_lim_v1; 436 437 /* Driver-preferred Rx/Tx parameters */ 438 dev_info->default_rxportconf.burst_size = IONIC_DEF_TXRX_BURST; 439 dev_info->default_txportconf.burst_size = IONIC_DEF_TXRX_BURST; 440 dev_info->default_rxportconf.nb_queues = 1; 441 dev_info->default_txportconf.nb_queues = 1; 442 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 443 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 444 445 dev_info->default_rxconf = (struct rte_eth_rxconf) { 446 /* Packets are always dropped if no desc are available */ 447 .rx_drop_en = 1, 448 }; 449 450 return 0; 451 } 452 453 static int 454 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 455 struct rte_eth_fc_conf *fc_conf) 456 { 457 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 458 struct ionic_adapter *adapter = lif->adapter; 459 struct ionic_dev *idev = &adapter->idev; 460 461 if (idev->port_info) { 462 /* Flow control autoneg not supported */ 463 fc_conf->autoneg = 0; 464 465 if (idev->port_info->config.pause_type) 466 fc_conf->mode = RTE_ETH_FC_FULL; 467 else 468 fc_conf->mode = RTE_ETH_FC_NONE; 469 } 470 471 return 0; 472 } 473 474 static int 475 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 476 struct rte_eth_fc_conf *fc_conf) 477 { 478 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 479 struct ionic_adapter *adapter = lif->adapter; 480 struct ionic_dev *idev = &adapter->idev; 481 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 482 int err; 483 484 if (fc_conf->autoneg) { 485 IONIC_PRINT(WARNING, "Flow control autoneg not supported"); 486 return -ENOTSUP; 487 } 488 489 switch (fc_conf->mode) { 490 case RTE_ETH_FC_NONE: 491 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 492 break; 493 case RTE_ETH_FC_FULL: 494 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 495 break; 496 case RTE_ETH_FC_RX_PAUSE: 497 case RTE_ETH_FC_TX_PAUSE: 498 return -ENOTSUP; 499 } 500 501 ionic_dev_cmd_port_pause(idev, pause_type); 502 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 503 if (err) 504 IONIC_PRINT(WARNING, "Failed to configure flow control"); 505 506 return err; 507 } 508 509 static int 510 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 511 { 512 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 513 514 ionic_lif_configure_vlan_offload(lif, mask); 515 516 ionic_lif_set_features(lif); 517 518 return 0; 519 } 520 521 static int 522 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 523 struct rte_eth_rss_reta_entry64 *reta_conf, 524 uint16_t reta_size) 525 { 526 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 527 struct ionic_adapter *adapter = lif->adapter; 528 struct ionic_identity *ident = &adapter->ident; 529 uint32_t i, j, index, num; 530 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 531 532 IONIC_PRINT_CALL(); 533 534 if (!lif->rss_ind_tbl) { 535 IONIC_PRINT(ERR, "RSS RETA not initialized, " 536 "can't update the table"); 537 return -EINVAL; 538 } 539 540 if (reta_size != tbl_sz) { 541 IONIC_PRINT(ERR, "The size of hash lookup table configured " 542 "(%d) does not match the number hardware can support " 543 "(%d)", 544 reta_size, tbl_sz); 545 return -EINVAL; 546 } 547 548 num = tbl_sz / RTE_ETH_RETA_GROUP_SIZE; 549 550 for (i = 0; i < num; i++) { 551 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) { 552 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 553 index = (i * RTE_ETH_RETA_GROUP_SIZE) + j; 554 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 555 } 556 } 557 } 558 559 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 560 } 561 562 static int 563 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 564 struct rte_eth_rss_reta_entry64 *reta_conf, 565 uint16_t reta_size) 566 { 567 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 568 struct ionic_adapter *adapter = lif->adapter; 569 struct ionic_identity *ident = &adapter->ident; 570 int i, j, num; 571 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 572 573 IONIC_PRINT_CALL(); 574 575 if (reta_size != tbl_sz) { 576 IONIC_PRINT(ERR, "The size of hash lookup table configured " 577 "(%d) does not match the number hardware can support " 578 "(%d)", 579 reta_size, tbl_sz); 580 return -EINVAL; 581 } 582 583 if (!lif->rss_ind_tbl) { 584 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 585 return -EINVAL; 586 } 587 588 num = reta_size / RTE_ETH_RETA_GROUP_SIZE; 589 590 for (i = 0; i < num; i++) { 591 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) { 592 reta_conf->reta[j] = 593 lif->rss_ind_tbl[(i * RTE_ETH_RETA_GROUP_SIZE) + j]; 594 } 595 reta_conf++; 596 } 597 598 return 0; 599 } 600 601 static int 602 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 603 struct rte_eth_rss_conf *rss_conf) 604 { 605 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 606 uint64_t rss_hf = 0; 607 608 IONIC_PRINT_CALL(); 609 610 if (!lif->rss_ind_tbl) { 611 IONIC_PRINT(NOTICE, "RSS not enabled"); 612 return 0; 613 } 614 615 /* Get key value (if not null, rss_key is 40-byte) */ 616 if (rss_conf->rss_key != NULL && 617 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 618 memcpy(rss_conf->rss_key, lif->rss_hash_key, 619 IONIC_RSS_HASH_KEY_SIZE); 620 621 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 622 rss_hf |= RTE_ETH_RSS_IPV4; 623 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 624 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 625 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 626 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 627 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 628 rss_hf |= RTE_ETH_RSS_IPV6; 629 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 630 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP; 631 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 632 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP; 633 634 rss_conf->rss_hf = rss_hf; 635 636 return 0; 637 } 638 639 static int 640 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 641 struct rte_eth_rss_conf *rss_conf) 642 { 643 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 644 uint32_t rss_types = 0; 645 uint8_t *key = NULL; 646 647 IONIC_PRINT_CALL(); 648 649 if (rss_conf->rss_key) 650 key = rss_conf->rss_key; 651 652 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 653 /* 654 * Can't disable rss through hash flags, 655 * if it is enabled by default during init 656 */ 657 if (lif->rss_ind_tbl) 658 return -EINVAL; 659 } else { 660 /* Can't enable rss if disabled by default during init */ 661 if (!lif->rss_ind_tbl) 662 return -EINVAL; 663 664 if (rss_conf->rss_hf & RTE_ETH_RSS_IPV4) 665 rss_types |= IONIC_RSS_TYPE_IPV4; 666 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) 667 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 668 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) 669 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 670 if (rss_conf->rss_hf & RTE_ETH_RSS_IPV6) 671 rss_types |= IONIC_RSS_TYPE_IPV6; 672 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) 673 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 674 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) 675 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 676 677 ionic_lif_rss_config(lif, rss_types, key, NULL); 678 } 679 680 return 0; 681 } 682 683 static int 684 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 685 struct rte_eth_stats *stats) 686 { 687 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 688 689 ionic_lif_get_stats(lif, stats); 690 691 return 0; 692 } 693 694 static int 695 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 696 { 697 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 698 699 IONIC_PRINT_CALL(); 700 701 ionic_lif_reset_stats(lif); 702 703 return 0; 704 } 705 706 static int 707 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 708 struct rte_eth_xstat_name *xstats_names, 709 __rte_unused unsigned int size) 710 { 711 unsigned int i; 712 713 if (xstats_names != NULL) { 714 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 715 snprintf(xstats_names[i].name, 716 sizeof(xstats_names[i].name), 717 "%s", rte_ionic_xstats_strings[i].name); 718 } 719 } 720 721 return IONIC_NB_HW_STATS; 722 } 723 724 static int 725 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 726 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 727 unsigned int limit) 728 { 729 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 730 uint16_t i; 731 732 if (!ids) { 733 if (xstats_names != NULL) { 734 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 735 snprintf(xstats_names[i].name, 736 sizeof(xstats_names[i].name), 737 "%s", rte_ionic_xstats_strings[i].name); 738 } 739 } 740 741 return IONIC_NB_HW_STATS; 742 } 743 744 ionic_dev_xstats_get_names_by_id(eth_dev, NULL, xstats_names_copy, 745 IONIC_NB_HW_STATS); 746 747 for (i = 0; i < limit; i++) { 748 if (ids[i] >= IONIC_NB_HW_STATS) { 749 IONIC_PRINT(ERR, "id value isn't valid"); 750 return -1; 751 } 752 753 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 754 } 755 756 return limit; 757 } 758 759 static int 760 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 761 unsigned int n) 762 { 763 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 764 struct ionic_lif_stats hw_stats; 765 uint16_t i; 766 767 if (n < IONIC_NB_HW_STATS) 768 return IONIC_NB_HW_STATS; 769 770 ionic_lif_get_hw_stats(lif, &hw_stats); 771 772 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 773 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 774 rte_ionic_xstats_strings[i].offset); 775 xstats[i].id = i; 776 } 777 778 return IONIC_NB_HW_STATS; 779 } 780 781 static int 782 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 783 uint64_t *values, unsigned int n) 784 { 785 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 786 struct ionic_lif_stats hw_stats; 787 uint64_t values_copy[IONIC_NB_HW_STATS]; 788 uint16_t i; 789 790 if (!ids) { 791 if (!ids && n < IONIC_NB_HW_STATS) 792 return IONIC_NB_HW_STATS; 793 794 ionic_lif_get_hw_stats(lif, &hw_stats); 795 796 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 797 values[i] = *(uint64_t *)(((char *)&hw_stats) + 798 rte_ionic_xstats_strings[i].offset); 799 } 800 801 return IONIC_NB_HW_STATS; 802 } 803 804 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 805 IONIC_NB_HW_STATS); 806 807 for (i = 0; i < n; i++) { 808 if (ids[i] >= IONIC_NB_HW_STATS) { 809 IONIC_PRINT(ERR, "id value isn't valid"); 810 return -1; 811 } 812 813 values[i] = values_copy[ids[i]]; 814 } 815 816 return n; 817 } 818 819 static int 820 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 821 { 822 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 823 824 ionic_lif_reset_hw_stats(lif); 825 826 return 0; 827 } 828 829 static int 830 ionic_dev_configure(struct rte_eth_dev *eth_dev) 831 { 832 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 833 834 IONIC_PRINT_CALL(); 835 836 ionic_lif_configure(lif); 837 838 return 0; 839 } 840 841 static inline uint32_t 842 ionic_parse_link_speeds(uint16_t link_speeds) 843 { 844 if (link_speeds & RTE_ETH_LINK_SPEED_100G) 845 return 100000; 846 else if (link_speeds & RTE_ETH_LINK_SPEED_50G) 847 return 50000; 848 else if (link_speeds & RTE_ETH_LINK_SPEED_40G) 849 return 40000; 850 else if (link_speeds & RTE_ETH_LINK_SPEED_25G) 851 return 25000; 852 else if (link_speeds & RTE_ETH_LINK_SPEED_10G) 853 return 10000; 854 else 855 return 0; 856 } 857 858 /* 859 * Configure device link speed and setup link. 860 * It returns 0 on success. 861 */ 862 static int 863 ionic_dev_start(struct rte_eth_dev *eth_dev) 864 { 865 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 866 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 867 struct ionic_adapter *adapter = lif->adapter; 868 struct ionic_dev *idev = &adapter->idev; 869 uint32_t speed = 0, allowed_speeds; 870 uint8_t an_enable; 871 int err; 872 873 IONIC_PRINT_CALL(); 874 875 allowed_speeds = 876 RTE_ETH_LINK_SPEED_FIXED | 877 RTE_ETH_LINK_SPEED_10G | 878 RTE_ETH_LINK_SPEED_25G | 879 RTE_ETH_LINK_SPEED_40G | 880 RTE_ETH_LINK_SPEED_50G | 881 RTE_ETH_LINK_SPEED_100G; 882 883 if (dev_conf->link_speeds & ~allowed_speeds) { 884 IONIC_PRINT(ERR, "Invalid link setting"); 885 return -EINVAL; 886 } 887 888 if (dev_conf->lpbk_mode) 889 IONIC_PRINT(WARNING, "Loopback mode not supported"); 890 891 /* Re-set features in case SG flag was added in rx_queue_setup() */ 892 err = ionic_lif_set_features(lif); 893 if (err) { 894 IONIC_PRINT(ERR, "Cannot set LIF features: %d", err); 895 return err; 896 } 897 898 lif->frame_size = eth_dev->data->mtu + IONIC_ETH_OVERHEAD; 899 900 err = ionic_lif_change_mtu(lif, eth_dev->data->mtu); 901 if (err) { 902 IONIC_PRINT(ERR, "Cannot set LIF frame size %u: %d", 903 lif->frame_size, err); 904 return err; 905 } 906 907 err = ionic_lif_start(lif); 908 if (err) { 909 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 910 return err; 911 } 912 913 /* Configure link */ 914 an_enable = (dev_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) == 0; 915 916 ionic_dev_cmd_port_autoneg(idev, an_enable); 917 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 918 if (err) 919 IONIC_PRINT(WARNING, "Failed to %s autonegotiation", 920 an_enable ? "enable" : "disable"); 921 922 if (!an_enable) 923 speed = ionic_parse_link_speeds(dev_conf->link_speeds); 924 if (speed) { 925 ionic_dev_cmd_port_speed(idev, speed); 926 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 927 if (err) 928 IONIC_PRINT(WARNING, "Failed to set link speed %u", 929 speed); 930 } 931 932 if (lif->hw_features & IONIC_ETH_HW_RX_SG) 933 eth_dev->rx_pkt_burst = &ionic_recv_pkts_sg; 934 else 935 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 936 937 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 938 eth_dev->tx_pkt_burst = &ionic_xmit_pkts_sg; 939 else 940 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 941 942 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 943 944 ionic_dev_link_update(eth_dev, 0); 945 946 return 0; 947 } 948 949 /* 950 * Stop device: disable rx and tx functions to allow for reconfiguring. 951 */ 952 static int 953 ionic_dev_stop(struct rte_eth_dev *eth_dev) 954 { 955 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 956 957 IONIC_PRINT_CALL(); 958 959 ionic_lif_stop(lif); 960 961 return 0; 962 } 963 964 /* 965 * Reset and stop device. 966 */ 967 static int 968 ionic_dev_close(struct rte_eth_dev *eth_dev) 969 { 970 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 971 struct ionic_adapter *adapter = lif->adapter; 972 973 IONIC_PRINT_CALL(); 974 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 975 return 0; 976 977 ionic_lif_stop(lif); 978 979 ionic_lif_free_queues(lif); 980 981 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 982 if (adapter->intf->unconfigure_intr) 983 (*adapter->intf->unconfigure_intr)(adapter); 984 985 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 986 987 ionic_port_reset(adapter); 988 ionic_reset(adapter); 989 if (adapter->intf->unmap_bars) 990 (*adapter->intf->unmap_bars)(adapter); 991 992 rte_free(adapter); 993 994 return 0; 995 } 996 997 int 998 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 999 { 1000 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1001 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 1002 int err; 1003 1004 IONIC_PRINT_CALL(); 1005 1006 eth_dev->dev_ops = &ionic_eth_dev_ops; 1007 eth_dev->rx_descriptor_status = ionic_dev_rx_descriptor_status; 1008 eth_dev->tx_descriptor_status = ionic_dev_tx_descriptor_status; 1009 1010 /* Multi-process not supported, primary does initialization anyway */ 1011 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1012 return 0; 1013 1014 if (adapter->intf->copy_bus_info) 1015 (*adapter->intf->copy_bus_info)(adapter, eth_dev); 1016 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1017 1018 lif->eth_dev = eth_dev; 1019 lif->adapter = adapter; 1020 adapter->lif = lif; 1021 1022 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1023 adapter->max_mac_addrs); 1024 1025 /* Allocate memory for storing MAC addresses */ 1026 eth_dev->data->mac_addrs = rte_calloc("ionic", 1027 adapter->max_mac_addrs, 1028 RTE_ETHER_ADDR_LEN, 1029 RTE_CACHE_LINE_SIZE); 1030 if (eth_dev->data->mac_addrs == NULL) { 1031 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1032 "store MAC addresses", 1033 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1034 err = -ENOMEM; 1035 goto err; 1036 } 1037 1038 err = ionic_lif_alloc(lif); 1039 if (err) { 1040 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1041 err); 1042 goto err; 1043 } 1044 1045 err = ionic_lif_init(lif); 1046 if (err) { 1047 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1048 goto err_free_lif; 1049 } 1050 1051 /* Copy the MAC address */ 1052 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1053 ð_dev->data->mac_addrs[0]); 1054 1055 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1056 1057 return 0; 1058 1059 err_free_lif: 1060 ionic_lif_free(lif); 1061 err: 1062 return err; 1063 } 1064 1065 static int 1066 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1067 { 1068 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1069 struct ionic_adapter *adapter = lif->adapter; 1070 1071 IONIC_PRINT_CALL(); 1072 1073 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1074 return 0; 1075 1076 adapter->lif = NULL; 1077 1078 ionic_lif_deinit(lif); 1079 ionic_lif_free(lif); 1080 1081 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1082 ionic_lif_reset(lif); 1083 1084 return 0; 1085 } 1086 1087 int 1088 eth_ionic_dev_probe(void *bus_dev, struct rte_device *rte_dev, 1089 struct ionic_bars *bars, const struct ionic_dev_intf *intf, 1090 uint16_t device_id, uint16_t vendor_id) 1091 { 1092 char name[RTE_ETH_NAME_MAX_LEN]; 1093 struct ionic_adapter *adapter; 1094 struct ionic_hw *hw; 1095 unsigned long i; 1096 int err; 1097 1098 /* Check structs (trigger error at compilation time) */ 1099 ionic_struct_size_checks(); 1100 1101 /* Multi-process not supported */ 1102 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1103 err = -EPERM; 1104 goto err; 1105 } 1106 1107 adapter = rte_zmalloc("ionic", sizeof(*adapter), RTE_CACHE_LINE_SIZE); 1108 if (!adapter) { 1109 IONIC_PRINT(ERR, "OOM"); 1110 err = -ENOMEM; 1111 goto err; 1112 } 1113 1114 adapter->bus_dev = bus_dev; 1115 hw = &adapter->hw; 1116 1117 /* Vendor and Device ID need to be set before init of shared code */ 1118 hw->device_id = device_id; 1119 hw->vendor_id = vendor_id; 1120 1121 err = ionic_init_mac(hw); 1122 if (err != 0) { 1123 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1124 err = -EIO; 1125 goto err_free_adapter; 1126 } 1127 1128 adapter->bars.num_bars = bars->num_bars; 1129 for (i = 0; i < bars->num_bars; i++) { 1130 adapter->bars.bar[i].vaddr = bars->bar[i].vaddr; 1131 adapter->bars.bar[i].bus_addr = bars->bar[i].bus_addr; 1132 adapter->bars.bar[i].len = bars->bar[i].len; 1133 } 1134 1135 if (intf->setup == NULL) { 1136 IONIC_PRINT(ERR, "Device setup function is mandatory"); 1137 goto err_free_adapter; 1138 } 1139 1140 adapter->intf = intf; 1141 1142 /* Parse device arguments */ 1143 if (adapter->intf->devargs) { 1144 err = (*adapter->intf->devargs)(adapter, rte_dev->devargs); 1145 if (err) { 1146 IONIC_PRINT(ERR, "Cannot parse device arguments"); 1147 goto err_free_adapter; 1148 } 1149 } 1150 1151 /* Discover ionic dev resources */ 1152 err = ionic_setup(adapter); 1153 if (err) { 1154 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1155 goto err_free_adapter; 1156 } 1157 1158 err = ionic_identify(adapter); 1159 if (err) { 1160 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1161 err); 1162 goto err_free_adapter; 1163 } 1164 1165 err = ionic_init(adapter); 1166 if (err) { 1167 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1168 goto err_free_adapter; 1169 } 1170 1171 /* Configure the ports */ 1172 err = ionic_port_identify(adapter); 1173 if (err) { 1174 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1175 err); 1176 goto err_free_adapter; 1177 } 1178 1179 err = ionic_port_init(adapter); 1180 if (err) { 1181 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1182 goto err_free_adapter; 1183 } 1184 1185 /* Configure LIFs */ 1186 err = ionic_lif_identify(adapter); 1187 if (err) { 1188 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1189 goto err_free_adapter; 1190 } 1191 1192 /* Allocate and init LIFs */ 1193 err = ionic_lifs_size(adapter); 1194 if (err) { 1195 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1196 goto err_free_adapter; 1197 } 1198 1199 adapter->max_mac_addrs = 1200 rte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters); 1201 1202 if (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) { 1203 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1204 rte_le_to_cpu_32(adapter->ident.dev.nlifs)); 1205 goto err_free_adapter; 1206 } 1207 1208 snprintf(name, sizeof(name), "%s_lif", rte_dev->name); 1209 err = rte_eth_dev_create(rte_dev, name, sizeof(struct ionic_lif), 1210 NULL, NULL, eth_ionic_dev_init, adapter); 1211 if (err) { 1212 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1213 goto err_free_adapter; 1214 } 1215 1216 if (adapter->intf->configure_intr) { 1217 err = (*adapter->intf->configure_intr)(adapter); 1218 if (err) { 1219 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1220 goto err_free_adapter; 1221 } 1222 } 1223 1224 return 0; 1225 1226 err_free_adapter: 1227 rte_free(adapter); 1228 err: 1229 return err; 1230 } 1231 1232 int 1233 eth_ionic_dev_remove(struct rte_device *rte_dev) 1234 { 1235 char name[RTE_ETH_NAME_MAX_LEN]; 1236 struct rte_eth_dev *eth_dev; 1237 1238 /* Adapter lookup is using the eth_dev name */ 1239 snprintf(name, sizeof(name), "%s_lif", rte_dev->name); 1240 1241 eth_dev = rte_eth_dev_allocated(name); 1242 if (eth_dev) 1243 ionic_dev_close(eth_dev); 1244 else 1245 IONIC_PRINT(DEBUG, "Cannot find device %s", rte_dev->name); 1246 1247 return 0; 1248 } 1249 1250 RTE_LOG_REGISTER_DEFAULT(ionic_logtype, NOTICE); 1251