1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static int ionic_dev_stop(struct rte_eth_dev *dev); 28 static int ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 32 struct rte_eth_fc_conf *fc_conf); 33 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 36 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 37 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 38 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_conf *rss_conf); 42 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 45 struct rte_eth_stats *stats); 46 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 47 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 48 struct rte_eth_xstat *xstats, unsigned int n); 49 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 50 const uint64_t *ids, uint64_t *values, unsigned int n); 51 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 52 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 53 struct rte_eth_xstat_name *xstats_names, unsigned int size); 54 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 55 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 56 unsigned int limit); 57 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 58 char *fw_version, size_t fw_size); 59 60 static const struct rte_pci_id pci_id_ionic_map[] = { 61 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 62 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 64 { .vendor_id = 0, /* sentinel */ }, 65 }; 66 67 static const struct rte_eth_desc_lim rx_desc_lim = { 68 .nb_max = IONIC_MAX_RING_DESC, 69 .nb_min = IONIC_MIN_RING_DESC, 70 .nb_align = 1, 71 }; 72 73 static const struct rte_eth_desc_lim tx_desc_lim_v1 = { 74 .nb_max = IONIC_MAX_RING_DESC, 75 .nb_min = IONIC_MIN_RING_DESC, 76 .nb_align = 1, 77 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 78 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 79 }; 80 81 static const struct eth_dev_ops ionic_eth_dev_ops = { 82 .dev_infos_get = ionic_dev_info_get, 83 .dev_configure = ionic_dev_configure, 84 .mtu_set = ionic_dev_mtu_set, 85 .dev_start = ionic_dev_start, 86 .dev_stop = ionic_dev_stop, 87 .dev_close = ionic_dev_close, 88 .link_update = ionic_dev_link_update, 89 .dev_set_link_up = ionic_dev_set_link_up, 90 .dev_set_link_down = ionic_dev_set_link_down, 91 .mac_addr_add = ionic_dev_add_mac, 92 .mac_addr_remove = ionic_dev_remove_mac, 93 .mac_addr_set = ionic_dev_set_mac, 94 .vlan_filter_set = ionic_dev_vlan_filter_set, 95 .promiscuous_enable = ionic_dev_promiscuous_enable, 96 .promiscuous_disable = ionic_dev_promiscuous_disable, 97 .allmulticast_enable = ionic_dev_allmulticast_enable, 98 .allmulticast_disable = ionic_dev_allmulticast_disable, 99 .flow_ctrl_get = ionic_flow_ctrl_get, 100 .flow_ctrl_set = ionic_flow_ctrl_set, 101 .rxq_info_get = ionic_rxq_info_get, 102 .txq_info_get = ionic_txq_info_get, 103 .rx_queue_setup = ionic_dev_rx_queue_setup, 104 .rx_queue_release = ionic_dev_rx_queue_release, 105 .rx_queue_start = ionic_dev_rx_queue_start, 106 .rx_queue_stop = ionic_dev_rx_queue_stop, 107 .tx_queue_setup = ionic_dev_tx_queue_setup, 108 .tx_queue_release = ionic_dev_tx_queue_release, 109 .tx_queue_start = ionic_dev_tx_queue_start, 110 .tx_queue_stop = ionic_dev_tx_queue_stop, 111 .vlan_offload_set = ionic_vlan_offload_set, 112 .reta_update = ionic_dev_rss_reta_update, 113 .reta_query = ionic_dev_rss_reta_query, 114 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 115 .rss_hash_update = ionic_dev_rss_hash_update, 116 .stats_get = ionic_dev_stats_get, 117 .stats_reset = ionic_dev_stats_reset, 118 .xstats_get = ionic_dev_xstats_get, 119 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 120 .xstats_reset = ionic_dev_xstats_reset, 121 .xstats_get_names = ionic_dev_xstats_get_names, 122 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 123 .fw_version_get = ionic_dev_fw_version_get, 124 }; 125 126 struct rte_ionic_xstats_name_off { 127 char name[RTE_ETH_XSTATS_NAME_SIZE]; 128 unsigned int offset; 129 }; 130 131 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 132 /* RX */ 133 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 134 rx_ucast_bytes)}, 135 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 136 rx_ucast_packets)}, 137 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 138 rx_mcast_bytes)}, 139 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 140 rx_mcast_packets)}, 141 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 142 rx_bcast_bytes)}, 143 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 144 rx_bcast_packets)}, 145 /* RX drops */ 146 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 147 rx_ucast_drop_bytes)}, 148 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 149 rx_ucast_drop_packets)}, 150 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 151 rx_mcast_drop_bytes)}, 152 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 153 rx_mcast_drop_packets)}, 154 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 155 rx_bcast_drop_bytes)}, 156 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 157 rx_bcast_drop_packets)}, 158 {"rx_dma_error", offsetof(struct ionic_lif_stats, 159 rx_dma_error)}, 160 /* TX */ 161 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 162 tx_ucast_bytes)}, 163 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 164 tx_ucast_packets)}, 165 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 166 tx_mcast_bytes)}, 167 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 168 tx_mcast_packets)}, 169 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 170 tx_bcast_bytes)}, 171 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 172 tx_bcast_packets)}, 173 /* TX drops */ 174 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 175 tx_ucast_drop_bytes)}, 176 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 177 tx_ucast_drop_packets)}, 178 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 179 tx_mcast_drop_bytes)}, 180 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 181 tx_mcast_drop_packets)}, 182 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 183 tx_bcast_drop_bytes)}, 184 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 185 tx_bcast_drop_packets)}, 186 {"tx_dma_error", offsetof(struct ionic_lif_stats, 187 tx_dma_error)}, 188 /* Rx Queue/Ring drops */ 189 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 190 rx_queue_disabled)}, 191 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 192 rx_queue_empty)}, 193 {"rx_queue_error", offsetof(struct ionic_lif_stats, 194 rx_queue_error)}, 195 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 rx_desc_fetch_error)}, 197 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 198 rx_desc_data_error)}, 199 /* Tx Queue/Ring drops */ 200 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 201 tx_queue_disabled)}, 202 {"tx_queue_error", offsetof(struct ionic_lif_stats, 203 tx_queue_error)}, 204 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 205 tx_desc_fetch_error)}, 206 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 207 tx_desc_data_error)}, 208 }; 209 210 #define IONIC_NB_HW_STATS RTE_DIM(rte_ionic_xstats_strings) 211 212 static int 213 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 214 char *fw_version, size_t fw_size) 215 { 216 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 217 struct ionic_adapter *adapter = lif->adapter; 218 int ret; 219 220 ret = snprintf(fw_version, fw_size, "%s", 221 adapter->fw_version); 222 if (ret < 0) 223 return -EINVAL; 224 225 ret += 1; /* add the size of '\0' */ 226 if (fw_size < (size_t)ret) 227 return ret; 228 else 229 return 0; 230 } 231 232 /* 233 * Set device link up, enable tx. 234 */ 235 static int 236 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 237 { 238 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 239 int err; 240 241 IONIC_PRINT_CALL(); 242 243 err = ionic_lif_start(lif); 244 if (err) 245 IONIC_PRINT(ERR, "Could not start lif to set link up"); 246 247 ionic_dev_link_update(lif->eth_dev, 0); 248 249 return err; 250 } 251 252 /* 253 * Set device link down, disable tx. 254 */ 255 static int 256 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 257 { 258 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 259 260 IONIC_PRINT_CALL(); 261 262 ionic_lif_stop(lif); 263 264 ionic_dev_link_update(lif->eth_dev, 0); 265 266 return 0; 267 } 268 269 int 270 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 271 int wait_to_complete __rte_unused) 272 { 273 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 274 struct ionic_adapter *adapter = lif->adapter; 275 struct rte_eth_link link; 276 277 IONIC_PRINT_CALL(); 278 279 /* Initialize */ 280 memset(&link, 0, sizeof(link)); 281 282 if (adapter->idev.port_info->config.an_enable) { 283 link.link_autoneg = ETH_LINK_AUTONEG; 284 } 285 286 if (!adapter->link_up || 287 !(lif->state & IONIC_LIF_F_UP)) { 288 /* Interface is down */ 289 link.link_status = ETH_LINK_DOWN; 290 link.link_duplex = ETH_LINK_HALF_DUPLEX; 291 link.link_speed = ETH_SPEED_NUM_NONE; 292 } else { 293 /* Interface is up */ 294 link.link_status = ETH_LINK_UP; 295 link.link_duplex = ETH_LINK_FULL_DUPLEX; 296 switch (adapter->link_speed) { 297 case 10000: 298 link.link_speed = ETH_SPEED_NUM_10G; 299 break; 300 case 25000: 301 link.link_speed = ETH_SPEED_NUM_25G; 302 break; 303 case 40000: 304 link.link_speed = ETH_SPEED_NUM_40G; 305 break; 306 case 50000: 307 link.link_speed = ETH_SPEED_NUM_50G; 308 break; 309 case 100000: 310 link.link_speed = ETH_SPEED_NUM_100G; 311 break; 312 default: 313 link.link_speed = ETH_SPEED_NUM_NONE; 314 break; 315 } 316 } 317 318 return rte_eth_linkstatus_set(eth_dev, &link); 319 } 320 321 /** 322 * Interrupt handler triggered by NIC for handling 323 * specific interrupt. 324 * 325 * @param param 326 * The address of parameter registered before. 327 * 328 * @return 329 * void 330 */ 331 static void 332 ionic_dev_interrupt_handler(void *param) 333 { 334 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 335 336 IONIC_PRINT(DEBUG, "->"); 337 338 if (adapter->lif) 339 ionic_notifyq_handler(adapter->lif, -1); 340 } 341 342 static int 343 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 344 { 345 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 346 int err; 347 348 IONIC_PRINT_CALL(); 349 350 /* 351 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 352 * is done by the API. 353 */ 354 355 err = ionic_lif_change_mtu(lif, mtu); 356 if (err) 357 return err; 358 359 return 0; 360 } 361 362 static int 363 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 364 struct rte_eth_dev_info *dev_info) 365 { 366 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 367 struct ionic_adapter *adapter = lif->adapter; 368 struct ionic_identity *ident = &adapter->ident; 369 union ionic_lif_config *cfg = &ident->lif.eth.config; 370 371 IONIC_PRINT_CALL(); 372 373 dev_info->max_rx_queues = (uint16_t) 374 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 375 dev_info->max_tx_queues = (uint16_t) 376 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 377 378 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 379 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 380 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 381 dev_info->max_mac_addrs = adapter->max_mac_addrs; 382 dev_info->min_mtu = IONIC_MIN_MTU; 383 dev_info->max_mtu = IONIC_MAX_MTU; 384 385 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 386 dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 387 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 388 389 dev_info->speed_capa = 390 ETH_LINK_SPEED_10G | 391 ETH_LINK_SPEED_25G | 392 ETH_LINK_SPEED_40G | 393 ETH_LINK_SPEED_50G | 394 ETH_LINK_SPEED_100G; 395 396 /* 397 * Per-queue capabilities 398 * RTE does not support disabling a feature on a queue if it is 399 * enabled globally on the device. Thus the driver does not advertise 400 * capabilities like DEV_TX_OFFLOAD_IPV4_CKSUM as per-queue even 401 * though the driver would be otherwise capable of disabling it on 402 * a per-queue basis. 403 */ 404 405 dev_info->rx_queue_offload_capa = 0; 406 dev_info->tx_queue_offload_capa = 0; 407 408 /* 409 * Per-port capabilities 410 * See ionic_set_features to request and check supported features 411 */ 412 413 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 414 DEV_RX_OFFLOAD_IPV4_CKSUM | 415 DEV_RX_OFFLOAD_UDP_CKSUM | 416 DEV_RX_OFFLOAD_TCP_CKSUM | 417 DEV_RX_OFFLOAD_JUMBO_FRAME | 418 DEV_RX_OFFLOAD_VLAN_FILTER | 419 DEV_RX_OFFLOAD_VLAN_STRIP | 420 DEV_RX_OFFLOAD_SCATTER | 421 DEV_RX_OFFLOAD_RSS_HASH | 422 0; 423 424 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 425 DEV_TX_OFFLOAD_IPV4_CKSUM | 426 DEV_TX_OFFLOAD_UDP_CKSUM | 427 DEV_TX_OFFLOAD_TCP_CKSUM | 428 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 429 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 430 DEV_TX_OFFLOAD_MULTI_SEGS | 431 DEV_TX_OFFLOAD_TCP_TSO | 432 DEV_TX_OFFLOAD_VLAN_INSERT | 433 0; 434 435 dev_info->rx_desc_lim = rx_desc_lim; 436 dev_info->tx_desc_lim = tx_desc_lim_v1; 437 438 /* Driver-preferred Rx/Tx parameters */ 439 dev_info->default_rxportconf.burst_size = 32; 440 dev_info->default_txportconf.burst_size = 32; 441 dev_info->default_rxportconf.nb_queues = 1; 442 dev_info->default_txportconf.nb_queues = 1; 443 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 444 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 445 446 dev_info->default_rxconf = (struct rte_eth_rxconf) { 447 /* Packets are always dropped if no desc are available */ 448 .rx_drop_en = 1, 449 }; 450 451 return 0; 452 } 453 454 static int 455 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 456 struct rte_eth_fc_conf *fc_conf) 457 { 458 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 459 struct ionic_adapter *adapter = lif->adapter; 460 struct ionic_dev *idev = &adapter->idev; 461 462 if (idev->port_info) { 463 /* Flow control autoneg not supported */ 464 fc_conf->autoneg = 0; 465 466 if (idev->port_info->config.pause_type) 467 fc_conf->mode = RTE_FC_FULL; 468 else 469 fc_conf->mode = RTE_FC_NONE; 470 } 471 472 return 0; 473 } 474 475 static int 476 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 477 struct rte_eth_fc_conf *fc_conf) 478 { 479 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 480 struct ionic_adapter *adapter = lif->adapter; 481 struct ionic_dev *idev = &adapter->idev; 482 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 483 int err; 484 485 if (fc_conf->autoneg) { 486 IONIC_PRINT(WARNING, "Flow control autoneg not supported"); 487 return -ENOTSUP; 488 } 489 490 switch (fc_conf->mode) { 491 case RTE_FC_NONE: 492 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 493 break; 494 case RTE_FC_FULL: 495 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 496 break; 497 case RTE_FC_RX_PAUSE: 498 case RTE_FC_TX_PAUSE: 499 return -ENOTSUP; 500 } 501 502 ionic_dev_cmd_port_pause(idev, pause_type); 503 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 504 if (err) 505 IONIC_PRINT(WARNING, "Failed to configure flow control"); 506 507 return err; 508 } 509 510 static int 511 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 512 { 513 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 514 515 ionic_lif_configure_vlan_offload(lif, mask); 516 517 ionic_lif_set_features(lif); 518 519 return 0; 520 } 521 522 static int 523 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 524 struct rte_eth_rss_reta_entry64 *reta_conf, 525 uint16_t reta_size) 526 { 527 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 528 struct ionic_adapter *adapter = lif->adapter; 529 struct ionic_identity *ident = &adapter->ident; 530 uint32_t i, j, index, num; 531 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 532 533 IONIC_PRINT_CALL(); 534 535 if (!lif->rss_ind_tbl) { 536 IONIC_PRINT(ERR, "RSS RETA not initialized, " 537 "can't update the table"); 538 return -EINVAL; 539 } 540 541 if (reta_size != tbl_sz) { 542 IONIC_PRINT(ERR, "The size of hash lookup table configured " 543 "(%d) does not match the number hardware can support " 544 "(%d)", 545 reta_size, tbl_sz); 546 return -EINVAL; 547 } 548 549 num = tbl_sz / RTE_RETA_GROUP_SIZE; 550 551 for (i = 0; i < num; i++) { 552 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 553 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 554 index = (i * RTE_RETA_GROUP_SIZE) + j; 555 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 556 } 557 } 558 } 559 560 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 561 } 562 563 static int 564 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 565 struct rte_eth_rss_reta_entry64 *reta_conf, 566 uint16_t reta_size) 567 { 568 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 569 struct ionic_adapter *adapter = lif->adapter; 570 struct ionic_identity *ident = &adapter->ident; 571 int i, num; 572 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 573 574 IONIC_PRINT_CALL(); 575 576 if (reta_size != tbl_sz) { 577 IONIC_PRINT(ERR, "The size of hash lookup table configured " 578 "(%d) does not match the number hardware can support " 579 "(%d)", 580 reta_size, tbl_sz); 581 return -EINVAL; 582 } 583 584 if (!lif->rss_ind_tbl) { 585 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 586 return -EINVAL; 587 } 588 589 num = reta_size / RTE_RETA_GROUP_SIZE; 590 591 for (i = 0; i < num; i++) { 592 memcpy(reta_conf->reta, 593 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 594 RTE_RETA_GROUP_SIZE); 595 reta_conf++; 596 } 597 598 return 0; 599 } 600 601 static int 602 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 603 struct rte_eth_rss_conf *rss_conf) 604 { 605 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 606 uint64_t rss_hf = 0; 607 608 IONIC_PRINT_CALL(); 609 610 if (!lif->rss_ind_tbl) { 611 IONIC_PRINT(NOTICE, "RSS not enabled"); 612 return 0; 613 } 614 615 /* Get key value (if not null, rss_key is 40-byte) */ 616 if (rss_conf->rss_key != NULL && 617 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 618 memcpy(rss_conf->rss_key, lif->rss_hash_key, 619 IONIC_RSS_HASH_KEY_SIZE); 620 621 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 622 rss_hf |= ETH_RSS_IPV4; 623 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 624 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 625 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 626 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 627 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 628 rss_hf |= ETH_RSS_IPV6; 629 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 630 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 631 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 632 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 633 634 rss_conf->rss_hf = rss_hf; 635 636 return 0; 637 } 638 639 static int 640 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 641 struct rte_eth_rss_conf *rss_conf) 642 { 643 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 644 uint32_t rss_types = 0; 645 uint8_t *key = NULL; 646 647 IONIC_PRINT_CALL(); 648 649 if (rss_conf->rss_key) 650 key = rss_conf->rss_key; 651 652 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 653 /* 654 * Can't disable rss through hash flags, 655 * if it is enabled by default during init 656 */ 657 if (lif->rss_ind_tbl) 658 return -EINVAL; 659 } else { 660 /* Can't enable rss if disabled by default during init */ 661 if (!lif->rss_ind_tbl) 662 return -EINVAL; 663 664 if (rss_conf->rss_hf & ETH_RSS_IPV4) 665 rss_types |= IONIC_RSS_TYPE_IPV4; 666 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 667 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 668 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 669 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 670 if (rss_conf->rss_hf & ETH_RSS_IPV6) 671 rss_types |= IONIC_RSS_TYPE_IPV6; 672 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 673 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 674 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 675 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 676 677 ionic_lif_rss_config(lif, rss_types, key, NULL); 678 } 679 680 return 0; 681 } 682 683 static int 684 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 685 struct rte_eth_stats *stats) 686 { 687 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 688 689 ionic_lif_get_stats(lif, stats); 690 691 return 0; 692 } 693 694 static int 695 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 696 { 697 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 698 699 IONIC_PRINT_CALL(); 700 701 ionic_lif_reset_stats(lif); 702 703 return 0; 704 } 705 706 static int 707 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 708 struct rte_eth_xstat_name *xstats_names, 709 __rte_unused unsigned int size) 710 { 711 unsigned int i; 712 713 if (xstats_names != NULL) { 714 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 715 snprintf(xstats_names[i].name, 716 sizeof(xstats_names[i].name), 717 "%s", rte_ionic_xstats_strings[i].name); 718 } 719 } 720 721 return IONIC_NB_HW_STATS; 722 } 723 724 static int 725 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 726 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 727 unsigned int limit) 728 { 729 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 730 uint16_t i; 731 732 if (!ids) { 733 if (xstats_names != NULL) { 734 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 735 snprintf(xstats_names[i].name, 736 sizeof(xstats_names[i].name), 737 "%s", rte_ionic_xstats_strings[i].name); 738 } 739 } 740 741 return IONIC_NB_HW_STATS; 742 } 743 744 ionic_dev_xstats_get_names_by_id(eth_dev, NULL, xstats_names_copy, 745 IONIC_NB_HW_STATS); 746 747 for (i = 0; i < limit; i++) { 748 if (ids[i] >= IONIC_NB_HW_STATS) { 749 IONIC_PRINT(ERR, "id value isn't valid"); 750 return -1; 751 } 752 753 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 754 } 755 756 return limit; 757 } 758 759 static int 760 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 761 unsigned int n) 762 { 763 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 764 struct ionic_lif_stats hw_stats; 765 uint16_t i; 766 767 if (n < IONIC_NB_HW_STATS) 768 return IONIC_NB_HW_STATS; 769 770 ionic_lif_get_hw_stats(lif, &hw_stats); 771 772 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 773 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 774 rte_ionic_xstats_strings[i].offset); 775 xstats[i].id = i; 776 } 777 778 return IONIC_NB_HW_STATS; 779 } 780 781 static int 782 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 783 uint64_t *values, unsigned int n) 784 { 785 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 786 struct ionic_lif_stats hw_stats; 787 uint64_t values_copy[IONIC_NB_HW_STATS]; 788 uint16_t i; 789 790 if (!ids) { 791 if (!ids && n < IONIC_NB_HW_STATS) 792 return IONIC_NB_HW_STATS; 793 794 ionic_lif_get_hw_stats(lif, &hw_stats); 795 796 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 797 values[i] = *(uint64_t *)(((char *)&hw_stats) + 798 rte_ionic_xstats_strings[i].offset); 799 } 800 801 return IONIC_NB_HW_STATS; 802 } 803 804 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 805 IONIC_NB_HW_STATS); 806 807 for (i = 0; i < n; i++) { 808 if (ids[i] >= IONIC_NB_HW_STATS) { 809 IONIC_PRINT(ERR, "id value isn't valid"); 810 return -1; 811 } 812 813 values[i] = values_copy[ids[i]]; 814 } 815 816 return n; 817 } 818 819 static int 820 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 821 { 822 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 823 824 ionic_lif_reset_hw_stats(lif); 825 826 return 0; 827 } 828 829 static int 830 ionic_dev_configure(struct rte_eth_dev *eth_dev) 831 { 832 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 833 834 IONIC_PRINT_CALL(); 835 836 ionic_lif_configure(lif); 837 838 ionic_lif_set_features(lif); 839 840 return 0; 841 } 842 843 static inline uint32_t 844 ionic_parse_link_speeds(uint16_t link_speeds) 845 { 846 if (link_speeds & ETH_LINK_SPEED_100G) 847 return 100000; 848 else if (link_speeds & ETH_LINK_SPEED_50G) 849 return 50000; 850 else if (link_speeds & ETH_LINK_SPEED_40G) 851 return 40000; 852 else if (link_speeds & ETH_LINK_SPEED_25G) 853 return 25000; 854 else if (link_speeds & ETH_LINK_SPEED_10G) 855 return 10000; 856 else 857 return 0; 858 } 859 860 /* 861 * Configure device link speed and setup link. 862 * It returns 0 on success. 863 */ 864 static int 865 ionic_dev_start(struct rte_eth_dev *eth_dev) 866 { 867 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 868 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 869 struct ionic_adapter *adapter = lif->adapter; 870 struct ionic_dev *idev = &adapter->idev; 871 uint32_t speed = 0, allowed_speeds; 872 uint8_t an_enable; 873 int err; 874 875 IONIC_PRINT_CALL(); 876 877 allowed_speeds = 878 ETH_LINK_SPEED_FIXED | 879 ETH_LINK_SPEED_10G | 880 ETH_LINK_SPEED_25G | 881 ETH_LINK_SPEED_40G | 882 ETH_LINK_SPEED_50G | 883 ETH_LINK_SPEED_100G; 884 885 if (dev_conf->link_speeds & ~allowed_speeds) { 886 IONIC_PRINT(ERR, "Invalid link setting"); 887 return -EINVAL; 888 } 889 890 if (dev_conf->lpbk_mode) 891 IONIC_PRINT(WARNING, "Loopback mode not supported"); 892 893 err = ionic_lif_start(lif); 894 if (err) { 895 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 896 return err; 897 } 898 899 /* Configure link */ 900 an_enable = (dev_conf->link_speeds & ETH_LINK_SPEED_FIXED) == 0; 901 902 ionic_dev_cmd_port_autoneg(idev, an_enable); 903 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 904 if (err) 905 IONIC_PRINT(WARNING, "Failed to %s autonegotiation", 906 an_enable ? "enable" : "disable"); 907 908 if (!an_enable) 909 speed = ionic_parse_link_speeds(dev_conf->link_speeds); 910 if (speed) { 911 ionic_dev_cmd_port_speed(idev, speed); 912 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 913 if (err) 914 IONIC_PRINT(WARNING, "Failed to set link speed %u", 915 speed); 916 } 917 918 ionic_dev_link_update(eth_dev, 0); 919 920 return 0; 921 } 922 923 /* 924 * Stop device: disable rx and tx functions to allow for reconfiguring. 925 */ 926 static int 927 ionic_dev_stop(struct rte_eth_dev *eth_dev) 928 { 929 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 930 931 IONIC_PRINT_CALL(); 932 933 ionic_lif_stop(lif); 934 935 return 0; 936 } 937 938 static void ionic_unconfigure_intr(struct ionic_adapter *adapter); 939 940 /* 941 * Reset and stop device. 942 */ 943 static int 944 ionic_dev_close(struct rte_eth_dev *eth_dev) 945 { 946 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 947 struct ionic_adapter *adapter = lif->adapter; 948 949 IONIC_PRINT_CALL(); 950 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 951 return 0; 952 953 ionic_lif_stop(lif); 954 955 ionic_lif_free_queues(lif); 956 957 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 958 ionic_unconfigure_intr(adapter); 959 960 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 961 962 ionic_port_reset(adapter); 963 ionic_reset(adapter); 964 965 rte_free(adapter); 966 967 return 0; 968 } 969 970 static int 971 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 972 { 973 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 974 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 975 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 976 int err; 977 978 IONIC_PRINT_CALL(); 979 980 eth_dev->dev_ops = &ionic_eth_dev_ops; 981 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 982 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 983 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 984 985 /* Multi-process not supported, primary does initialization anyway */ 986 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 987 return 0; 988 989 rte_eth_copy_pci_info(eth_dev, pci_dev); 990 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 991 992 lif->eth_dev = eth_dev; 993 lif->adapter = adapter; 994 adapter->lif = lif; 995 996 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 997 adapter->max_mac_addrs); 998 999 /* Allocate memory for storing MAC addresses */ 1000 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 1001 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 1002 1003 if (eth_dev->data->mac_addrs == NULL) { 1004 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1005 "store MAC addresses", 1006 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1007 err = -ENOMEM; 1008 goto err; 1009 } 1010 1011 err = ionic_lif_alloc(lif); 1012 if (err) { 1013 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1014 err); 1015 goto err; 1016 } 1017 1018 err = ionic_lif_init(lif); 1019 if (err) { 1020 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1021 goto err_free_lif; 1022 } 1023 1024 /* Copy the MAC address */ 1025 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1026 ð_dev->data->mac_addrs[0]); 1027 1028 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1029 1030 return 0; 1031 1032 err_free_lif: 1033 ionic_lif_free(lif); 1034 err: 1035 return err; 1036 } 1037 1038 static int 1039 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1040 { 1041 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1042 struct ionic_adapter *adapter = lif->adapter; 1043 1044 IONIC_PRINT_CALL(); 1045 1046 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1047 return 0; 1048 1049 adapter->lif = NULL; 1050 1051 ionic_lif_deinit(lif); 1052 ionic_lif_free(lif); 1053 1054 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1055 ionic_lif_reset(lif); 1056 1057 return 0; 1058 } 1059 1060 static int 1061 ionic_configure_intr(struct ionic_adapter *adapter) 1062 { 1063 struct rte_pci_device *pci_dev = adapter->pci_dev; 1064 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1065 int err; 1066 1067 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1068 1069 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1070 IONIC_PRINT(ERR, "Fail to create eventfd"); 1071 return -1; 1072 } 1073 1074 if (rte_intr_dp_is_en(intr_handle)) 1075 IONIC_PRINT(DEBUG, 1076 "Packet I/O interrupt on datapath is enabled"); 1077 1078 if (!intr_handle->intr_vec) { 1079 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1080 adapter->nintrs * sizeof(int), 0); 1081 1082 if (!intr_handle->intr_vec) { 1083 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1084 adapter->nintrs); 1085 return -ENOMEM; 1086 } 1087 } 1088 1089 err = rte_intr_callback_register(intr_handle, 1090 ionic_dev_interrupt_handler, 1091 adapter); 1092 1093 if (err) { 1094 IONIC_PRINT(ERR, 1095 "Failure registering interrupts handler (%d)", 1096 err); 1097 return err; 1098 } 1099 1100 /* enable intr mapping */ 1101 err = rte_intr_enable(intr_handle); 1102 1103 if (err) { 1104 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1105 return err; 1106 } 1107 1108 return 0; 1109 } 1110 1111 static void 1112 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1113 { 1114 struct rte_pci_device *pci_dev = adapter->pci_dev; 1115 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1116 1117 rte_intr_disable(intr_handle); 1118 1119 rte_intr_callback_unregister(intr_handle, 1120 ionic_dev_interrupt_handler, 1121 adapter); 1122 } 1123 1124 static int 1125 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1126 struct rte_pci_device *pci_dev) 1127 { 1128 char name[RTE_ETH_NAME_MAX_LEN]; 1129 struct rte_mem_resource *resource; 1130 struct ionic_adapter *adapter; 1131 struct ionic_hw *hw; 1132 unsigned long i; 1133 int err; 1134 1135 /* Check structs (trigger error at compilation time) */ 1136 ionic_struct_size_checks(); 1137 1138 /* Multi-process not supported */ 1139 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1140 err = -EPERM; 1141 goto err; 1142 } 1143 1144 IONIC_PRINT(DEBUG, "Initializing device %s", 1145 pci_dev->device.name); 1146 1147 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1148 if (!adapter) { 1149 IONIC_PRINT(ERR, "OOM"); 1150 err = -ENOMEM; 1151 goto err; 1152 } 1153 1154 adapter->pci_dev = pci_dev; 1155 hw = &adapter->hw; 1156 1157 hw->device_id = pci_dev->id.device_id; 1158 hw->vendor_id = pci_dev->id.vendor_id; 1159 1160 err = ionic_init_mac(hw); 1161 if (err != 0) { 1162 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1163 err = -EIO; 1164 goto err_free_adapter; 1165 } 1166 1167 adapter->num_bars = 0; 1168 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1169 resource = &pci_dev->mem_resource[i]; 1170 if (resource->phys_addr == 0 || resource->len == 0) 1171 continue; 1172 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1173 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1174 adapter->bars[adapter->num_bars].len = resource->len; 1175 adapter->num_bars++; 1176 } 1177 1178 /* Discover ionic dev resources */ 1179 1180 err = ionic_setup(adapter); 1181 if (err) { 1182 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1183 goto err_free_adapter; 1184 } 1185 1186 err = ionic_identify(adapter); 1187 if (err) { 1188 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1189 err); 1190 goto err_free_adapter; 1191 } 1192 1193 err = ionic_init(adapter); 1194 if (err) { 1195 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1196 goto err_free_adapter; 1197 } 1198 1199 /* Configure the ports */ 1200 err = ionic_port_identify(adapter); 1201 if (err) { 1202 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1203 err); 1204 goto err_free_adapter; 1205 } 1206 1207 err = ionic_port_init(adapter); 1208 if (err) { 1209 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1210 goto err_free_adapter; 1211 } 1212 1213 /* Configure LIFs */ 1214 err = ionic_lif_identify(adapter); 1215 if (err) { 1216 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1217 goto err_free_adapter; 1218 } 1219 1220 /* Allocate and init LIFs */ 1221 err = ionic_lifs_size(adapter); 1222 if (err) { 1223 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1224 goto err_free_adapter; 1225 } 1226 1227 adapter->max_mac_addrs = 1228 rte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters); 1229 1230 if (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) { 1231 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1232 rte_le_to_cpu_32(adapter->ident.dev.nlifs)); 1233 goto err_free_adapter; 1234 } 1235 1236 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1237 err = rte_eth_dev_create(&pci_dev->device, 1238 name, sizeof(struct ionic_lif), 1239 NULL, NULL, eth_ionic_dev_init, adapter); 1240 if (err) { 1241 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1242 goto err_free_adapter; 1243 } 1244 1245 err = ionic_configure_intr(adapter); 1246 1247 if (err) { 1248 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1249 goto err_free_adapter; 1250 } 1251 1252 return 0; 1253 1254 err_free_adapter: 1255 rte_free(adapter); 1256 err: 1257 return err; 1258 } 1259 1260 static int 1261 eth_ionic_pci_remove(struct rte_pci_device *pci_dev) 1262 { 1263 char name[RTE_ETH_NAME_MAX_LEN]; 1264 struct rte_eth_dev *eth_dev; 1265 1266 /* Adapter lookup is using the eth_dev name */ 1267 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1268 1269 eth_dev = rte_eth_dev_allocated(name); 1270 if (eth_dev) 1271 ionic_dev_close(eth_dev); 1272 else 1273 IONIC_PRINT(DEBUG, "Cannot find device %s", 1274 pci_dev->device.name); 1275 1276 return 0; 1277 } 1278 1279 static struct rte_pci_driver rte_ionic_pmd = { 1280 .id_table = pci_id_ionic_map, 1281 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1282 .probe = eth_ionic_pci_probe, 1283 .remove = eth_ionic_pci_remove, 1284 }; 1285 1286 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1287 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1288 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1289 RTE_LOG_REGISTER_DEFAULT(ionic_logtype, NOTICE); 1290