1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <rte_ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static int ionic_dev_stop(struct rte_eth_dev *dev); 28 static int ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_dev_link_update(struct rte_eth_dev *eth_dev, 32 int wait_to_complete); 33 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 36 struct rte_eth_fc_conf *fc_conf); 37 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 38 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 42 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 45 struct rte_eth_rss_conf *rss_conf); 46 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 47 struct rte_eth_stats *stats); 48 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 49 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 50 struct rte_eth_xstat *xstats, unsigned int n); 51 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 52 const uint64_t *ids, uint64_t *values, unsigned int n); 53 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 54 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 55 struct rte_eth_xstat_name *xstats_names, unsigned int size); 56 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 57 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 58 unsigned int limit); 59 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 60 char *fw_version, size_t fw_size); 61 62 static const struct rte_pci_id pci_id_ionic_map[] = { 63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 64 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 65 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 66 { .vendor_id = 0, /* sentinel */ }, 67 }; 68 69 static const struct rte_eth_desc_lim rx_desc_lim = { 70 .nb_max = IONIC_MAX_RING_DESC, 71 .nb_min = IONIC_MIN_RING_DESC, 72 .nb_align = 1, 73 }; 74 75 static const struct rte_eth_desc_lim tx_desc_lim = { 76 .nb_max = IONIC_MAX_RING_DESC, 77 .nb_min = IONIC_MIN_RING_DESC, 78 .nb_align = 1, 79 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS, 80 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS, 81 }; 82 83 static const struct eth_dev_ops ionic_eth_dev_ops = { 84 .dev_infos_get = ionic_dev_info_get, 85 .dev_configure = ionic_dev_configure, 86 .mtu_set = ionic_dev_mtu_set, 87 .dev_start = ionic_dev_start, 88 .dev_stop = ionic_dev_stop, 89 .dev_close = ionic_dev_close, 90 .link_update = ionic_dev_link_update, 91 .dev_set_link_up = ionic_dev_set_link_up, 92 .dev_set_link_down = ionic_dev_set_link_down, 93 .mac_addr_add = ionic_dev_add_mac, 94 .mac_addr_remove = ionic_dev_remove_mac, 95 .mac_addr_set = ionic_dev_set_mac, 96 .vlan_filter_set = ionic_dev_vlan_filter_set, 97 .promiscuous_enable = ionic_dev_promiscuous_enable, 98 .promiscuous_disable = ionic_dev_promiscuous_disable, 99 .allmulticast_enable = ionic_dev_allmulticast_enable, 100 .allmulticast_disable = ionic_dev_allmulticast_disable, 101 .flow_ctrl_get = ionic_flow_ctrl_get, 102 .flow_ctrl_set = ionic_flow_ctrl_set, 103 .rxq_info_get = ionic_rxq_info_get, 104 .txq_info_get = ionic_txq_info_get, 105 .rx_queue_setup = ionic_dev_rx_queue_setup, 106 .rx_queue_release = ionic_dev_rx_queue_release, 107 .rx_queue_start = ionic_dev_rx_queue_start, 108 .rx_queue_stop = ionic_dev_rx_queue_stop, 109 .tx_queue_setup = ionic_dev_tx_queue_setup, 110 .tx_queue_release = ionic_dev_tx_queue_release, 111 .tx_queue_start = ionic_dev_tx_queue_start, 112 .tx_queue_stop = ionic_dev_tx_queue_stop, 113 .vlan_offload_set = ionic_vlan_offload_set, 114 .reta_update = ionic_dev_rss_reta_update, 115 .reta_query = ionic_dev_rss_reta_query, 116 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 117 .rss_hash_update = ionic_dev_rss_hash_update, 118 .stats_get = ionic_dev_stats_get, 119 .stats_reset = ionic_dev_stats_reset, 120 .xstats_get = ionic_dev_xstats_get, 121 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 122 .xstats_reset = ionic_dev_xstats_reset, 123 .xstats_get_names = ionic_dev_xstats_get_names, 124 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 125 .fw_version_get = ionic_dev_fw_version_get, 126 }; 127 128 struct rte_ionic_xstats_name_off { 129 char name[RTE_ETH_XSTATS_NAME_SIZE]; 130 unsigned int offset; 131 }; 132 133 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 134 /* RX */ 135 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 136 rx_ucast_bytes)}, 137 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 138 rx_ucast_packets)}, 139 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 140 rx_mcast_bytes)}, 141 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 142 rx_mcast_packets)}, 143 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 144 rx_bcast_bytes)}, 145 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 146 rx_bcast_packets)}, 147 /* RX drops */ 148 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 149 rx_ucast_drop_bytes)}, 150 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 151 rx_ucast_drop_packets)}, 152 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 153 rx_mcast_drop_bytes)}, 154 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 155 rx_mcast_drop_packets)}, 156 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 157 rx_bcast_drop_bytes)}, 158 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 159 rx_bcast_drop_packets)}, 160 {"rx_dma_error", offsetof(struct ionic_lif_stats, 161 rx_dma_error)}, 162 /* TX */ 163 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 164 tx_ucast_bytes)}, 165 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 166 tx_ucast_packets)}, 167 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 168 tx_mcast_bytes)}, 169 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 170 tx_mcast_packets)}, 171 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 172 tx_bcast_bytes)}, 173 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 174 tx_bcast_packets)}, 175 /* TX drops */ 176 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 177 tx_ucast_drop_bytes)}, 178 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 179 tx_ucast_drop_packets)}, 180 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 181 tx_mcast_drop_bytes)}, 182 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 183 tx_mcast_drop_packets)}, 184 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 185 tx_bcast_drop_bytes)}, 186 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 187 tx_bcast_drop_packets)}, 188 {"tx_dma_error", offsetof(struct ionic_lif_stats, 189 tx_dma_error)}, 190 /* Rx Queue/Ring drops */ 191 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 192 rx_queue_disabled)}, 193 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 194 rx_queue_empty)}, 195 {"rx_queue_error", offsetof(struct ionic_lif_stats, 196 rx_queue_error)}, 197 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 198 rx_desc_fetch_error)}, 199 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 200 rx_desc_data_error)}, 201 /* Tx Queue/Ring drops */ 202 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 203 tx_queue_disabled)}, 204 {"tx_queue_error", offsetof(struct ionic_lif_stats, 205 tx_queue_error)}, 206 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 207 tx_desc_fetch_error)}, 208 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 209 tx_desc_data_error)}, 210 }; 211 212 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \ 213 sizeof(rte_ionic_xstats_strings[0])) 214 215 static int 216 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 217 char *fw_version, size_t fw_size) 218 { 219 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 220 struct ionic_adapter *adapter = lif->adapter; 221 222 if (fw_version == NULL || fw_size <= 0) 223 return -EINVAL; 224 225 snprintf(fw_version, fw_size, "%s", 226 adapter->fw_version); 227 fw_version[fw_size - 1] = '\0'; 228 229 return 0; 230 } 231 232 /* 233 * Set device link up, enable tx. 234 */ 235 static int 236 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 237 { 238 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 239 struct ionic_adapter *adapter = lif->adapter; 240 struct ionic_dev *idev = &adapter->idev; 241 int err; 242 243 IONIC_PRINT_CALL(); 244 245 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_UP); 246 247 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 248 if (err) { 249 IONIC_PRINT(WARNING, "Failed to bring port UP"); 250 return err; 251 } 252 253 return 0; 254 } 255 256 /* 257 * Set device link down, disable tx. 258 */ 259 static int 260 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 261 { 262 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 263 struct ionic_adapter *adapter = lif->adapter; 264 struct ionic_dev *idev = &adapter->idev; 265 int err; 266 267 IONIC_PRINT_CALL(); 268 269 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_DOWN); 270 271 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 272 if (err) { 273 IONIC_PRINT(WARNING, "Failed to bring port DOWN"); 274 return err; 275 } 276 277 return 0; 278 } 279 280 static int 281 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 282 int wait_to_complete __rte_unused) 283 { 284 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 285 struct ionic_adapter *adapter = lif->adapter; 286 struct rte_eth_link link; 287 288 IONIC_PRINT_CALL(); 289 290 /* Initialize */ 291 memset(&link, 0, sizeof(link)); 292 link.link_autoneg = ETH_LINK_AUTONEG; 293 294 if (!adapter->link_up) { 295 /* Interface is down */ 296 link.link_status = ETH_LINK_DOWN; 297 link.link_duplex = ETH_LINK_HALF_DUPLEX; 298 link.link_speed = ETH_SPEED_NUM_NONE; 299 } else { 300 /* Interface is up */ 301 link.link_status = ETH_LINK_UP; 302 link.link_duplex = ETH_LINK_FULL_DUPLEX; 303 switch (adapter->link_speed) { 304 case 10000: 305 link.link_speed = ETH_SPEED_NUM_10G; 306 break; 307 case 25000: 308 link.link_speed = ETH_SPEED_NUM_25G; 309 break; 310 case 40000: 311 link.link_speed = ETH_SPEED_NUM_40G; 312 break; 313 case 50000: 314 link.link_speed = ETH_SPEED_NUM_50G; 315 break; 316 case 100000: 317 link.link_speed = ETH_SPEED_NUM_100G; 318 break; 319 default: 320 link.link_speed = ETH_SPEED_NUM_NONE; 321 break; 322 } 323 } 324 325 return rte_eth_linkstatus_set(eth_dev, &link); 326 } 327 328 /** 329 * Interrupt handler triggered by NIC for handling 330 * specific interrupt. 331 * 332 * @param param 333 * The address of parameter registered before. 334 * 335 * @return 336 * void 337 */ 338 static void 339 ionic_dev_interrupt_handler(void *param) 340 { 341 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 342 343 IONIC_PRINT(DEBUG, "->"); 344 345 if (adapter->lif) 346 ionic_notifyq_handler(adapter->lif, -1); 347 } 348 349 static int 350 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 351 { 352 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 353 uint32_t max_frame_size; 354 int err; 355 356 IONIC_PRINT_CALL(); 357 358 /* 359 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 360 * is done by the the API. 361 */ 362 363 /* 364 * Max frame size is MTU + Ethernet header + VLAN + QinQ 365 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC) 366 */ 367 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4; 368 369 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size) 370 return -EINVAL; 371 372 err = ionic_lif_change_mtu(lif, mtu); 373 if (err) 374 return err; 375 376 return 0; 377 } 378 379 static int 380 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 381 struct rte_eth_dev_info *dev_info) 382 { 383 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 384 struct ionic_adapter *adapter = lif->adapter; 385 struct ionic_identity *ident = &adapter->ident; 386 387 IONIC_PRINT_CALL(); 388 389 dev_info->max_rx_queues = (uint16_t) 390 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; 391 dev_info->max_tx_queues = (uint16_t) 392 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; 393 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 394 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 395 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 396 dev_info->max_mac_addrs = adapter->max_mac_addrs; 397 dev_info->min_mtu = IONIC_MIN_MTU; 398 dev_info->max_mtu = IONIC_MAX_MTU; 399 400 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 401 dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz; 402 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 403 404 dev_info->speed_capa = 405 ETH_LINK_SPEED_10G | 406 ETH_LINK_SPEED_25G | 407 ETH_LINK_SPEED_40G | 408 ETH_LINK_SPEED_50G | 409 ETH_LINK_SPEED_100G; 410 411 /* 412 * Per-queue capabilities. Actually most of the offloads are enabled 413 * by default on the port and can be used on selected queues (by adding 414 * packet flags at runtime when required) 415 */ 416 417 dev_info->rx_queue_offload_capa = 418 DEV_RX_OFFLOAD_IPV4_CKSUM | 419 DEV_RX_OFFLOAD_UDP_CKSUM | 420 DEV_RX_OFFLOAD_TCP_CKSUM | 421 0; 422 423 dev_info->tx_queue_offload_capa = 424 DEV_TX_OFFLOAD_IPV4_CKSUM | 425 DEV_TX_OFFLOAD_UDP_CKSUM | 426 DEV_TX_OFFLOAD_TCP_CKSUM | 427 DEV_TX_OFFLOAD_VLAN_INSERT | 428 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 429 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 430 0; 431 432 /* 433 * Per-port capabilities 434 * See ionic_set_features to request and check supported features 435 */ 436 437 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 438 DEV_RX_OFFLOAD_JUMBO_FRAME | 439 DEV_RX_OFFLOAD_VLAN_FILTER | 440 DEV_RX_OFFLOAD_VLAN_STRIP | 441 DEV_RX_OFFLOAD_SCATTER | 442 0; 443 444 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 445 DEV_TX_OFFLOAD_MULTI_SEGS | 446 DEV_TX_OFFLOAD_TCP_TSO | 447 0; 448 449 dev_info->rx_desc_lim = rx_desc_lim; 450 dev_info->tx_desc_lim = tx_desc_lim; 451 452 /* Driver-preferred Rx/Tx parameters */ 453 dev_info->default_rxportconf.burst_size = 32; 454 dev_info->default_txportconf.burst_size = 32; 455 dev_info->default_rxportconf.nb_queues = 1; 456 dev_info->default_txportconf.nb_queues = 1; 457 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 458 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 459 460 return 0; 461 } 462 463 static int 464 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 465 struct rte_eth_fc_conf *fc_conf) 466 { 467 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 468 struct ionic_adapter *adapter = lif->adapter; 469 struct ionic_dev *idev = &adapter->idev; 470 471 if (idev->port_info) { 472 fc_conf->autoneg = idev->port_info->config.an_enable; 473 474 if (idev->port_info->config.pause_type) 475 fc_conf->mode = RTE_FC_FULL; 476 else 477 fc_conf->mode = RTE_FC_NONE; 478 } 479 480 return 0; 481 } 482 483 static int 484 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 485 struct rte_eth_fc_conf *fc_conf) 486 { 487 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 488 struct ionic_adapter *adapter = lif->adapter; 489 struct ionic_dev *idev = &adapter->idev; 490 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 491 uint8_t an_enable; 492 493 switch (fc_conf->mode) { 494 case RTE_FC_NONE: 495 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 496 break; 497 case RTE_FC_FULL: 498 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 499 break; 500 case RTE_FC_RX_PAUSE: 501 case RTE_FC_TX_PAUSE: 502 return -ENOTSUP; 503 } 504 505 an_enable = fc_conf->autoneg; 506 507 ionic_dev_cmd_port_pause(idev, pause_type); 508 ionic_dev_cmd_port_autoneg(idev, an_enable); 509 510 return 0; 511 } 512 513 static int 514 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 515 { 516 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 517 struct rte_eth_rxmode *rxmode; 518 rxmode = ð_dev->data->dev_conf.rxmode; 519 int i; 520 521 if (mask & ETH_VLAN_STRIP_MASK) { 522 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 523 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 524 struct ionic_qcq *rxq = 525 eth_dev->data->rx_queues[i]; 526 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 527 } 528 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP; 529 } else { 530 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 531 struct ionic_qcq *rxq = 532 eth_dev->data->rx_queues[i]; 533 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 534 } 535 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP; 536 } 537 } 538 539 if (mask & ETH_VLAN_FILTER_MASK) { 540 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 541 lif->features |= IONIC_ETH_HW_VLAN_RX_FILTER; 542 else 543 lif->features &= ~IONIC_ETH_HW_VLAN_RX_FILTER; 544 } 545 546 ionic_lif_set_features(lif); 547 548 return 0; 549 } 550 551 static int 552 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 553 struct rte_eth_rss_reta_entry64 *reta_conf, 554 uint16_t reta_size) 555 { 556 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 557 struct ionic_adapter *adapter = lif->adapter; 558 struct ionic_identity *ident = &adapter->ident; 559 uint32_t i, j, index, num; 560 561 IONIC_PRINT_CALL(); 562 563 if (!lif->rss_ind_tbl) { 564 IONIC_PRINT(ERR, "RSS RETA not initialized, " 565 "can't update the table"); 566 return -EINVAL; 567 } 568 569 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 570 IONIC_PRINT(ERR, "The size of hash lookup table configured " 571 "(%d) does not match the number hardware can support " 572 "(%d)", 573 reta_size, ident->lif.eth.rss_ind_tbl_sz); 574 return -EINVAL; 575 } 576 577 num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE; 578 579 for (i = 0; i < num; i++) { 580 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 581 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 582 index = (i * RTE_RETA_GROUP_SIZE) + j; 583 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 584 } 585 } 586 } 587 588 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 589 } 590 591 static int 592 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 593 struct rte_eth_rss_reta_entry64 *reta_conf, 594 uint16_t reta_size) 595 { 596 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 597 struct ionic_adapter *adapter = lif->adapter; 598 struct ionic_identity *ident = &adapter->ident; 599 int i, num; 600 601 IONIC_PRINT_CALL(); 602 603 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 604 IONIC_PRINT(ERR, "The size of hash lookup table configured " 605 "(%d) does not match the number hardware can support " 606 "(%d)", 607 reta_size, ident->lif.eth.rss_ind_tbl_sz); 608 return -EINVAL; 609 } 610 611 if (!lif->rss_ind_tbl) { 612 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 613 return -EINVAL; 614 } 615 616 num = reta_size / RTE_RETA_GROUP_SIZE; 617 618 for (i = 0; i < num; i++) { 619 memcpy(reta_conf->reta, 620 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 621 RTE_RETA_GROUP_SIZE); 622 reta_conf++; 623 } 624 625 return 0; 626 } 627 628 static int 629 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 630 struct rte_eth_rss_conf *rss_conf) 631 { 632 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 633 uint64_t rss_hf = 0; 634 635 IONIC_PRINT_CALL(); 636 637 if (!lif->rss_ind_tbl) { 638 IONIC_PRINT(NOTICE, "RSS not enabled"); 639 return 0; 640 } 641 642 /* Get key value (if not null, rss_key is 40-byte) */ 643 if (rss_conf->rss_key != NULL && 644 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 645 memcpy(rss_conf->rss_key, lif->rss_hash_key, 646 IONIC_RSS_HASH_KEY_SIZE); 647 648 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 649 rss_hf |= ETH_RSS_IPV4; 650 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 651 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 652 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 653 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 654 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 655 rss_hf |= ETH_RSS_IPV6; 656 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 657 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 658 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 659 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 660 661 rss_conf->rss_hf = rss_hf; 662 663 return 0; 664 } 665 666 static int 667 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 668 struct rte_eth_rss_conf *rss_conf) 669 { 670 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 671 uint32_t rss_types = 0; 672 uint8_t *key = NULL; 673 674 IONIC_PRINT_CALL(); 675 676 if (rss_conf->rss_key) 677 key = rss_conf->rss_key; 678 679 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 680 /* 681 * Can't disable rss through hash flags, 682 * if it is enabled by default during init 683 */ 684 if (lif->rss_ind_tbl) 685 return -EINVAL; 686 } else { 687 /* Can't enable rss if disabled by default during init */ 688 if (!lif->rss_ind_tbl) 689 return -EINVAL; 690 691 if (rss_conf->rss_hf & ETH_RSS_IPV4) 692 rss_types |= IONIC_RSS_TYPE_IPV4; 693 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 694 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 695 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 696 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 697 if (rss_conf->rss_hf & ETH_RSS_IPV6) 698 rss_types |= IONIC_RSS_TYPE_IPV6; 699 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 700 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 701 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 702 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 703 704 ionic_lif_rss_config(lif, rss_types, key, NULL); 705 } 706 707 return 0; 708 } 709 710 static int 711 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 712 struct rte_eth_stats *stats) 713 { 714 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 715 716 ionic_lif_get_stats(lif, stats); 717 718 return 0; 719 } 720 721 static int 722 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 723 { 724 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 725 726 IONIC_PRINT_CALL(); 727 728 ionic_lif_reset_stats(lif); 729 730 return 0; 731 } 732 733 static int 734 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 735 struct rte_eth_xstat_name *xstats_names, 736 __rte_unused unsigned int size) 737 { 738 unsigned int i; 739 740 if (xstats_names != NULL) { 741 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 742 snprintf(xstats_names[i].name, 743 sizeof(xstats_names[i].name), 744 "%s", rte_ionic_xstats_strings[i].name); 745 } 746 } 747 748 return IONIC_NB_HW_STATS; 749 } 750 751 static int 752 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 753 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 754 unsigned int limit) 755 { 756 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 757 uint16_t i; 758 759 if (!ids) { 760 if (xstats_names != NULL) { 761 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 762 snprintf(xstats_names[i].name, 763 sizeof(xstats_names[i].name), 764 "%s", rte_ionic_xstats_strings[i].name); 765 } 766 } 767 768 return IONIC_NB_HW_STATS; 769 } 770 771 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL, 772 IONIC_NB_HW_STATS); 773 774 for (i = 0; i < limit; i++) { 775 if (ids[i] >= IONIC_NB_HW_STATS) { 776 IONIC_PRINT(ERR, "id value isn't valid"); 777 return -1; 778 } 779 780 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 781 } 782 783 return limit; 784 } 785 786 static int 787 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 788 unsigned int n) 789 { 790 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 791 struct ionic_lif_stats hw_stats; 792 uint16_t i; 793 794 if (n < IONIC_NB_HW_STATS) 795 return IONIC_NB_HW_STATS; 796 797 ionic_lif_get_hw_stats(lif, &hw_stats); 798 799 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 800 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 801 rte_ionic_xstats_strings[i].offset); 802 xstats[i].id = i; 803 } 804 805 return IONIC_NB_HW_STATS; 806 } 807 808 static int 809 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 810 uint64_t *values, unsigned int n) 811 { 812 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 813 struct ionic_lif_stats hw_stats; 814 uint64_t values_copy[IONIC_NB_HW_STATS]; 815 uint16_t i; 816 817 if (!ids) { 818 if (!ids && n < IONIC_NB_HW_STATS) 819 return IONIC_NB_HW_STATS; 820 821 ionic_lif_get_hw_stats(lif, &hw_stats); 822 823 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 824 values[i] = *(uint64_t *)(((char *)&hw_stats) + 825 rte_ionic_xstats_strings[i].offset); 826 } 827 828 return IONIC_NB_HW_STATS; 829 } 830 831 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 832 IONIC_NB_HW_STATS); 833 834 for (i = 0; i < n; i++) { 835 if (ids[i] >= IONIC_NB_HW_STATS) { 836 IONIC_PRINT(ERR, "id value isn't valid"); 837 return -1; 838 } 839 840 values[i] = values_copy[ids[i]]; 841 } 842 843 return n; 844 } 845 846 static int 847 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 848 { 849 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 850 851 ionic_lif_reset_hw_stats(lif); 852 853 return 0; 854 } 855 856 static int 857 ionic_dev_configure(struct rte_eth_dev *eth_dev) 858 { 859 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 860 int err; 861 862 IONIC_PRINT_CALL(); 863 864 err = ionic_lif_configure(lif); 865 if (err) { 866 IONIC_PRINT(ERR, "Cannot configure LIF: %d", err); 867 return err; 868 } 869 870 return 0; 871 } 872 873 static inline uint32_t 874 ionic_parse_link_speeds(uint16_t link_speeds) 875 { 876 if (link_speeds & ETH_LINK_SPEED_100G) 877 return 100000; 878 else if (link_speeds & ETH_LINK_SPEED_50G) 879 return 50000; 880 else if (link_speeds & ETH_LINK_SPEED_40G) 881 return 40000; 882 else if (link_speeds & ETH_LINK_SPEED_25G) 883 return 25000; 884 else if (link_speeds & ETH_LINK_SPEED_10G) 885 return 10000; 886 else 887 return 0; 888 } 889 890 /* 891 * Configure device link speed and setup link. 892 * It returns 0 on success. 893 */ 894 static int 895 ionic_dev_start(struct rte_eth_dev *eth_dev) 896 { 897 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 898 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 899 struct ionic_adapter *adapter = lif->adapter; 900 struct ionic_dev *idev = &adapter->idev; 901 uint32_t allowed_speeds; 902 int err; 903 904 IONIC_PRINT_CALL(); 905 906 allowed_speeds = 907 ETH_LINK_SPEED_FIXED | 908 ETH_LINK_SPEED_10G | 909 ETH_LINK_SPEED_25G | 910 ETH_LINK_SPEED_40G | 911 ETH_LINK_SPEED_50G | 912 ETH_LINK_SPEED_100G; 913 914 if (dev_conf->link_speeds & ~allowed_speeds) { 915 IONIC_PRINT(ERR, "Invalid link setting"); 916 return -EINVAL; 917 } 918 919 if (dev_conf->lpbk_mode) 920 IONIC_PRINT(WARNING, "Loopback mode not supported"); 921 922 err = ionic_lif_start(lif); 923 if (err) { 924 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 925 return err; 926 } 927 928 if (eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 929 uint32_t speed = ionic_parse_link_speeds(dev_conf->link_speeds); 930 931 if (speed) 932 ionic_dev_cmd_port_speed(idev, speed); 933 } 934 935 ionic_dev_link_update(eth_dev, 0); 936 937 return 0; 938 } 939 940 /* 941 * Stop device: disable rx and tx functions to allow for reconfiguring. 942 */ 943 static int 944 ionic_dev_stop(struct rte_eth_dev *eth_dev) 945 { 946 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 947 int err; 948 949 IONIC_PRINT_CALL(); 950 951 err = ionic_lif_stop(lif); 952 if (err) 953 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err); 954 955 return err; 956 } 957 958 /* 959 * Reset and stop device. 960 */ 961 static int 962 ionic_dev_close(struct rte_eth_dev *eth_dev) 963 { 964 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 965 int err; 966 967 IONIC_PRINT_CALL(); 968 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 969 return 0; 970 971 err = ionic_lif_stop(lif); 972 if (err) { 973 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err); 974 return -1; 975 } 976 977 err = eth_ionic_dev_uninit(eth_dev); 978 if (err) { 979 IONIC_PRINT(ERR, "Cannot destroy LIF: %d", err); 980 return -1; 981 } 982 983 return 0; 984 } 985 986 static int 987 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 988 { 989 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 990 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 991 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 992 int err; 993 994 IONIC_PRINT_CALL(); 995 996 eth_dev->dev_ops = &ionic_eth_dev_ops; 997 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 998 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 999 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 1000 1001 /* Multi-process not supported, primary does initialization anyway */ 1002 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1003 return 0; 1004 1005 rte_eth_copy_pci_info(eth_dev, pci_dev); 1006 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1007 1008 lif->eth_dev = eth_dev; 1009 lif->adapter = adapter; 1010 adapter->lif = lif; 1011 1012 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1013 adapter->max_mac_addrs); 1014 1015 /* Allocate memory for storing MAC addresses */ 1016 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 1017 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 1018 1019 if (eth_dev->data->mac_addrs == NULL) { 1020 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1021 "store MAC addresses", 1022 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1023 err = -ENOMEM; 1024 goto err; 1025 } 1026 1027 err = ionic_lif_alloc(lif); 1028 if (err) { 1029 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1030 err); 1031 goto err; 1032 } 1033 1034 err = ionic_lif_init(lif); 1035 if (err) { 1036 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1037 goto err_free_lif; 1038 } 1039 1040 /* Copy the MAC address */ 1041 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1042 ð_dev->data->mac_addrs[0]); 1043 1044 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1045 1046 return 0; 1047 1048 err_free_lif: 1049 ionic_lif_free(lif); 1050 err: 1051 return err; 1052 } 1053 1054 static int 1055 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1056 { 1057 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1058 struct ionic_adapter *adapter = lif->adapter; 1059 1060 IONIC_PRINT_CALL(); 1061 1062 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1063 return 0; 1064 1065 adapter->lif = NULL; 1066 1067 ionic_lif_deinit(lif); 1068 ionic_lif_free(lif); 1069 1070 return 0; 1071 } 1072 1073 static int 1074 ionic_configure_intr(struct ionic_adapter *adapter) 1075 { 1076 struct rte_pci_device *pci_dev = adapter->pci_dev; 1077 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1078 int err; 1079 1080 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1081 1082 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1083 IONIC_PRINT(ERR, "Fail to create eventfd"); 1084 return -1; 1085 } 1086 1087 if (rte_intr_dp_is_en(intr_handle)) 1088 IONIC_PRINT(DEBUG, 1089 "Packet I/O interrupt on datapath is enabled"); 1090 1091 if (!intr_handle->intr_vec) { 1092 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1093 adapter->nintrs * sizeof(int), 0); 1094 1095 if (!intr_handle->intr_vec) { 1096 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1097 adapter->nintrs); 1098 return -ENOMEM; 1099 } 1100 } 1101 1102 err = rte_intr_callback_register(intr_handle, 1103 ionic_dev_interrupt_handler, 1104 adapter); 1105 1106 if (err) { 1107 IONIC_PRINT(ERR, 1108 "Failure registering interrupts handler (%d)", 1109 err); 1110 return err; 1111 } 1112 1113 /* enable intr mapping */ 1114 err = rte_intr_enable(intr_handle); 1115 1116 if (err) { 1117 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1118 return err; 1119 } 1120 1121 return 0; 1122 } 1123 1124 static void 1125 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1126 { 1127 struct rte_pci_device *pci_dev = adapter->pci_dev; 1128 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1129 1130 rte_intr_disable(intr_handle); 1131 1132 rte_intr_callback_unregister(intr_handle, 1133 ionic_dev_interrupt_handler, 1134 adapter); 1135 } 1136 1137 static int 1138 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1139 struct rte_pci_device *pci_dev) 1140 { 1141 char name[RTE_ETH_NAME_MAX_LEN]; 1142 struct rte_mem_resource *resource; 1143 struct ionic_adapter *adapter; 1144 struct ionic_hw *hw; 1145 unsigned long i; 1146 int err; 1147 1148 /* Check structs (trigger error at compilation time) */ 1149 ionic_struct_size_checks(); 1150 1151 /* Multi-process not supported */ 1152 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1153 err = -EPERM; 1154 goto err; 1155 } 1156 1157 IONIC_PRINT(DEBUG, "Initializing device %s", 1158 pci_dev->device.name); 1159 1160 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1161 if (!adapter) { 1162 IONIC_PRINT(ERR, "OOM"); 1163 err = -ENOMEM; 1164 goto err; 1165 } 1166 1167 adapter->pci_dev = pci_dev; 1168 hw = &adapter->hw; 1169 1170 hw->device_id = pci_dev->id.device_id; 1171 hw->vendor_id = pci_dev->id.vendor_id; 1172 1173 err = ionic_init_mac(hw); 1174 if (err != 0) { 1175 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1176 err = -EIO; 1177 goto err_free_adapter; 1178 } 1179 1180 adapter->num_bars = 0; 1181 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1182 resource = &pci_dev->mem_resource[i]; 1183 if (resource->phys_addr == 0 || resource->len == 0) 1184 continue; 1185 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1186 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1187 adapter->bars[adapter->num_bars].len = resource->len; 1188 adapter->num_bars++; 1189 } 1190 1191 /* Discover ionic dev resources */ 1192 1193 err = ionic_setup(adapter); 1194 if (err) { 1195 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1196 goto err_free_adapter; 1197 } 1198 1199 err = ionic_identify(adapter); 1200 if (err) { 1201 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1202 err); 1203 goto err_free_adapter; 1204 } 1205 1206 err = ionic_init(adapter); 1207 if (err) { 1208 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1209 goto err_free_adapter; 1210 } 1211 1212 /* Configure the ports */ 1213 err = ionic_port_identify(adapter); 1214 if (err) { 1215 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1216 err); 1217 goto err_free_adapter; 1218 } 1219 1220 err = ionic_port_init(adapter); 1221 if (err) { 1222 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1223 goto err_free_adapter; 1224 } 1225 1226 /* Configure LIFs */ 1227 err = ionic_lif_identify(adapter); 1228 if (err) { 1229 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1230 goto err_free_adapter; 1231 } 1232 1233 /* Allocate and init LIFs */ 1234 err = ionic_lifs_size(adapter); 1235 if (err) { 1236 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1237 goto err_free_adapter; 1238 } 1239 1240 adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters; 1241 1242 if (adapter->ident.dev.nlifs != 1) { 1243 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1244 adapter->ident.dev.nlifs); 1245 goto err_free_adapter; 1246 } 1247 1248 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1249 err = rte_eth_dev_create(&pci_dev->device, 1250 name, sizeof(struct ionic_lif), 1251 NULL, NULL, eth_ionic_dev_init, adapter); 1252 if (err) { 1253 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1254 goto err_free_adapter; 1255 } 1256 1257 err = ionic_configure_intr(adapter); 1258 1259 if (err) { 1260 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1261 goto err_free_adapter; 1262 } 1263 1264 return 0; 1265 1266 err_free_adapter: 1267 rte_free(adapter); 1268 err: 1269 return err; 1270 } 1271 1272 static int 1273 eth_ionic_pci_remove(struct rte_pci_device *pci_dev __rte_unused) 1274 { 1275 char name[RTE_ETH_NAME_MAX_LEN]; 1276 struct ionic_adapter *adapter = NULL; 1277 struct rte_eth_dev *eth_dev; 1278 struct ionic_lif *lif; 1279 1280 /* Adapter lookup is using the eth_dev name */ 1281 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1282 1283 eth_dev = rte_eth_dev_allocated(name); 1284 if (eth_dev) { 1285 lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1286 adapter = lif->adapter; 1287 } 1288 1289 if (adapter) { 1290 ionic_unconfigure_intr(adapter); 1291 1292 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 1293 1294 rte_free(adapter); 1295 } 1296 1297 return 0; 1298 } 1299 1300 static struct rte_pci_driver rte_ionic_pmd = { 1301 .id_table = pci_id_ionic_map, 1302 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1303 .probe = eth_ionic_pci_probe, 1304 .remove = eth_ionic_pci_remove, 1305 }; 1306 1307 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1308 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1309 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1310 RTE_LOG_REGISTER(ionic_logtype, pmd.net.ionic, NOTICE); 1311