12e99ea80SHyong Youb Kim /* SPDX-License-Identifier: BSD-3-Clause 22e99ea80SHyong Youb Kim * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 372f3de30SBruce Richardson * Copyright 2007 Nuova Systems, Inc. All rights reserved. 472f3de30SBruce Richardson */ 572f3de30SBruce Richardson 672f3de30SBruce Richardson #ifndef _VNIC_RESOURCE_H_ 772f3de30SBruce Richardson #define _VNIC_RESOURCE_H_ 872f3de30SBruce Richardson 972f3de30SBruce Richardson #define VNIC_RES_MAGIC 0x766E6963L /* 'vnic' */ 1072f3de30SBruce Richardson #define VNIC_RES_VERSION 0x00000000L 1172f3de30SBruce Richardson #define MGMTVNIC_MAGIC 0x544d474dL /* 'MGMT' */ 1272f3de30SBruce Richardson #define MGMTVNIC_VERSION 0x00000000L 1372f3de30SBruce Richardson 1472f3de30SBruce Richardson /* The MAC address assigned to the CFG vNIC is fixed. */ 1572f3de30SBruce Richardson #define MGMTVNIC_MAC { 0x02, 0x00, 0x54, 0x4d, 0x47, 0x4d } 1672f3de30SBruce Richardson 1772f3de30SBruce Richardson /* vNIC resource types */ 1872f3de30SBruce Richardson enum vnic_res_type { 1972f3de30SBruce Richardson RES_TYPE_EOL, /* End-of-list */ 2072f3de30SBruce Richardson RES_TYPE_WQ, /* Work queues */ 2172f3de30SBruce Richardson RES_TYPE_RQ, /* Receive queues */ 2272f3de30SBruce Richardson RES_TYPE_CQ, /* Completion queues */ 2372f3de30SBruce Richardson RES_TYPE_MEM, /* Window to dev memory */ 2472f3de30SBruce Richardson RES_TYPE_NIC_CFG, /* Enet NIC config registers */ 2572f3de30SBruce Richardson RES_TYPE_RSS_KEY, /* Enet RSS secret key */ 2672f3de30SBruce Richardson RES_TYPE_RSS_CPU, /* Enet RSS indirection table */ 2772f3de30SBruce Richardson RES_TYPE_TX_STATS, /* Netblock Tx statistic regs */ 2872f3de30SBruce Richardson RES_TYPE_RX_STATS, /* Netblock Rx statistic regs */ 2972f3de30SBruce Richardson RES_TYPE_INTR_CTRL, /* Interrupt ctrl table */ 3072f3de30SBruce Richardson RES_TYPE_INTR_TABLE, /* MSI/MSI-X Interrupt table */ 3172f3de30SBruce Richardson RES_TYPE_INTR_PBA, /* MSI/MSI-X PBA table */ 3272f3de30SBruce Richardson RES_TYPE_INTR_PBA_LEGACY, /* Legacy intr status */ 3372f3de30SBruce Richardson RES_TYPE_DEBUG, /* Debug-only info */ 3472f3de30SBruce Richardson RES_TYPE_DEV, /* Device-specific region */ 3572f3de30SBruce Richardson RES_TYPE_DEVCMD, /* Device command region */ 3672f3de30SBruce Richardson RES_TYPE_PASS_THRU_PAGE, /* Pass-thru page */ 3772f3de30SBruce Richardson RES_TYPE_SUBVNIC, /* subvnic resource type */ 3872f3de30SBruce Richardson RES_TYPE_MQ_WQ, /* MQ Work queues */ 3972f3de30SBruce Richardson RES_TYPE_MQ_RQ, /* MQ Receive queues */ 4072f3de30SBruce Richardson RES_TYPE_MQ_CQ, /* MQ Completion queues */ 4172f3de30SBruce Richardson RES_TYPE_DEPRECATED1, /* Old version of devcmd 2 */ 42*00ce4311SHyong Youb Kim RES_TYPE_DEPRECATED2, /* Old version of devcmd 2 */ 4372f3de30SBruce Richardson RES_TYPE_DEVCMD2, /* Device control region */ 44*00ce4311SHyong Youb Kim RES_TYPE_RDMA_WQ, /* RDMA WQ */ 45*00ce4311SHyong Youb Kim RES_TYPE_RDMA_RQ, /* RDMA RQ */ 46*00ce4311SHyong Youb Kim RES_TYPE_RDMA_CQ, /* RDMA CQ */ 47*00ce4311SHyong Youb Kim RES_TYPE_RDMA_RKEY_TABLE, /* RDMA RKEY table */ 48*00ce4311SHyong Youb Kim RES_TYPE_RDMA_RQ_HEADER_TABLE, /* RDMA RQ Header Table */ 49*00ce4311SHyong Youb Kim RES_TYPE_RDMA_RQ_TABLE, /* RDMA RQ Table */ 50*00ce4311SHyong Youb Kim RES_TYPE_RDMA_RD_RESP_HEADER_TABLE, /* RDMA Read Response Header Table */ 51*00ce4311SHyong Youb Kim RES_TYPE_RDMA_RD_RESP_TABLE, /* RDMA Read Response Table */ 52*00ce4311SHyong Youb Kim RES_TYPE_RDMA_QP_STATS_TABLE, /* RDMA per QP stats table */ 53*00ce4311SHyong Youb Kim RES_TYPE_WQ_MREGS, /* XXX snic proto only */ 54*00ce4311SHyong Youb Kim RES_TYPE_GRPMBR_INTR, /* Group member interrupt control */ 55*00ce4311SHyong Youb Kim RES_TYPE_DPKT, /* Direct Packet memory region */ 56*00ce4311SHyong Youb Kim RES_TYPE_RDMA2_DATA_WQ, /* RDMA datapath command WQ */ 57*00ce4311SHyong Youb Kim RES_TYPE_RDMA2_REG_WQ, /* RDMA registration command WQ */ 58*00ce4311SHyong Youb Kim RES_TYPE_RDMA2_CQ, /* RDMA datapath CQ */ 59*00ce4311SHyong Youb Kim RES_TYPE_MQ_RDMA2_DATA_WQ, /* RDMA datapath command WQ */ 60*00ce4311SHyong Youb Kim RES_TYPE_MQ_RDMA2_REG_WQ, /* RDMA registration command WQ */ 61*00ce4311SHyong Youb Kim RES_TYPE_MQ_RDMA2_CQ, /* RDMA datapath CQ */ 62*00ce4311SHyong Youb Kim RES_TYPE_PTP, /* PTP registers */ 63*00ce4311SHyong Youb Kim RES_TYPE_INTR_CTRL2, /* Extended INTR CTRL registers */ 64*00ce4311SHyong Youb Kim RES_TYPE_SRIOV_INTR, /* VF intr */ 65*00ce4311SHyong Youb Kim RES_TYPE_VF_WQ, /* VF WQ */ 66*00ce4311SHyong Youb Kim RES_TYPE_VF_RQ, /* VF RQ */ 67*00ce4311SHyong Youb Kim RES_TYPE_VF_CQ, /* VF CQ */ 68*00ce4311SHyong Youb Kim RES_TYPE_ADMIN_WQ, /* admin channel WQ */ 69*00ce4311SHyong Youb Kim RES_TYPE_ADMIN_RQ, /* admin channel RQ */ 70*00ce4311SHyong Youb Kim RES_TYPE_ADMIN_CQ, /* admin channel CQ */ 7172f3de30SBruce Richardson RES_TYPE_MAX, /* Count of resource types */ 7272f3de30SBruce Richardson }; 7372f3de30SBruce Richardson 7472f3de30SBruce Richardson struct vnic_resource_header { 7504e8ec74SJohn Daley uint32_t magic; 7604e8ec74SJohn Daley uint32_t version; 7772f3de30SBruce Richardson }; 7872f3de30SBruce Richardson 7972f3de30SBruce Richardson struct mgmt_barmap_hdr { 8004e8ec74SJohn Daley uint32_t magic; /* magic number */ 8104e8ec74SJohn Daley uint32_t version; /* header format version */ 8204e8ec74SJohn Daley uint16_t lif; /* loopback lif for mgmt frames */ 8304e8ec74SJohn Daley uint16_t pci_slot; /* installed pci slot */ 8472f3de30SBruce Richardson char serial[16]; /* card serial number */ 8572f3de30SBruce Richardson }; 8672f3de30SBruce Richardson 8772f3de30SBruce Richardson struct vnic_resource { 8804e8ec74SJohn Daley uint8_t type; 8904e8ec74SJohn Daley uint8_t bar; 9004e8ec74SJohn Daley uint8_t pad[2]; 9104e8ec74SJohn Daley uint32_t bar_offset; 9204e8ec74SJohn Daley uint32_t count; 9372f3de30SBruce Richardson }; 9472f3de30SBruce Richardson 9572f3de30SBruce Richardson #endif /* _VNIC_RESOURCE_H_ */ 96