12e99ea80SHyong Youb Kim /* SPDX-License-Identifier: BSD-3-Clause 22e99ea80SHyong Youb Kim * Copyright 2008-2017 Cisco Systems, Inc. All rights reserved. 372f3de30SBruce Richardson * Copyright 2007 Nuova Systems, Inc. All rights reserved. 472f3de30SBruce Richardson */ 572f3de30SBruce Richardson 672f3de30SBruce Richardson #ifndef _VNIC_ENIC_H_ 772f3de30SBruce Richardson #define _VNIC_ENIC_H_ 872f3de30SBruce Richardson 9bb34ffb8SJohn Daley /* Hardware intr coalesce timer is in units of 1.5us */ 10bb34ffb8SJohn Daley #define INTR_COALESCE_USEC_TO_HW(usec) ((usec) * 2 / 3) 11bb34ffb8SJohn Daley #define INTR_COALESCE_HW_TO_USEC(usec) ((usec) * 3 / 2) 12bb34ffb8SJohn Daley 1372f3de30SBruce Richardson /* Device-specific region: enet configuration */ 1472f3de30SBruce Richardson struct vnic_enet_config { 1504e8ec74SJohn Daley uint32_t flags; 1604e8ec74SJohn Daley uint32_t wq_desc_count; 1704e8ec74SJohn Daley uint32_t rq_desc_count; 1804e8ec74SJohn Daley uint16_t mtu; 1904e8ec74SJohn Daley uint16_t intr_timer_deprecated; 2004e8ec74SJohn Daley uint8_t intr_timer_type; 2104e8ec74SJohn Daley uint8_t intr_mode; 2272f3de30SBruce Richardson char devname[16]; 2304e8ec74SJohn Daley uint32_t intr_timer_usec; 2404e8ec74SJohn Daley uint16_t loop_tag; 2504e8ec74SJohn Daley uint16_t vf_rq_count; 2604e8ec74SJohn Daley uint16_t num_arfs; 2704e8ec74SJohn Daley uint64_t mem_paddr; 2804e8ec74SJohn Daley uint16_t rdma_qp_id; 2904e8ec74SJohn Daley uint16_t rdma_qp_count; 3004e8ec74SJohn Daley uint16_t rdma_resgrp; 3104e8ec74SJohn Daley uint32_t rdma_mr_id; 3204e8ec74SJohn Daley uint32_t rdma_mr_count; 3304e8ec74SJohn Daley uint32_t max_pkt_size; 34*9ca71a5bSJohn Daley uint16_t vf_subvnic_count; 35*9ca71a5bSJohn Daley uint16_t mq_subvnic_count; 36*9ca71a5bSJohn Daley uint32_t mq_flags; 37*9ca71a5bSJohn Daley 38*9ca71a5bSJohn Daley /* the following 3 fields are per-MQ-vnic counts */ 39*9ca71a5bSJohn Daley uint32_t mq_rdma_mr_count; 40*9ca71a5bSJohn Daley uint16_t mq_rdma_qp_count; 41*9ca71a5bSJohn Daley uint16_t mq_rdma_resgrp; 42*9ca71a5bSJohn Daley 43*9ca71a5bSJohn Daley uint16_t rdma_max_sq_ring_sz; 44*9ca71a5bSJohn Daley uint16_t rdma_max_rq_ring_sz; 45*9ca71a5bSJohn Daley uint32_t rdma_max_cq_ring_sz; 46*9ca71a5bSJohn Daley uint16_t rdma_max_wr_sge; 47*9ca71a5bSJohn Daley uint16_t rdma_max_mr_sge; 48*9ca71a5bSJohn Daley uint8_t rdma_max_rd_per_qp; 49*9ca71a5bSJohn Daley uint8_t unused; /* available */ 50*9ca71a5bSJohn Daley uint16_t mq_rdma_engine_count; 51*9ca71a5bSJohn Daley uint32_t intr_coal_tick_ns; /* coalescing timer tick in nsec */ 52*9ca71a5bSJohn Daley uint32_t max_rq_ring; /* MAX RQ ring size */ 53*9ca71a5bSJohn Daley uint32_t max_wq_ring; /* MAX WQ ring size */ 54*9ca71a5bSJohn Daley uint32_t max_cq_ring; /* MAX CQ ring size */ 55*9ca71a5bSJohn Daley uint32_t rdma_rsvd_lkey; /* Reserved (privileged) LKey */ 5672f3de30SBruce Richardson }; 5772f3de30SBruce Richardson 5872f3de30SBruce Richardson #define VENETF_TSO 0x1 /* TSO enabled */ 5972f3de30SBruce Richardson #define VENETF_LRO 0x2 /* LRO enabled */ 6072f3de30SBruce Richardson #define VENETF_RXCSUM 0x4 /* RX csum enabled */ 6172f3de30SBruce Richardson #define VENETF_TXCSUM 0x8 /* TX csum enabled */ 6272f3de30SBruce Richardson #define VENETF_RSS 0x10 /* RSS enabled */ 6372f3de30SBruce Richardson #define VENETF_RSSHASH_IPV4 0x20 /* Hash on IPv4 fields */ 6472f3de30SBruce Richardson #define VENETF_RSSHASH_TCPIPV4 0x40 /* Hash on TCP + IPv4 fields */ 6572f3de30SBruce Richardson #define VENETF_RSSHASH_IPV6 0x80 /* Hash on IPv6 fields */ 6672f3de30SBruce Richardson #define VENETF_RSSHASH_TCPIPV6 0x100 /* Hash on TCP + IPv6 fields */ 6772f3de30SBruce Richardson #define VENETF_RSSHASH_IPV6_EX 0x200 /* Hash on IPv6 extended fields */ 6872f3de30SBruce Richardson #define VENETF_RSSHASH_TCPIPV6_EX 0x400 /* Hash on TCP + IPv6 ext. fields */ 6972f3de30SBruce Richardson #define VENETF_LOOP 0x800 /* Loopback enabled */ 70bb34ffb8SJohn Daley #define VENETF_FAILOVER 0x1000 /* Fabric failover enabled */ 71bb34ffb8SJohn Daley #define VENETF_USPACE_NIC 0x2000 /* vHPC enabled */ 72bb34ffb8SJohn Daley #define VENETF_VMQ 0x4000 /* VMQ enabled */ 73bb34ffb8SJohn Daley #define VENETF_ARFS 0x8000 /* ARFS enabled */ 7472f3de30SBruce Richardson #define VENETF_VXLAN 0x10000 /* VxLAN offload */ 7572f3de30SBruce Richardson #define VENETF_NVGRE 0x20000 /* NVGRE offload */ 76bb34ffb8SJohn Daley #define VENETF_GRPINTR 0x40000 /* group interrupt */ 7794c35189SHyong Youb Kim #define VENETF_NICSWITCH 0x80000 /* NICSWITCH enabled */ 785bc989e6SHyong Youb Kim #define VENETF_RSSHASH_UDPIPV4 0x100000 /* Hash on UDP + IPv4 fields */ 795bc989e6SHyong Youb Kim #define VENETF_RSSHASH_UDPIPV6 0x200000 /* Hash on UDP + IPv6 fields */ 8061c7b522SJohn Daley #define VENETF_GENEVE 0x400000 /* GENEVE offload */ 81bb34ffb8SJohn Daley 8272f3de30SBruce Richardson #define VENET_INTR_TYPE_MIN 0 /* Timer specs min interrupt spacing */ 8372f3de30SBruce Richardson #define VENET_INTR_TYPE_IDLE 1 /* Timer specs idle time before irq */ 8472f3de30SBruce Richardson 8572f3de30SBruce Richardson #define VENET_INTR_MODE_ANY 0 /* Try MSI-X, then MSI, then INTx */ 8672f3de30SBruce Richardson #define VENET_INTR_MODE_MSI 1 /* Try MSI then INTx */ 8772f3de30SBruce Richardson #define VENET_INTR_MODE_INTX 2 /* Try INTx only */ 8872f3de30SBruce Richardson 8972f3de30SBruce Richardson #endif /* _VNIC_ENIC_H_ */ 90