1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <rte_string_fns.h> 35 #include <rte_ether.h> 36 #include <rte_ethdev_driver.h> 37 #include <rte_ethdev_pci.h> 38 #include <rte_tcp.h> 39 #include <rte_atomic.h> 40 #include <rte_dev.h> 41 #include <rte_errno.h> 42 #include <rte_version.h> 43 #include <rte_net.h> 44 45 #include "ena_ethdev.h" 46 #include "ena_logs.h" 47 #include "ena_platform.h" 48 #include "ena_com.h" 49 #include "ena_eth_com.h" 50 51 #include <ena_common_defs.h> 52 #include <ena_regs_defs.h> 53 #include <ena_admin_defs.h> 54 #include <ena_eth_io_defs.h> 55 56 #define DRV_MODULE_VER_MAJOR 2 57 #define DRV_MODULE_VER_MINOR 0 58 #define DRV_MODULE_VER_SUBMINOR 1 59 60 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 61 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 62 /*reverse version of ENA_IO_RXQ_IDX*/ 63 #define ENA_IO_RXQ_IDX_REV(q) ((q - 1) / 2) 64 65 /* While processing submitted and completed descriptors (rx and tx path 66 * respectively) in a loop it is desired to: 67 * - perform batch submissions while populating sumbissmion queue 68 * - avoid blocking transmission of other packets during cleanup phase 69 * Hence the utilization ratio of 1/8 of a queue size. 70 */ 71 #define ENA_RING_DESCS_RATIO(ring_size) (ring_size / 8) 72 73 #define __MERGE_64B_H_L(h, l) (((uint64_t)h << 32) | l) 74 #define TEST_BIT(val, bit_shift) (val & (1UL << bit_shift)) 75 76 #define GET_L4_HDR_LEN(mbuf) \ 77 ((rte_pktmbuf_mtod_offset(mbuf, struct rte_tcp_hdr *, \ 78 mbuf->l3_len + mbuf->l2_len)->data_off) >> 4) 79 80 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 81 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 82 #define ENA_HASH_KEY_SIZE 40 83 #define ETH_GSTRING_LEN 32 84 85 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 86 87 #define ENA_MIN_RING_DESC 128 88 89 enum ethtool_stringset { 90 ETH_SS_TEST = 0, 91 ETH_SS_STATS, 92 }; 93 94 struct ena_stats { 95 char name[ETH_GSTRING_LEN]; 96 int stat_offset; 97 }; 98 99 #define ENA_STAT_ENTRY(stat, stat_type) { \ 100 .name = #stat, \ 101 .stat_offset = offsetof(struct ena_stats_##stat_type, stat) \ 102 } 103 104 #define ENA_STAT_RX_ENTRY(stat) \ 105 ENA_STAT_ENTRY(stat, rx) 106 107 #define ENA_STAT_TX_ENTRY(stat) \ 108 ENA_STAT_ENTRY(stat, tx) 109 110 #define ENA_STAT_GLOBAL_ENTRY(stat) \ 111 ENA_STAT_ENTRY(stat, dev) 112 113 #define ENA_MAX_RING_SIZE_RX 8192 114 #define ENA_MAX_RING_SIZE_TX 1024 115 116 /* 117 * Each rte_memzone should have unique name. 118 * To satisfy it, count number of allocation and add it to name. 119 */ 120 uint32_t ena_alloc_cnt; 121 122 static const struct ena_stats ena_stats_global_strings[] = { 123 ENA_STAT_GLOBAL_ENTRY(wd_expired), 124 ENA_STAT_GLOBAL_ENTRY(dev_start), 125 ENA_STAT_GLOBAL_ENTRY(dev_stop), 126 }; 127 128 static const struct ena_stats ena_stats_tx_strings[] = { 129 ENA_STAT_TX_ENTRY(cnt), 130 ENA_STAT_TX_ENTRY(bytes), 131 ENA_STAT_TX_ENTRY(prepare_ctx_err), 132 ENA_STAT_TX_ENTRY(linearize), 133 ENA_STAT_TX_ENTRY(linearize_failed), 134 ENA_STAT_TX_ENTRY(tx_poll), 135 ENA_STAT_TX_ENTRY(doorbells), 136 ENA_STAT_TX_ENTRY(bad_req_id), 137 ENA_STAT_TX_ENTRY(available_desc), 138 }; 139 140 static const struct ena_stats ena_stats_rx_strings[] = { 141 ENA_STAT_RX_ENTRY(cnt), 142 ENA_STAT_RX_ENTRY(bytes), 143 ENA_STAT_RX_ENTRY(refill_partial), 144 ENA_STAT_RX_ENTRY(bad_csum), 145 ENA_STAT_RX_ENTRY(mbuf_alloc_fail), 146 ENA_STAT_RX_ENTRY(bad_desc_num), 147 ENA_STAT_RX_ENTRY(bad_req_id), 148 }; 149 150 #define ENA_STATS_ARRAY_GLOBAL ARRAY_SIZE(ena_stats_global_strings) 151 #define ENA_STATS_ARRAY_TX ARRAY_SIZE(ena_stats_tx_strings) 152 #define ENA_STATS_ARRAY_RX ARRAY_SIZE(ena_stats_rx_strings) 153 154 #define QUEUE_OFFLOADS (DEV_TX_OFFLOAD_TCP_CKSUM |\ 155 DEV_TX_OFFLOAD_UDP_CKSUM |\ 156 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 157 DEV_TX_OFFLOAD_TCP_TSO) 158 #define MBUF_OFFLOADS (PKT_TX_L4_MASK |\ 159 PKT_TX_IP_CKSUM |\ 160 PKT_TX_TCP_SEG) 161 162 /** Vendor ID used by Amazon devices */ 163 #define PCI_VENDOR_ID_AMAZON 0x1D0F 164 /** Amazon devices */ 165 #define PCI_DEVICE_ID_ENA_VF 0xEC20 166 #define PCI_DEVICE_ID_ENA_LLQ_VF 0xEC21 167 168 #define ENA_TX_OFFLOAD_MASK (\ 169 PKT_TX_L4_MASK | \ 170 PKT_TX_IPV6 | \ 171 PKT_TX_IPV4 | \ 172 PKT_TX_IP_CKSUM | \ 173 PKT_TX_TCP_SEG) 174 175 #define ENA_TX_OFFLOAD_NOTSUP_MASK \ 176 (PKT_TX_OFFLOAD_MASK ^ ENA_TX_OFFLOAD_MASK) 177 178 int ena_logtype_init; 179 int ena_logtype_driver; 180 181 static const struct rte_pci_id pci_id_ena_map[] = { 182 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_VF) }, 183 { RTE_PCI_DEVICE(PCI_VENDOR_ID_AMAZON, PCI_DEVICE_ID_ENA_LLQ_VF) }, 184 { .device_id = 0 }, 185 }; 186 187 static struct ena_aenq_handlers aenq_handlers; 188 189 static int ena_device_init(struct ena_com_dev *ena_dev, 190 struct ena_com_dev_get_features_ctx *get_feat_ctx, 191 bool *wd_state); 192 static int ena_dev_configure(struct rte_eth_dev *dev); 193 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 194 uint16_t nb_pkts); 195 static uint16_t eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 196 uint16_t nb_pkts); 197 static int ena_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 198 uint16_t nb_desc, unsigned int socket_id, 199 const struct rte_eth_txconf *tx_conf); 200 static int ena_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 201 uint16_t nb_desc, unsigned int socket_id, 202 const struct rte_eth_rxconf *rx_conf, 203 struct rte_mempool *mp); 204 static uint16_t eth_ena_recv_pkts(void *rx_queue, 205 struct rte_mbuf **rx_pkts, uint16_t nb_pkts); 206 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count); 207 static void ena_init_rings(struct ena_adapter *adapter); 208 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 209 static int ena_start(struct rte_eth_dev *dev); 210 static void ena_stop(struct rte_eth_dev *dev); 211 static void ena_close(struct rte_eth_dev *dev); 212 static int ena_dev_reset(struct rte_eth_dev *dev); 213 static int ena_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 214 static void ena_rx_queue_release_all(struct rte_eth_dev *dev); 215 static void ena_tx_queue_release_all(struct rte_eth_dev *dev); 216 static void ena_rx_queue_release(void *queue); 217 static void ena_tx_queue_release(void *queue); 218 static void ena_rx_queue_release_bufs(struct ena_ring *ring); 219 static void ena_tx_queue_release_bufs(struct ena_ring *ring); 220 static int ena_link_update(struct rte_eth_dev *dev, 221 int wait_to_complete); 222 static int ena_create_io_queue(struct ena_ring *ring); 223 static void ena_queue_stop(struct ena_ring *ring); 224 static void ena_queue_stop_all(struct rte_eth_dev *dev, 225 enum ena_ring_type ring_type); 226 static int ena_queue_start(struct ena_ring *ring); 227 static int ena_queue_start_all(struct rte_eth_dev *dev, 228 enum ena_ring_type ring_type); 229 static void ena_stats_restart(struct rte_eth_dev *dev); 230 static int ena_infos_get(struct rte_eth_dev *dev, 231 struct rte_eth_dev_info *dev_info); 232 static int ena_rss_reta_update(struct rte_eth_dev *dev, 233 struct rte_eth_rss_reta_entry64 *reta_conf, 234 uint16_t reta_size); 235 static int ena_rss_reta_query(struct rte_eth_dev *dev, 236 struct rte_eth_rss_reta_entry64 *reta_conf, 237 uint16_t reta_size); 238 static void ena_interrupt_handler_rte(void *cb_arg); 239 static void ena_timer_wd_callback(struct rte_timer *timer, void *arg); 240 static void ena_destroy_device(struct rte_eth_dev *eth_dev); 241 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev); 242 static int ena_xstats_get_names(struct rte_eth_dev *dev, 243 struct rte_eth_xstat_name *xstats_names, 244 unsigned int n); 245 static int ena_xstats_get(struct rte_eth_dev *dev, 246 struct rte_eth_xstat *stats, 247 unsigned int n); 248 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 249 const uint64_t *ids, 250 uint64_t *values, 251 unsigned int n); 252 253 static const struct eth_dev_ops ena_dev_ops = { 254 .dev_configure = ena_dev_configure, 255 .dev_infos_get = ena_infos_get, 256 .rx_queue_setup = ena_rx_queue_setup, 257 .tx_queue_setup = ena_tx_queue_setup, 258 .dev_start = ena_start, 259 .dev_stop = ena_stop, 260 .link_update = ena_link_update, 261 .stats_get = ena_stats_get, 262 .xstats_get_names = ena_xstats_get_names, 263 .xstats_get = ena_xstats_get, 264 .xstats_get_by_id = ena_xstats_get_by_id, 265 .mtu_set = ena_mtu_set, 266 .rx_queue_release = ena_rx_queue_release, 267 .tx_queue_release = ena_tx_queue_release, 268 .dev_close = ena_close, 269 .dev_reset = ena_dev_reset, 270 .reta_update = ena_rss_reta_update, 271 .reta_query = ena_rss_reta_query, 272 }; 273 274 static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf, 275 struct ena_com_rx_ctx *ena_rx_ctx) 276 { 277 uint64_t ol_flags = 0; 278 uint32_t packet_type = 0; 279 280 if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) 281 packet_type |= RTE_PTYPE_L4_TCP; 282 else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP) 283 packet_type |= RTE_PTYPE_L4_UDP; 284 285 if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) 286 packet_type |= RTE_PTYPE_L3_IPV4; 287 else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) 288 packet_type |= RTE_PTYPE_L3_IPV6; 289 290 if (unlikely(ena_rx_ctx->l4_csum_err)) 291 ol_flags |= PKT_RX_L4_CKSUM_BAD; 292 if (unlikely(ena_rx_ctx->l3_csum_err)) 293 ol_flags |= PKT_RX_IP_CKSUM_BAD; 294 295 mbuf->ol_flags = ol_flags; 296 mbuf->packet_type = packet_type; 297 } 298 299 static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf, 300 struct ena_com_tx_ctx *ena_tx_ctx, 301 uint64_t queue_offloads) 302 { 303 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta; 304 305 if ((mbuf->ol_flags & MBUF_OFFLOADS) && 306 (queue_offloads & QUEUE_OFFLOADS)) { 307 /* check if TSO is required */ 308 if ((mbuf->ol_flags & PKT_TX_TCP_SEG) && 309 (queue_offloads & DEV_TX_OFFLOAD_TCP_TSO)) { 310 ena_tx_ctx->tso_enable = true; 311 312 ena_meta->l4_hdr_len = GET_L4_HDR_LEN(mbuf); 313 } 314 315 /* check if L3 checksum is needed */ 316 if ((mbuf->ol_flags & PKT_TX_IP_CKSUM) && 317 (queue_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) 318 ena_tx_ctx->l3_csum_enable = true; 319 320 if (mbuf->ol_flags & PKT_TX_IPV6) { 321 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6; 322 } else { 323 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4; 324 325 /* set don't fragment (DF) flag */ 326 if (mbuf->packet_type & 327 (RTE_PTYPE_L4_NONFRAG 328 | RTE_PTYPE_INNER_L4_NONFRAG)) 329 ena_tx_ctx->df = true; 330 } 331 332 /* check if L4 checksum is needed */ 333 if (((mbuf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) && 334 (queue_offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) { 335 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP; 336 ena_tx_ctx->l4_csum_enable = true; 337 } else if (((mbuf->ol_flags & PKT_TX_L4_MASK) == 338 PKT_TX_UDP_CKSUM) && 339 (queue_offloads & DEV_TX_OFFLOAD_UDP_CKSUM)) { 340 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP; 341 ena_tx_ctx->l4_csum_enable = true; 342 } else { 343 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UNKNOWN; 344 ena_tx_ctx->l4_csum_enable = false; 345 } 346 347 ena_meta->mss = mbuf->tso_segsz; 348 ena_meta->l3_hdr_len = mbuf->l3_len; 349 ena_meta->l3_hdr_offset = mbuf->l2_len; 350 351 ena_tx_ctx->meta_valid = true; 352 } else { 353 ena_tx_ctx->meta_valid = false; 354 } 355 } 356 357 static inline int validate_rx_req_id(struct ena_ring *rx_ring, uint16_t req_id) 358 { 359 if (likely(req_id < rx_ring->ring_size)) 360 return 0; 361 362 RTE_LOG(ERR, PMD, "Invalid rx req_id: %hu\n", req_id); 363 364 rx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_RX_REQ_ID; 365 rx_ring->adapter->trigger_reset = true; 366 ++rx_ring->rx_stats.bad_req_id; 367 368 return -EFAULT; 369 } 370 371 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id) 372 { 373 struct ena_tx_buffer *tx_info = NULL; 374 375 if (likely(req_id < tx_ring->ring_size)) { 376 tx_info = &tx_ring->tx_buffer_info[req_id]; 377 if (likely(tx_info->mbuf)) 378 return 0; 379 } 380 381 if (tx_info) 382 RTE_LOG(ERR, PMD, "tx_info doesn't have valid mbuf\n"); 383 else 384 RTE_LOG(ERR, PMD, "Invalid req_id: %hu\n", req_id); 385 386 /* Trigger device reset */ 387 ++tx_ring->tx_stats.bad_req_id; 388 tx_ring->adapter->reset_reason = ENA_REGS_RESET_INV_TX_REQ_ID; 389 tx_ring->adapter->trigger_reset = true; 390 return -EFAULT; 391 } 392 393 static void ena_config_host_info(struct ena_com_dev *ena_dev) 394 { 395 struct ena_admin_host_info *host_info; 396 int rc; 397 398 /* Allocate only the host info */ 399 rc = ena_com_allocate_host_info(ena_dev); 400 if (rc) { 401 RTE_LOG(ERR, PMD, "Cannot allocate host info\n"); 402 return; 403 } 404 405 host_info = ena_dev->host_attr.host_info; 406 407 host_info->os_type = ENA_ADMIN_OS_DPDK; 408 host_info->kernel_ver = RTE_VERSION; 409 strlcpy((char *)host_info->kernel_ver_str, rte_version(), 410 sizeof(host_info->kernel_ver_str)); 411 host_info->os_dist = RTE_VERSION; 412 strlcpy((char *)host_info->os_dist_str, rte_version(), 413 sizeof(host_info->os_dist_str)); 414 host_info->driver_version = 415 (DRV_MODULE_VER_MAJOR) | 416 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) | 417 (DRV_MODULE_VER_SUBMINOR << 418 ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT); 419 host_info->num_cpus = rte_lcore_count(); 420 421 rc = ena_com_set_host_attributes(ena_dev); 422 if (rc) { 423 if (rc == -ENA_COM_UNSUPPORTED) 424 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 425 else 426 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 427 428 goto err; 429 } 430 431 return; 432 433 err: 434 ena_com_delete_host_info(ena_dev); 435 } 436 437 /* This function calculates the number of xstats based on the current config */ 438 static unsigned int ena_xstats_calc_num(struct rte_eth_dev *dev) 439 { 440 return ENA_STATS_ARRAY_GLOBAL + 441 (dev->data->nb_tx_queues * ENA_STATS_ARRAY_TX) + 442 (dev->data->nb_rx_queues * ENA_STATS_ARRAY_RX); 443 } 444 445 static void ena_config_debug_area(struct ena_adapter *adapter) 446 { 447 u32 debug_area_size; 448 int rc, ss_count; 449 450 ss_count = ena_xstats_calc_num(adapter->rte_dev); 451 452 /* allocate 32 bytes for each string and 64bit for the value */ 453 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count; 454 455 rc = ena_com_allocate_debug_area(&adapter->ena_dev, debug_area_size); 456 if (rc) { 457 RTE_LOG(ERR, PMD, "Cannot allocate debug area\n"); 458 return; 459 } 460 461 rc = ena_com_set_host_attributes(&adapter->ena_dev); 462 if (rc) { 463 if (rc == -ENA_COM_UNSUPPORTED) 464 RTE_LOG(WARNING, PMD, "Cannot set host attributes\n"); 465 else 466 RTE_LOG(ERR, PMD, "Cannot set host attributes\n"); 467 468 goto err; 469 } 470 471 return; 472 err: 473 ena_com_delete_debug_area(&adapter->ena_dev); 474 } 475 476 static void ena_close(struct rte_eth_dev *dev) 477 { 478 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); 479 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 480 struct ena_adapter *adapter = dev->data->dev_private; 481 482 if (adapter->state == ENA_ADAPTER_STATE_RUNNING) 483 ena_stop(dev); 484 adapter->state = ENA_ADAPTER_STATE_CLOSED; 485 486 ena_rx_queue_release_all(dev); 487 ena_tx_queue_release_all(dev); 488 489 rte_free(adapter->drv_stats); 490 adapter->drv_stats = NULL; 491 492 rte_intr_disable(intr_handle); 493 rte_intr_callback_unregister(intr_handle, 494 ena_interrupt_handler_rte, 495 adapter); 496 497 /* 498 * MAC is not allocated dynamically. Setting NULL should prevent from 499 * release of the resource in the rte_eth_dev_release_port(). 500 */ 501 dev->data->mac_addrs = NULL; 502 } 503 504 static int 505 ena_dev_reset(struct rte_eth_dev *dev) 506 { 507 int rc = 0; 508 509 ena_destroy_device(dev); 510 rc = eth_ena_dev_init(dev); 511 if (rc) 512 PMD_INIT_LOG(CRIT, "Cannot initialize device"); 513 514 return rc; 515 } 516 517 static int ena_rss_reta_update(struct rte_eth_dev *dev, 518 struct rte_eth_rss_reta_entry64 *reta_conf, 519 uint16_t reta_size) 520 { 521 struct ena_adapter *adapter = dev->data->dev_private; 522 struct ena_com_dev *ena_dev = &adapter->ena_dev; 523 int rc, i; 524 u16 entry_value; 525 int conf_idx; 526 int idx; 527 528 if ((reta_size == 0) || (reta_conf == NULL)) 529 return -EINVAL; 530 531 if (reta_size > ENA_RX_RSS_TABLE_SIZE) { 532 RTE_LOG(WARNING, PMD, 533 "indirection table %d is bigger than supported (%d)\n", 534 reta_size, ENA_RX_RSS_TABLE_SIZE); 535 return -EINVAL; 536 } 537 538 for (i = 0 ; i < reta_size ; i++) { 539 /* each reta_conf is for 64 entries. 540 * to support 128 we use 2 conf of 64 541 */ 542 conf_idx = i / RTE_RETA_GROUP_SIZE; 543 idx = i % RTE_RETA_GROUP_SIZE; 544 if (TEST_BIT(reta_conf[conf_idx].mask, idx)) { 545 entry_value = 546 ENA_IO_RXQ_IDX(reta_conf[conf_idx].reta[idx]); 547 548 rc = ena_com_indirect_table_fill_entry(ena_dev, 549 i, 550 entry_value); 551 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 552 RTE_LOG(ERR, PMD, 553 "Cannot fill indirect table\n"); 554 return rc; 555 } 556 } 557 } 558 559 rc = ena_com_indirect_table_set(ena_dev); 560 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 561 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 562 return rc; 563 } 564 565 RTE_LOG(DEBUG, PMD, "%s(): RSS configured %d entries for port %d\n", 566 __func__, reta_size, adapter->rte_dev->data->port_id); 567 568 return 0; 569 } 570 571 /* Query redirection table. */ 572 static int ena_rss_reta_query(struct rte_eth_dev *dev, 573 struct rte_eth_rss_reta_entry64 *reta_conf, 574 uint16_t reta_size) 575 { 576 struct ena_adapter *adapter = dev->data->dev_private; 577 struct ena_com_dev *ena_dev = &adapter->ena_dev; 578 int rc; 579 int i; 580 u32 indirect_table[ENA_RX_RSS_TABLE_SIZE] = {0}; 581 int reta_conf_idx; 582 int reta_idx; 583 584 if (reta_size == 0 || reta_conf == NULL || 585 (reta_size > RTE_RETA_GROUP_SIZE && ((reta_conf + 1) == NULL))) 586 return -EINVAL; 587 588 rc = ena_com_indirect_table_get(ena_dev, indirect_table); 589 if (unlikely(rc && rc != ENA_COM_UNSUPPORTED)) { 590 RTE_LOG(ERR, PMD, "cannot get indirect table\n"); 591 return -ENOTSUP; 592 } 593 594 for (i = 0 ; i < reta_size ; i++) { 595 reta_conf_idx = i / RTE_RETA_GROUP_SIZE; 596 reta_idx = i % RTE_RETA_GROUP_SIZE; 597 if (TEST_BIT(reta_conf[reta_conf_idx].mask, reta_idx)) 598 reta_conf[reta_conf_idx].reta[reta_idx] = 599 ENA_IO_RXQ_IDX_REV(indirect_table[i]); 600 } 601 602 return 0; 603 } 604 605 static int ena_rss_init_default(struct ena_adapter *adapter) 606 { 607 struct ena_com_dev *ena_dev = &adapter->ena_dev; 608 uint16_t nb_rx_queues = adapter->rte_dev->data->nb_rx_queues; 609 int rc, i; 610 u32 val; 611 612 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE); 613 if (unlikely(rc)) { 614 RTE_LOG(ERR, PMD, "Cannot init indirect table\n"); 615 goto err_rss_init; 616 } 617 618 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) { 619 val = i % nb_rx_queues; 620 rc = ena_com_indirect_table_fill_entry(ena_dev, i, 621 ENA_IO_RXQ_IDX(val)); 622 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 623 RTE_LOG(ERR, PMD, "Cannot fill indirect table\n"); 624 goto err_fill_indir; 625 } 626 } 627 628 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL, 629 ENA_HASH_KEY_SIZE, 0xFFFFFFFF); 630 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 631 RTE_LOG(INFO, PMD, "Cannot fill hash function\n"); 632 goto err_fill_indir; 633 } 634 635 rc = ena_com_set_default_hash_ctrl(ena_dev); 636 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 637 RTE_LOG(INFO, PMD, "Cannot fill hash control\n"); 638 goto err_fill_indir; 639 } 640 641 rc = ena_com_indirect_table_set(ena_dev); 642 if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) { 643 RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n"); 644 goto err_fill_indir; 645 } 646 RTE_LOG(DEBUG, PMD, "RSS configured for port %d\n", 647 adapter->rte_dev->data->port_id); 648 649 return 0; 650 651 err_fill_indir: 652 ena_com_rss_destroy(ena_dev); 653 err_rss_init: 654 655 return rc; 656 } 657 658 static void ena_rx_queue_release_all(struct rte_eth_dev *dev) 659 { 660 struct ena_ring **queues = (struct ena_ring **)dev->data->rx_queues; 661 int nb_queues = dev->data->nb_rx_queues; 662 int i; 663 664 for (i = 0; i < nb_queues; i++) 665 ena_rx_queue_release(queues[i]); 666 } 667 668 static void ena_tx_queue_release_all(struct rte_eth_dev *dev) 669 { 670 struct ena_ring **queues = (struct ena_ring **)dev->data->tx_queues; 671 int nb_queues = dev->data->nb_tx_queues; 672 int i; 673 674 for (i = 0; i < nb_queues; i++) 675 ena_tx_queue_release(queues[i]); 676 } 677 678 static void ena_rx_queue_release(void *queue) 679 { 680 struct ena_ring *ring = (struct ena_ring *)queue; 681 682 /* Free ring resources */ 683 if (ring->rx_buffer_info) 684 rte_free(ring->rx_buffer_info); 685 ring->rx_buffer_info = NULL; 686 687 if (ring->rx_refill_buffer) 688 rte_free(ring->rx_refill_buffer); 689 ring->rx_refill_buffer = NULL; 690 691 if (ring->empty_rx_reqs) 692 rte_free(ring->empty_rx_reqs); 693 ring->empty_rx_reqs = NULL; 694 695 ring->configured = 0; 696 697 RTE_LOG(NOTICE, PMD, "RX Queue %d:%d released\n", 698 ring->port_id, ring->id); 699 } 700 701 static void ena_tx_queue_release(void *queue) 702 { 703 struct ena_ring *ring = (struct ena_ring *)queue; 704 705 /* Free ring resources */ 706 if (ring->push_buf_intermediate_buf) 707 rte_free(ring->push_buf_intermediate_buf); 708 709 if (ring->tx_buffer_info) 710 rte_free(ring->tx_buffer_info); 711 712 if (ring->empty_tx_reqs) 713 rte_free(ring->empty_tx_reqs); 714 715 ring->empty_tx_reqs = NULL; 716 ring->tx_buffer_info = NULL; 717 ring->push_buf_intermediate_buf = NULL; 718 719 ring->configured = 0; 720 721 RTE_LOG(NOTICE, PMD, "TX Queue %d:%d released\n", 722 ring->port_id, ring->id); 723 } 724 725 static void ena_rx_queue_release_bufs(struct ena_ring *ring) 726 { 727 unsigned int i; 728 729 for (i = 0; i < ring->ring_size; ++i) 730 if (ring->rx_buffer_info[i]) { 731 rte_mbuf_raw_free(ring->rx_buffer_info[i]); 732 ring->rx_buffer_info[i] = NULL; 733 } 734 } 735 736 static void ena_tx_queue_release_bufs(struct ena_ring *ring) 737 { 738 unsigned int i; 739 740 for (i = 0; i < ring->ring_size; ++i) { 741 struct ena_tx_buffer *tx_buf = &ring->tx_buffer_info[i]; 742 743 if (tx_buf->mbuf) 744 rte_pktmbuf_free(tx_buf->mbuf); 745 } 746 } 747 748 static int ena_link_update(struct rte_eth_dev *dev, 749 __rte_unused int wait_to_complete) 750 { 751 struct rte_eth_link *link = &dev->data->dev_link; 752 struct ena_adapter *adapter = dev->data->dev_private; 753 754 link->link_status = adapter->link_status ? ETH_LINK_UP : ETH_LINK_DOWN; 755 link->link_speed = ETH_SPEED_NUM_NONE; 756 link->link_duplex = ETH_LINK_FULL_DUPLEX; 757 758 return 0; 759 } 760 761 static int ena_queue_start_all(struct rte_eth_dev *dev, 762 enum ena_ring_type ring_type) 763 { 764 struct ena_adapter *adapter = dev->data->dev_private; 765 struct ena_ring *queues = NULL; 766 int nb_queues; 767 int i = 0; 768 int rc = 0; 769 770 if (ring_type == ENA_RING_TYPE_RX) { 771 queues = adapter->rx_ring; 772 nb_queues = dev->data->nb_rx_queues; 773 } else { 774 queues = adapter->tx_ring; 775 nb_queues = dev->data->nb_tx_queues; 776 } 777 for (i = 0; i < nb_queues; i++) { 778 if (queues[i].configured) { 779 if (ring_type == ENA_RING_TYPE_RX) { 780 ena_assert_msg( 781 dev->data->rx_queues[i] == &queues[i], 782 "Inconsistent state of rx queues\n"); 783 } else { 784 ena_assert_msg( 785 dev->data->tx_queues[i] == &queues[i], 786 "Inconsistent state of tx queues\n"); 787 } 788 789 rc = ena_queue_start(&queues[i]); 790 791 if (rc) { 792 PMD_INIT_LOG(ERR, 793 "failed to start queue %d type(%d)", 794 i, ring_type); 795 goto err; 796 } 797 } 798 } 799 800 return 0; 801 802 err: 803 while (i--) 804 if (queues[i].configured) 805 ena_queue_stop(&queues[i]); 806 807 return rc; 808 } 809 810 static uint32_t ena_get_mtu_conf(struct ena_adapter *adapter) 811 { 812 uint32_t max_frame_len = adapter->max_mtu; 813 814 if (adapter->rte_eth_dev_data->dev_conf.rxmode.offloads & 815 DEV_RX_OFFLOAD_JUMBO_FRAME) 816 max_frame_len = 817 adapter->rte_eth_dev_data->dev_conf.rxmode.max_rx_pkt_len; 818 819 return max_frame_len; 820 } 821 822 static int ena_check_valid_conf(struct ena_adapter *adapter) 823 { 824 uint32_t max_frame_len = ena_get_mtu_conf(adapter); 825 826 if (max_frame_len > adapter->max_mtu || max_frame_len < ENA_MIN_MTU) { 827 PMD_INIT_LOG(ERR, "Unsupported MTU of %d. " 828 "max mtu: %d, min mtu: %d", 829 max_frame_len, adapter->max_mtu, ENA_MIN_MTU); 830 return ENA_COM_UNSUPPORTED; 831 } 832 833 return 0; 834 } 835 836 static int 837 ena_calc_queue_size(struct ena_calc_queue_size_ctx *ctx) 838 { 839 struct ena_admin_feature_llq_desc *llq = &ctx->get_feat_ctx->llq; 840 struct ena_com_dev *ena_dev = ctx->ena_dev; 841 uint32_t tx_queue_size = ENA_MAX_RING_SIZE_TX; 842 uint32_t rx_queue_size = ENA_MAX_RING_SIZE_RX; 843 844 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 845 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 846 &ctx->get_feat_ctx->max_queue_ext.max_queue_ext; 847 rx_queue_size = RTE_MIN(rx_queue_size, 848 max_queue_ext->max_rx_cq_depth); 849 rx_queue_size = RTE_MIN(rx_queue_size, 850 max_queue_ext->max_rx_sq_depth); 851 tx_queue_size = RTE_MIN(tx_queue_size, 852 max_queue_ext->max_tx_cq_depth); 853 854 if (ena_dev->tx_mem_queue_type == 855 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 856 tx_queue_size = RTE_MIN(tx_queue_size, 857 llq->max_llq_depth); 858 } else { 859 tx_queue_size = RTE_MIN(tx_queue_size, 860 max_queue_ext->max_tx_sq_depth); 861 } 862 863 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 864 max_queue_ext->max_per_packet_rx_descs); 865 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 866 max_queue_ext->max_per_packet_tx_descs); 867 } else { 868 struct ena_admin_queue_feature_desc *max_queues = 869 &ctx->get_feat_ctx->max_queues; 870 rx_queue_size = RTE_MIN(rx_queue_size, 871 max_queues->max_cq_depth); 872 rx_queue_size = RTE_MIN(rx_queue_size, 873 max_queues->max_sq_depth); 874 tx_queue_size = RTE_MIN(tx_queue_size, 875 max_queues->max_cq_depth); 876 877 if (ena_dev->tx_mem_queue_type == 878 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 879 tx_queue_size = RTE_MIN(tx_queue_size, 880 llq->max_llq_depth); 881 } else { 882 tx_queue_size = RTE_MIN(tx_queue_size, 883 max_queues->max_sq_depth); 884 } 885 886 ctx->max_rx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 887 max_queues->max_packet_tx_descs); 888 ctx->max_tx_sgl_size = RTE_MIN(ENA_PKT_MAX_BUFS, 889 max_queues->max_packet_rx_descs); 890 } 891 892 /* Round down to the nearest power of 2 */ 893 rx_queue_size = rte_align32prevpow2(rx_queue_size); 894 tx_queue_size = rte_align32prevpow2(tx_queue_size); 895 896 if (unlikely(rx_queue_size == 0 || tx_queue_size == 0)) { 897 PMD_INIT_LOG(ERR, "Invalid queue size"); 898 return -EFAULT; 899 } 900 901 ctx->rx_queue_size = rx_queue_size; 902 ctx->tx_queue_size = tx_queue_size; 903 904 return 0; 905 } 906 907 static void ena_stats_restart(struct rte_eth_dev *dev) 908 { 909 struct ena_adapter *adapter = dev->data->dev_private; 910 911 rte_atomic64_init(&adapter->drv_stats->ierrors); 912 rte_atomic64_init(&adapter->drv_stats->oerrors); 913 rte_atomic64_init(&adapter->drv_stats->rx_nombuf); 914 rte_atomic64_init(&adapter->drv_stats->rx_drops); 915 } 916 917 static int ena_stats_get(struct rte_eth_dev *dev, 918 struct rte_eth_stats *stats) 919 { 920 struct ena_admin_basic_stats ena_stats; 921 struct ena_adapter *adapter = dev->data->dev_private; 922 struct ena_com_dev *ena_dev = &adapter->ena_dev; 923 int rc; 924 int i; 925 int max_rings_stats; 926 927 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 928 return -ENOTSUP; 929 930 memset(&ena_stats, 0, sizeof(ena_stats)); 931 rc = ena_com_get_dev_basic_stats(ena_dev, &ena_stats); 932 if (unlikely(rc)) { 933 RTE_LOG(ERR, PMD, "Could not retrieve statistics from ENA\n"); 934 return rc; 935 } 936 937 /* Set of basic statistics from ENA */ 938 stats->ipackets = __MERGE_64B_H_L(ena_stats.rx_pkts_high, 939 ena_stats.rx_pkts_low); 940 stats->opackets = __MERGE_64B_H_L(ena_stats.tx_pkts_high, 941 ena_stats.tx_pkts_low); 942 stats->ibytes = __MERGE_64B_H_L(ena_stats.rx_bytes_high, 943 ena_stats.rx_bytes_low); 944 stats->obytes = __MERGE_64B_H_L(ena_stats.tx_bytes_high, 945 ena_stats.tx_bytes_low); 946 947 /* Driver related stats */ 948 stats->imissed = rte_atomic64_read(&adapter->drv_stats->rx_drops); 949 stats->ierrors = rte_atomic64_read(&adapter->drv_stats->ierrors); 950 stats->oerrors = rte_atomic64_read(&adapter->drv_stats->oerrors); 951 stats->rx_nombuf = rte_atomic64_read(&adapter->drv_stats->rx_nombuf); 952 953 max_rings_stats = RTE_MIN(dev->data->nb_rx_queues, 954 RTE_ETHDEV_QUEUE_STAT_CNTRS); 955 for (i = 0; i < max_rings_stats; ++i) { 956 struct ena_stats_rx *rx_stats = &adapter->rx_ring[i].rx_stats; 957 958 stats->q_ibytes[i] = rx_stats->bytes; 959 stats->q_ipackets[i] = rx_stats->cnt; 960 stats->q_errors[i] = rx_stats->bad_desc_num + 961 rx_stats->bad_req_id; 962 } 963 964 max_rings_stats = RTE_MIN(dev->data->nb_tx_queues, 965 RTE_ETHDEV_QUEUE_STAT_CNTRS); 966 for (i = 0; i < max_rings_stats; ++i) { 967 struct ena_stats_tx *tx_stats = &adapter->tx_ring[i].tx_stats; 968 969 stats->q_obytes[i] = tx_stats->bytes; 970 stats->q_opackets[i] = tx_stats->cnt; 971 } 972 973 return 0; 974 } 975 976 static int ena_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 977 { 978 struct ena_adapter *adapter; 979 struct ena_com_dev *ena_dev; 980 int rc = 0; 981 982 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 983 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 984 adapter = dev->data->dev_private; 985 986 ena_dev = &adapter->ena_dev; 987 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 988 989 if (mtu > ena_get_mtu_conf(adapter) || mtu < ENA_MIN_MTU) { 990 RTE_LOG(ERR, PMD, 991 "Invalid MTU setting. new_mtu: %d " 992 "max mtu: %d min mtu: %d\n", 993 mtu, ena_get_mtu_conf(adapter), ENA_MIN_MTU); 994 return -EINVAL; 995 } 996 997 rc = ena_com_set_dev_mtu(ena_dev, mtu); 998 if (rc) 999 RTE_LOG(ERR, PMD, "Could not set MTU: %d\n", mtu); 1000 else 1001 RTE_LOG(NOTICE, PMD, "Set MTU: %d\n", mtu); 1002 1003 return rc; 1004 } 1005 1006 static int ena_start(struct rte_eth_dev *dev) 1007 { 1008 struct ena_adapter *adapter = dev->data->dev_private; 1009 uint64_t ticks; 1010 int rc = 0; 1011 1012 rc = ena_check_valid_conf(adapter); 1013 if (rc) 1014 return rc; 1015 1016 rc = ena_queue_start_all(dev, ENA_RING_TYPE_RX); 1017 if (rc) 1018 return rc; 1019 1020 rc = ena_queue_start_all(dev, ENA_RING_TYPE_TX); 1021 if (rc) 1022 goto err_start_tx; 1023 1024 if (adapter->rte_dev->data->dev_conf.rxmode.mq_mode & 1025 ETH_MQ_RX_RSS_FLAG && adapter->rte_dev->data->nb_rx_queues > 0) { 1026 rc = ena_rss_init_default(adapter); 1027 if (rc) 1028 goto err_rss_init; 1029 } 1030 1031 ena_stats_restart(dev); 1032 1033 adapter->timestamp_wd = rte_get_timer_cycles(); 1034 adapter->keep_alive_timeout = ENA_DEVICE_KALIVE_TIMEOUT; 1035 1036 ticks = rte_get_timer_hz(); 1037 rte_timer_reset(&adapter->timer_wd, ticks, PERIODICAL, rte_lcore_id(), 1038 ena_timer_wd_callback, adapter); 1039 1040 ++adapter->dev_stats.dev_start; 1041 adapter->state = ENA_ADAPTER_STATE_RUNNING; 1042 1043 return 0; 1044 1045 err_rss_init: 1046 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1047 err_start_tx: 1048 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1049 return rc; 1050 } 1051 1052 static void ena_stop(struct rte_eth_dev *dev) 1053 { 1054 struct ena_adapter *adapter = dev->data->dev_private; 1055 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1056 int rc; 1057 1058 rte_timer_stop_sync(&adapter->timer_wd); 1059 ena_queue_stop_all(dev, ENA_RING_TYPE_TX); 1060 ena_queue_stop_all(dev, ENA_RING_TYPE_RX); 1061 1062 if (adapter->trigger_reset) { 1063 rc = ena_com_dev_reset(ena_dev, adapter->reset_reason); 1064 if (rc) 1065 RTE_LOG(ERR, PMD, "Device reset failed rc=%d\n", rc); 1066 } 1067 1068 ++adapter->dev_stats.dev_stop; 1069 adapter->state = ENA_ADAPTER_STATE_STOPPED; 1070 } 1071 1072 static int ena_create_io_queue(struct ena_ring *ring) 1073 { 1074 struct ena_adapter *adapter; 1075 struct ena_com_dev *ena_dev; 1076 struct ena_com_create_io_ctx ctx = 1077 /* policy set to _HOST just to satisfy icc compiler */ 1078 { ENA_ADMIN_PLACEMENT_POLICY_HOST, 1079 0, 0, 0, 0, 0 }; 1080 uint16_t ena_qid; 1081 unsigned int i; 1082 int rc; 1083 1084 adapter = ring->adapter; 1085 ena_dev = &adapter->ena_dev; 1086 1087 if (ring->type == ENA_RING_TYPE_TX) { 1088 ena_qid = ENA_IO_TXQ_IDX(ring->id); 1089 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX; 1090 ctx.mem_queue_type = ena_dev->tx_mem_queue_type; 1091 ctx.queue_size = adapter->tx_ring_size; 1092 for (i = 0; i < ring->ring_size; i++) 1093 ring->empty_tx_reqs[i] = i; 1094 } else { 1095 ena_qid = ENA_IO_RXQ_IDX(ring->id); 1096 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX; 1097 ctx.queue_size = adapter->rx_ring_size; 1098 for (i = 0; i < ring->ring_size; i++) 1099 ring->empty_rx_reqs[i] = i; 1100 } 1101 ctx.qid = ena_qid; 1102 ctx.msix_vector = -1; /* interrupts not used */ 1103 ctx.numa_node = ring->numa_socket_id; 1104 1105 rc = ena_com_create_io_queue(ena_dev, &ctx); 1106 if (rc) { 1107 RTE_LOG(ERR, PMD, 1108 "failed to create io queue #%d (qid:%d) rc: %d\n", 1109 ring->id, ena_qid, rc); 1110 return rc; 1111 } 1112 1113 rc = ena_com_get_io_handlers(ena_dev, ena_qid, 1114 &ring->ena_com_io_sq, 1115 &ring->ena_com_io_cq); 1116 if (rc) { 1117 RTE_LOG(ERR, PMD, 1118 "Failed to get io queue handlers. queue num %d rc: %d\n", 1119 ring->id, rc); 1120 ena_com_destroy_io_queue(ena_dev, ena_qid); 1121 return rc; 1122 } 1123 1124 if (ring->type == ENA_RING_TYPE_TX) 1125 ena_com_update_numa_node(ring->ena_com_io_cq, ctx.numa_node); 1126 1127 return 0; 1128 } 1129 1130 static void ena_queue_stop(struct ena_ring *ring) 1131 { 1132 struct ena_com_dev *ena_dev = &ring->adapter->ena_dev; 1133 1134 if (ring->type == ENA_RING_TYPE_RX) { 1135 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(ring->id)); 1136 ena_rx_queue_release_bufs(ring); 1137 } else { 1138 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(ring->id)); 1139 ena_tx_queue_release_bufs(ring); 1140 } 1141 } 1142 1143 static void ena_queue_stop_all(struct rte_eth_dev *dev, 1144 enum ena_ring_type ring_type) 1145 { 1146 struct ena_adapter *adapter = dev->data->dev_private; 1147 struct ena_ring *queues = NULL; 1148 uint16_t nb_queues, i; 1149 1150 if (ring_type == ENA_RING_TYPE_RX) { 1151 queues = adapter->rx_ring; 1152 nb_queues = dev->data->nb_rx_queues; 1153 } else { 1154 queues = adapter->tx_ring; 1155 nb_queues = dev->data->nb_tx_queues; 1156 } 1157 1158 for (i = 0; i < nb_queues; ++i) 1159 if (queues[i].configured) 1160 ena_queue_stop(&queues[i]); 1161 } 1162 1163 static int ena_queue_start(struct ena_ring *ring) 1164 { 1165 int rc, bufs_num; 1166 1167 ena_assert_msg(ring->configured == 1, 1168 "Trying to start unconfigured queue\n"); 1169 1170 rc = ena_create_io_queue(ring); 1171 if (rc) { 1172 PMD_INIT_LOG(ERR, "Failed to create IO queue!"); 1173 return rc; 1174 } 1175 1176 ring->next_to_clean = 0; 1177 ring->next_to_use = 0; 1178 1179 if (ring->type == ENA_RING_TYPE_TX) { 1180 ring->tx_stats.available_desc = 1181 ena_com_free_desc(ring->ena_com_io_sq); 1182 return 0; 1183 } 1184 1185 bufs_num = ring->ring_size - 1; 1186 rc = ena_populate_rx_queue(ring, bufs_num); 1187 if (rc != bufs_num) { 1188 ena_com_destroy_io_queue(&ring->adapter->ena_dev, 1189 ENA_IO_RXQ_IDX(ring->id)); 1190 PMD_INIT_LOG(ERR, "Failed to populate rx ring !"); 1191 return ENA_COM_FAULT; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int ena_tx_queue_setup(struct rte_eth_dev *dev, 1198 uint16_t queue_idx, 1199 uint16_t nb_desc, 1200 unsigned int socket_id, 1201 const struct rte_eth_txconf *tx_conf) 1202 { 1203 struct ena_ring *txq = NULL; 1204 struct ena_adapter *adapter = dev->data->dev_private; 1205 unsigned int i; 1206 1207 txq = &adapter->tx_ring[queue_idx]; 1208 1209 if (txq->configured) { 1210 RTE_LOG(CRIT, PMD, 1211 "API violation. Queue %d is already configured\n", 1212 queue_idx); 1213 return ENA_COM_FAULT; 1214 } 1215 1216 if (!rte_is_power_of_2(nb_desc)) { 1217 RTE_LOG(ERR, PMD, 1218 "Unsupported size of TX queue: %d is not a power of 2.\n", 1219 nb_desc); 1220 return -EINVAL; 1221 } 1222 1223 if (nb_desc > adapter->tx_ring_size) { 1224 RTE_LOG(ERR, PMD, 1225 "Unsupported size of TX queue (max size: %d)\n", 1226 adapter->tx_ring_size); 1227 return -EINVAL; 1228 } 1229 1230 if (nb_desc == RTE_ETH_DEV_FALLBACK_TX_RINGSIZE) 1231 nb_desc = adapter->tx_ring_size; 1232 1233 txq->port_id = dev->data->port_id; 1234 txq->next_to_clean = 0; 1235 txq->next_to_use = 0; 1236 txq->ring_size = nb_desc; 1237 txq->numa_socket_id = socket_id; 1238 1239 txq->tx_buffer_info = rte_zmalloc("txq->tx_buffer_info", 1240 sizeof(struct ena_tx_buffer) * 1241 txq->ring_size, 1242 RTE_CACHE_LINE_SIZE); 1243 if (!txq->tx_buffer_info) { 1244 RTE_LOG(ERR, PMD, "failed to alloc mem for tx buffer info\n"); 1245 return -ENOMEM; 1246 } 1247 1248 txq->empty_tx_reqs = rte_zmalloc("txq->empty_tx_reqs", 1249 sizeof(u16) * txq->ring_size, 1250 RTE_CACHE_LINE_SIZE); 1251 if (!txq->empty_tx_reqs) { 1252 RTE_LOG(ERR, PMD, "failed to alloc mem for tx reqs\n"); 1253 rte_free(txq->tx_buffer_info); 1254 return -ENOMEM; 1255 } 1256 1257 txq->push_buf_intermediate_buf = 1258 rte_zmalloc("txq->push_buf_intermediate_buf", 1259 txq->tx_max_header_size, 1260 RTE_CACHE_LINE_SIZE); 1261 if (!txq->push_buf_intermediate_buf) { 1262 RTE_LOG(ERR, PMD, "failed to alloc push buff for LLQ\n"); 1263 rte_free(txq->tx_buffer_info); 1264 rte_free(txq->empty_tx_reqs); 1265 return -ENOMEM; 1266 } 1267 1268 for (i = 0; i < txq->ring_size; i++) 1269 txq->empty_tx_reqs[i] = i; 1270 1271 if (tx_conf != NULL) { 1272 txq->offloads = 1273 tx_conf->offloads | dev->data->dev_conf.txmode.offloads; 1274 } 1275 /* Store pointer to this queue in upper layer */ 1276 txq->configured = 1; 1277 dev->data->tx_queues[queue_idx] = txq; 1278 1279 return 0; 1280 } 1281 1282 static int ena_rx_queue_setup(struct rte_eth_dev *dev, 1283 uint16_t queue_idx, 1284 uint16_t nb_desc, 1285 unsigned int socket_id, 1286 __rte_unused const struct rte_eth_rxconf *rx_conf, 1287 struct rte_mempool *mp) 1288 { 1289 struct ena_adapter *adapter = dev->data->dev_private; 1290 struct ena_ring *rxq = NULL; 1291 int i; 1292 1293 rxq = &adapter->rx_ring[queue_idx]; 1294 if (rxq->configured) { 1295 RTE_LOG(CRIT, PMD, 1296 "API violation. Queue %d is already configured\n", 1297 queue_idx); 1298 return ENA_COM_FAULT; 1299 } 1300 1301 if (nb_desc == RTE_ETH_DEV_FALLBACK_RX_RINGSIZE) 1302 nb_desc = adapter->rx_ring_size; 1303 1304 if (!rte_is_power_of_2(nb_desc)) { 1305 RTE_LOG(ERR, PMD, 1306 "Unsupported size of RX queue: %d is not a power of 2.\n", 1307 nb_desc); 1308 return -EINVAL; 1309 } 1310 1311 if (nb_desc > adapter->rx_ring_size) { 1312 RTE_LOG(ERR, PMD, 1313 "Unsupported size of RX queue (max size: %d)\n", 1314 adapter->rx_ring_size); 1315 return -EINVAL; 1316 } 1317 1318 rxq->port_id = dev->data->port_id; 1319 rxq->next_to_clean = 0; 1320 rxq->next_to_use = 0; 1321 rxq->ring_size = nb_desc; 1322 rxq->numa_socket_id = socket_id; 1323 rxq->mb_pool = mp; 1324 1325 rxq->rx_buffer_info = rte_zmalloc("rxq->buffer_info", 1326 sizeof(struct rte_mbuf *) * nb_desc, 1327 RTE_CACHE_LINE_SIZE); 1328 if (!rxq->rx_buffer_info) { 1329 RTE_LOG(ERR, PMD, "failed to alloc mem for rx buffer info\n"); 1330 return -ENOMEM; 1331 } 1332 1333 rxq->rx_refill_buffer = rte_zmalloc("rxq->rx_refill_buffer", 1334 sizeof(struct rte_mbuf *) * nb_desc, 1335 RTE_CACHE_LINE_SIZE); 1336 1337 if (!rxq->rx_refill_buffer) { 1338 RTE_LOG(ERR, PMD, "failed to alloc mem for rx refill buffer\n"); 1339 rte_free(rxq->rx_buffer_info); 1340 rxq->rx_buffer_info = NULL; 1341 return -ENOMEM; 1342 } 1343 1344 rxq->empty_rx_reqs = rte_zmalloc("rxq->empty_rx_reqs", 1345 sizeof(uint16_t) * nb_desc, 1346 RTE_CACHE_LINE_SIZE); 1347 if (!rxq->empty_rx_reqs) { 1348 RTE_LOG(ERR, PMD, "failed to alloc mem for empty rx reqs\n"); 1349 rte_free(rxq->rx_buffer_info); 1350 rxq->rx_buffer_info = NULL; 1351 rte_free(rxq->rx_refill_buffer); 1352 rxq->rx_refill_buffer = NULL; 1353 return -ENOMEM; 1354 } 1355 1356 for (i = 0; i < nb_desc; i++) 1357 rxq->empty_rx_reqs[i] = i; 1358 1359 /* Store pointer to this queue in upper layer */ 1360 rxq->configured = 1; 1361 dev->data->rx_queues[queue_idx] = rxq; 1362 1363 return 0; 1364 } 1365 1366 static int ena_populate_rx_queue(struct ena_ring *rxq, unsigned int count) 1367 { 1368 unsigned int i; 1369 int rc; 1370 uint16_t ring_size = rxq->ring_size; 1371 uint16_t ring_mask = ring_size - 1; 1372 uint16_t next_to_use = rxq->next_to_use; 1373 uint16_t in_use, req_id; 1374 struct rte_mbuf **mbufs = rxq->rx_refill_buffer; 1375 1376 if (unlikely(!count)) 1377 return 0; 1378 1379 in_use = rxq->next_to_use - rxq->next_to_clean; 1380 ena_assert_msg(((in_use + count) < ring_size), "bad ring state\n"); 1381 1382 /* get resources for incoming packets */ 1383 rc = rte_mempool_get_bulk(rxq->mb_pool, (void **)mbufs, count); 1384 if (unlikely(rc < 0)) { 1385 rte_atomic64_inc(&rxq->adapter->drv_stats->rx_nombuf); 1386 ++rxq->rx_stats.mbuf_alloc_fail; 1387 PMD_RX_LOG(DEBUG, "there are no enough free buffers"); 1388 return 0; 1389 } 1390 1391 for (i = 0; i < count; i++) { 1392 uint16_t next_to_use_masked = next_to_use & ring_mask; 1393 struct rte_mbuf *mbuf = mbufs[i]; 1394 struct ena_com_buf ebuf; 1395 1396 if (likely((i + 4) < count)) 1397 rte_prefetch0(mbufs[i + 4]); 1398 1399 req_id = rxq->empty_rx_reqs[next_to_use_masked]; 1400 rc = validate_rx_req_id(rxq, req_id); 1401 if (unlikely(rc < 0)) 1402 break; 1403 rxq->rx_buffer_info[req_id] = mbuf; 1404 1405 /* prepare physical address for DMA transaction */ 1406 ebuf.paddr = mbuf->buf_iova + RTE_PKTMBUF_HEADROOM; 1407 ebuf.len = mbuf->buf_len - RTE_PKTMBUF_HEADROOM; 1408 /* pass resource to device */ 1409 rc = ena_com_add_single_rx_desc(rxq->ena_com_io_sq, 1410 &ebuf, req_id); 1411 if (unlikely(rc)) { 1412 RTE_LOG(WARNING, PMD, "failed adding rx desc\n"); 1413 rxq->rx_buffer_info[req_id] = NULL; 1414 break; 1415 } 1416 next_to_use++; 1417 } 1418 1419 if (unlikely(i < count)) { 1420 RTE_LOG(WARNING, PMD, "refilled rx qid %d with only %d " 1421 "buffers (from %d)\n", rxq->id, i, count); 1422 rte_mempool_put_bulk(rxq->mb_pool, (void **)(&mbufs[i]), 1423 count - i); 1424 ++rxq->rx_stats.refill_partial; 1425 } 1426 1427 /* When we submitted free recources to device... */ 1428 if (likely(i > 0)) { 1429 /* ...let HW know that it can fill buffers with data 1430 * 1431 * Add memory barrier to make sure the desc were written before 1432 * issue a doorbell 1433 */ 1434 rte_wmb(); 1435 ena_com_write_sq_doorbell(rxq->ena_com_io_sq); 1436 1437 rxq->next_to_use = next_to_use; 1438 } 1439 1440 return i; 1441 } 1442 1443 static int ena_device_init(struct ena_com_dev *ena_dev, 1444 struct ena_com_dev_get_features_ctx *get_feat_ctx, 1445 bool *wd_state) 1446 { 1447 uint32_t aenq_groups; 1448 int rc; 1449 bool readless_supported; 1450 1451 /* Initialize mmio registers */ 1452 rc = ena_com_mmio_reg_read_request_init(ena_dev); 1453 if (rc) { 1454 RTE_LOG(ERR, PMD, "failed to init mmio read less\n"); 1455 return rc; 1456 } 1457 1458 /* The PCIe configuration space revision id indicate if mmio reg 1459 * read is disabled. 1460 */ 1461 readless_supported = 1462 !(((struct rte_pci_device *)ena_dev->dmadev)->id.class_id 1463 & ENA_MMIO_DISABLE_REG_READ); 1464 ena_com_set_mmio_read_mode(ena_dev, readless_supported); 1465 1466 /* reset device */ 1467 rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL); 1468 if (rc) { 1469 RTE_LOG(ERR, PMD, "cannot reset device\n"); 1470 goto err_mmio_read_less; 1471 } 1472 1473 /* check FW version */ 1474 rc = ena_com_validate_version(ena_dev); 1475 if (rc) { 1476 RTE_LOG(ERR, PMD, "device version is too low\n"); 1477 goto err_mmio_read_less; 1478 } 1479 1480 ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev); 1481 1482 /* ENA device administration layer init */ 1483 rc = ena_com_admin_init(ena_dev, &aenq_handlers); 1484 if (rc) { 1485 RTE_LOG(ERR, PMD, 1486 "cannot initialize ena admin queue with device\n"); 1487 goto err_mmio_read_less; 1488 } 1489 1490 /* To enable the msix interrupts the driver needs to know the number 1491 * of queues. So the driver uses polling mode to retrieve this 1492 * information. 1493 */ 1494 ena_com_set_admin_polling_mode(ena_dev, true); 1495 1496 ena_config_host_info(ena_dev); 1497 1498 /* Get Device Attributes and features */ 1499 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx); 1500 if (rc) { 1501 RTE_LOG(ERR, PMD, 1502 "cannot get attribute for ena device rc= %d\n", rc); 1503 goto err_admin_init; 1504 } 1505 1506 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) | 1507 BIT(ENA_ADMIN_NOTIFICATION) | 1508 BIT(ENA_ADMIN_KEEP_ALIVE) | 1509 BIT(ENA_ADMIN_FATAL_ERROR) | 1510 BIT(ENA_ADMIN_WARNING); 1511 1512 aenq_groups &= get_feat_ctx->aenq.supported_groups; 1513 rc = ena_com_set_aenq_config(ena_dev, aenq_groups); 1514 if (rc) { 1515 RTE_LOG(ERR, PMD, "Cannot configure aenq groups rc: %d\n", rc); 1516 goto err_admin_init; 1517 } 1518 1519 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE)); 1520 1521 return 0; 1522 1523 err_admin_init: 1524 ena_com_admin_destroy(ena_dev); 1525 1526 err_mmio_read_less: 1527 ena_com_mmio_reg_read_request_destroy(ena_dev); 1528 1529 return rc; 1530 } 1531 1532 static void ena_interrupt_handler_rte(void *cb_arg) 1533 { 1534 struct ena_adapter *adapter = cb_arg; 1535 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1536 1537 ena_com_admin_q_comp_intr_handler(ena_dev); 1538 if (likely(adapter->state != ENA_ADAPTER_STATE_CLOSED)) 1539 ena_com_aenq_intr_handler(ena_dev, adapter); 1540 } 1541 1542 static void check_for_missing_keep_alive(struct ena_adapter *adapter) 1543 { 1544 if (!adapter->wd_state) 1545 return; 1546 1547 if (adapter->keep_alive_timeout == ENA_HW_HINTS_NO_TIMEOUT) 1548 return; 1549 1550 if (unlikely((rte_get_timer_cycles() - adapter->timestamp_wd) >= 1551 adapter->keep_alive_timeout)) { 1552 RTE_LOG(ERR, PMD, "Keep alive timeout\n"); 1553 adapter->reset_reason = ENA_REGS_RESET_KEEP_ALIVE_TO; 1554 adapter->trigger_reset = true; 1555 ++adapter->dev_stats.wd_expired; 1556 } 1557 } 1558 1559 /* Check if admin queue is enabled */ 1560 static void check_for_admin_com_state(struct ena_adapter *adapter) 1561 { 1562 if (unlikely(!ena_com_get_admin_running_state(&adapter->ena_dev))) { 1563 RTE_LOG(ERR, PMD, "ENA admin queue is not in running state!\n"); 1564 adapter->reset_reason = ENA_REGS_RESET_ADMIN_TO; 1565 adapter->trigger_reset = true; 1566 } 1567 } 1568 1569 static void ena_timer_wd_callback(__rte_unused struct rte_timer *timer, 1570 void *arg) 1571 { 1572 struct ena_adapter *adapter = arg; 1573 struct rte_eth_dev *dev = adapter->rte_dev; 1574 1575 check_for_missing_keep_alive(adapter); 1576 check_for_admin_com_state(adapter); 1577 1578 if (unlikely(adapter->trigger_reset)) { 1579 RTE_LOG(ERR, PMD, "Trigger reset is on\n"); 1580 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, 1581 NULL); 1582 } 1583 } 1584 1585 static inline void 1586 set_default_llq_configurations(struct ena_llq_configurations *llq_config) 1587 { 1588 llq_config->llq_header_location = ENA_ADMIN_INLINE_HEADER; 1589 llq_config->llq_ring_entry_size = ENA_ADMIN_LIST_ENTRY_SIZE_128B; 1590 llq_config->llq_stride_ctrl = ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY; 1591 llq_config->llq_num_decs_before_header = 1592 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2; 1593 llq_config->llq_ring_entry_size_value = 128; 1594 } 1595 1596 static int 1597 ena_set_queues_placement_policy(struct ena_adapter *adapter, 1598 struct ena_com_dev *ena_dev, 1599 struct ena_admin_feature_llq_desc *llq, 1600 struct ena_llq_configurations *llq_default_configurations) 1601 { 1602 int rc; 1603 u32 llq_feature_mask; 1604 1605 llq_feature_mask = 1 << ENA_ADMIN_LLQ; 1606 if (!(ena_dev->supported_features & llq_feature_mask)) { 1607 RTE_LOG(INFO, PMD, 1608 "LLQ is not supported. Fallback to host mode policy.\n"); 1609 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1610 return 0; 1611 } 1612 1613 rc = ena_com_config_dev_mode(ena_dev, llq, llq_default_configurations); 1614 if (unlikely(rc)) { 1615 PMD_INIT_LOG(WARNING, "Failed to config dev mode. " 1616 "Fallback to host mode policy."); 1617 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1618 return 0; 1619 } 1620 1621 /* Nothing to config, exit */ 1622 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1623 return 0; 1624 1625 if (!adapter->dev_mem_base) { 1626 RTE_LOG(ERR, PMD, "Unable to access LLQ bar resource. " 1627 "Fallback to host mode policy.\n."); 1628 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST; 1629 return 0; 1630 } 1631 1632 ena_dev->mem_bar = adapter->dev_mem_base; 1633 1634 return 0; 1635 } 1636 1637 static int ena_calc_io_queue_num(struct ena_com_dev *ena_dev, 1638 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1639 { 1640 uint32_t io_tx_sq_num, io_tx_cq_num, io_rx_num, io_queue_num; 1641 1642 /* Regular queues capabilities */ 1643 if (ena_dev->supported_features & BIT(ENA_ADMIN_MAX_QUEUES_EXT)) { 1644 struct ena_admin_queue_ext_feature_fields *max_queue_ext = 1645 &get_feat_ctx->max_queue_ext.max_queue_ext; 1646 io_rx_num = RTE_MIN(max_queue_ext->max_rx_sq_num, 1647 max_queue_ext->max_rx_cq_num); 1648 io_tx_sq_num = max_queue_ext->max_tx_sq_num; 1649 io_tx_cq_num = max_queue_ext->max_tx_cq_num; 1650 } else { 1651 struct ena_admin_queue_feature_desc *max_queues = 1652 &get_feat_ctx->max_queues; 1653 io_tx_sq_num = max_queues->max_sq_num; 1654 io_tx_cq_num = max_queues->max_cq_num; 1655 io_rx_num = RTE_MIN(io_tx_sq_num, io_tx_cq_num); 1656 } 1657 1658 /* In case of LLQ use the llq number in the get feature cmd */ 1659 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) 1660 io_tx_sq_num = get_feat_ctx->llq.max_llq_num; 1661 1662 io_queue_num = RTE_MIN(ENA_MAX_NUM_IO_QUEUES, io_rx_num); 1663 io_queue_num = RTE_MIN(io_queue_num, io_tx_sq_num); 1664 io_queue_num = RTE_MIN(io_queue_num, io_tx_cq_num); 1665 1666 if (unlikely(io_queue_num == 0)) { 1667 RTE_LOG(ERR, PMD, "Number of IO queues should not be 0\n"); 1668 return -EFAULT; 1669 } 1670 1671 return io_queue_num; 1672 } 1673 1674 static int eth_ena_dev_init(struct rte_eth_dev *eth_dev) 1675 { 1676 struct ena_calc_queue_size_ctx calc_queue_ctx = { 0 }; 1677 struct rte_pci_device *pci_dev; 1678 struct rte_intr_handle *intr_handle; 1679 struct ena_adapter *adapter = eth_dev->data->dev_private; 1680 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1681 struct ena_com_dev_get_features_ctx get_feat_ctx; 1682 struct ena_llq_configurations llq_config; 1683 const char *queue_type_str; 1684 int rc; 1685 1686 static int adapters_found; 1687 bool wd_state; 1688 1689 eth_dev->dev_ops = &ena_dev_ops; 1690 eth_dev->rx_pkt_burst = ð_ena_recv_pkts; 1691 eth_dev->tx_pkt_burst = ð_ena_xmit_pkts; 1692 eth_dev->tx_pkt_prepare = ð_ena_prep_pkts; 1693 1694 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1695 return 0; 1696 1697 memset(adapter, 0, sizeof(struct ena_adapter)); 1698 ena_dev = &adapter->ena_dev; 1699 1700 adapter->rte_eth_dev_data = eth_dev->data; 1701 adapter->rte_dev = eth_dev; 1702 1703 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1704 adapter->pdev = pci_dev; 1705 1706 PMD_INIT_LOG(INFO, "Initializing %x:%x:%x.%d", 1707 pci_dev->addr.domain, 1708 pci_dev->addr.bus, 1709 pci_dev->addr.devid, 1710 pci_dev->addr.function); 1711 1712 intr_handle = &pci_dev->intr_handle; 1713 1714 adapter->regs = pci_dev->mem_resource[ENA_REGS_BAR].addr; 1715 adapter->dev_mem_base = pci_dev->mem_resource[ENA_MEM_BAR].addr; 1716 1717 if (!adapter->regs) { 1718 PMD_INIT_LOG(CRIT, "Failed to access registers BAR(%d)", 1719 ENA_REGS_BAR); 1720 return -ENXIO; 1721 } 1722 1723 ena_dev->reg_bar = adapter->regs; 1724 ena_dev->dmadev = adapter->pdev; 1725 1726 adapter->id_number = adapters_found; 1727 1728 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", 1729 adapter->id_number); 1730 1731 /* device specific initialization routine */ 1732 rc = ena_device_init(ena_dev, &get_feat_ctx, &wd_state); 1733 if (rc) { 1734 PMD_INIT_LOG(CRIT, "Failed to init ENA device"); 1735 goto err; 1736 } 1737 adapter->wd_state = wd_state; 1738 1739 set_default_llq_configurations(&llq_config); 1740 rc = ena_set_queues_placement_policy(adapter, ena_dev, 1741 &get_feat_ctx.llq, &llq_config); 1742 if (unlikely(rc)) { 1743 PMD_INIT_LOG(CRIT, "Failed to set placement policy"); 1744 return rc; 1745 } 1746 1747 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 1748 queue_type_str = "Regular"; 1749 else 1750 queue_type_str = "Low latency"; 1751 RTE_LOG(INFO, PMD, "Placement policy: %s\n", queue_type_str); 1752 1753 calc_queue_ctx.ena_dev = ena_dev; 1754 calc_queue_ctx.get_feat_ctx = &get_feat_ctx; 1755 adapter->num_queues = ena_calc_io_queue_num(ena_dev, 1756 &get_feat_ctx); 1757 1758 rc = ena_calc_queue_size(&calc_queue_ctx); 1759 if (unlikely((rc != 0) || (adapter->num_queues <= 0))) { 1760 rc = -EFAULT; 1761 goto err_device_destroy; 1762 } 1763 1764 adapter->tx_ring_size = calc_queue_ctx.tx_queue_size; 1765 adapter->rx_ring_size = calc_queue_ctx.rx_queue_size; 1766 1767 adapter->max_tx_sgl_size = calc_queue_ctx.max_tx_sgl_size; 1768 adapter->max_rx_sgl_size = calc_queue_ctx.max_rx_sgl_size; 1769 1770 /* prepare ring structures */ 1771 ena_init_rings(adapter); 1772 1773 ena_config_debug_area(adapter); 1774 1775 /* Set max MTU for this device */ 1776 adapter->max_mtu = get_feat_ctx.dev_attr.max_mtu; 1777 1778 /* set device support for offloads */ 1779 adapter->offloads.tso4_supported = (get_feat_ctx.offload.tx & 1780 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) != 0; 1781 adapter->offloads.tx_csum_supported = (get_feat_ctx.offload.tx & 1782 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) != 0; 1783 adapter->offloads.rx_csum_supported = 1784 (get_feat_ctx.offload.rx_supported & 1785 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) != 0; 1786 1787 /* Copy MAC address and point DPDK to it */ 1788 eth_dev->data->mac_addrs = (struct rte_ether_addr *)adapter->mac_addr; 1789 rte_ether_addr_copy((struct rte_ether_addr *) 1790 get_feat_ctx.dev_attr.mac_addr, 1791 (struct rte_ether_addr *)adapter->mac_addr); 1792 1793 /* 1794 * Pass the information to the rte_eth_dev_close() that it should also 1795 * release the private port resources. 1796 */ 1797 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1798 1799 adapter->drv_stats = rte_zmalloc("adapter stats", 1800 sizeof(*adapter->drv_stats), 1801 RTE_CACHE_LINE_SIZE); 1802 if (!adapter->drv_stats) { 1803 RTE_LOG(ERR, PMD, "failed to alloc mem for adapter stats\n"); 1804 rc = -ENOMEM; 1805 goto err_delete_debug_area; 1806 } 1807 1808 rte_intr_callback_register(intr_handle, 1809 ena_interrupt_handler_rte, 1810 adapter); 1811 rte_intr_enable(intr_handle); 1812 ena_com_set_admin_polling_mode(ena_dev, false); 1813 ena_com_admin_aenq_enable(ena_dev); 1814 1815 if (adapters_found == 0) 1816 rte_timer_subsystem_init(); 1817 rte_timer_init(&adapter->timer_wd); 1818 1819 adapters_found++; 1820 adapter->state = ENA_ADAPTER_STATE_INIT; 1821 1822 return 0; 1823 1824 err_delete_debug_area: 1825 ena_com_delete_debug_area(ena_dev); 1826 1827 err_device_destroy: 1828 ena_com_delete_host_info(ena_dev); 1829 ena_com_admin_destroy(ena_dev); 1830 1831 err: 1832 return rc; 1833 } 1834 1835 static void ena_destroy_device(struct rte_eth_dev *eth_dev) 1836 { 1837 struct ena_adapter *adapter = eth_dev->data->dev_private; 1838 struct ena_com_dev *ena_dev = &adapter->ena_dev; 1839 1840 if (adapter->state == ENA_ADAPTER_STATE_FREE) 1841 return; 1842 1843 ena_com_set_admin_running_state(ena_dev, false); 1844 1845 if (adapter->state != ENA_ADAPTER_STATE_CLOSED) 1846 ena_close(eth_dev); 1847 1848 ena_com_delete_debug_area(ena_dev); 1849 ena_com_delete_host_info(ena_dev); 1850 1851 ena_com_abort_admin_commands(ena_dev); 1852 ena_com_wait_for_abort_completion(ena_dev); 1853 ena_com_admin_destroy(ena_dev); 1854 ena_com_mmio_reg_read_request_destroy(ena_dev); 1855 1856 adapter->state = ENA_ADAPTER_STATE_FREE; 1857 } 1858 1859 static int eth_ena_dev_uninit(struct rte_eth_dev *eth_dev) 1860 { 1861 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1862 return 0; 1863 1864 ena_destroy_device(eth_dev); 1865 1866 eth_dev->dev_ops = NULL; 1867 eth_dev->rx_pkt_burst = NULL; 1868 eth_dev->tx_pkt_burst = NULL; 1869 eth_dev->tx_pkt_prepare = NULL; 1870 1871 return 0; 1872 } 1873 1874 static int ena_dev_configure(struct rte_eth_dev *dev) 1875 { 1876 struct ena_adapter *adapter = dev->data->dev_private; 1877 1878 adapter->state = ENA_ADAPTER_STATE_CONFIG; 1879 1880 adapter->tx_selected_offloads = dev->data->dev_conf.txmode.offloads; 1881 adapter->rx_selected_offloads = dev->data->dev_conf.rxmode.offloads; 1882 return 0; 1883 } 1884 1885 static void ena_init_rings(struct ena_adapter *adapter) 1886 { 1887 int i; 1888 1889 for (i = 0; i < adapter->num_queues; i++) { 1890 struct ena_ring *ring = &adapter->tx_ring[i]; 1891 1892 ring->configured = 0; 1893 ring->type = ENA_RING_TYPE_TX; 1894 ring->adapter = adapter; 1895 ring->id = i; 1896 ring->tx_mem_queue_type = adapter->ena_dev.tx_mem_queue_type; 1897 ring->tx_max_header_size = adapter->ena_dev.tx_max_header_size; 1898 ring->sgl_size = adapter->max_tx_sgl_size; 1899 } 1900 1901 for (i = 0; i < adapter->num_queues; i++) { 1902 struct ena_ring *ring = &adapter->rx_ring[i]; 1903 1904 ring->configured = 0; 1905 ring->type = ENA_RING_TYPE_RX; 1906 ring->adapter = adapter; 1907 ring->id = i; 1908 ring->sgl_size = adapter->max_rx_sgl_size; 1909 } 1910 } 1911 1912 static int ena_infos_get(struct rte_eth_dev *dev, 1913 struct rte_eth_dev_info *dev_info) 1914 { 1915 struct ena_adapter *adapter; 1916 struct ena_com_dev *ena_dev; 1917 uint64_t rx_feat = 0, tx_feat = 0; 1918 1919 ena_assert_msg(dev->data != NULL, "Uninitialized device\n"); 1920 ena_assert_msg(dev->data->dev_private != NULL, "Uninitialized device\n"); 1921 adapter = dev->data->dev_private; 1922 1923 ena_dev = &adapter->ena_dev; 1924 ena_assert_msg(ena_dev != NULL, "Uninitialized device\n"); 1925 1926 dev_info->speed_capa = 1927 ETH_LINK_SPEED_1G | 1928 ETH_LINK_SPEED_2_5G | 1929 ETH_LINK_SPEED_5G | 1930 ETH_LINK_SPEED_10G | 1931 ETH_LINK_SPEED_25G | 1932 ETH_LINK_SPEED_40G | 1933 ETH_LINK_SPEED_50G | 1934 ETH_LINK_SPEED_100G; 1935 1936 /* Set Tx & Rx features available for device */ 1937 if (adapter->offloads.tso4_supported) 1938 tx_feat |= DEV_TX_OFFLOAD_TCP_TSO; 1939 1940 if (adapter->offloads.tx_csum_supported) 1941 tx_feat |= DEV_TX_OFFLOAD_IPV4_CKSUM | 1942 DEV_TX_OFFLOAD_UDP_CKSUM | 1943 DEV_TX_OFFLOAD_TCP_CKSUM; 1944 1945 if (adapter->offloads.rx_csum_supported) 1946 rx_feat |= DEV_RX_OFFLOAD_IPV4_CKSUM | 1947 DEV_RX_OFFLOAD_UDP_CKSUM | 1948 DEV_RX_OFFLOAD_TCP_CKSUM; 1949 1950 rx_feat |= DEV_RX_OFFLOAD_JUMBO_FRAME; 1951 1952 /* Inform framework about available features */ 1953 dev_info->rx_offload_capa = rx_feat; 1954 dev_info->rx_queue_offload_capa = rx_feat; 1955 dev_info->tx_offload_capa = tx_feat; 1956 dev_info->tx_queue_offload_capa = tx_feat; 1957 1958 dev_info->flow_type_rss_offloads = ETH_RSS_IP | ETH_RSS_TCP | 1959 ETH_RSS_UDP; 1960 1961 dev_info->min_rx_bufsize = ENA_MIN_FRAME_LEN; 1962 dev_info->max_rx_pktlen = adapter->max_mtu; 1963 dev_info->max_mac_addrs = 1; 1964 1965 dev_info->max_rx_queues = adapter->num_queues; 1966 dev_info->max_tx_queues = adapter->num_queues; 1967 dev_info->reta_size = ENA_RX_RSS_TABLE_SIZE; 1968 1969 adapter->tx_supported_offloads = tx_feat; 1970 adapter->rx_supported_offloads = rx_feat; 1971 1972 dev_info->rx_desc_lim.nb_max = adapter->rx_ring_size; 1973 dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1974 dev_info->rx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1975 adapter->max_rx_sgl_size); 1976 dev_info->rx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1977 adapter->max_rx_sgl_size); 1978 1979 dev_info->tx_desc_lim.nb_max = adapter->tx_ring_size; 1980 dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; 1981 dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1982 adapter->max_tx_sgl_size); 1983 dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, 1984 adapter->max_tx_sgl_size); 1985 1986 return 0; 1987 } 1988 1989 static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 1990 uint16_t nb_pkts) 1991 { 1992 struct ena_ring *rx_ring = (struct ena_ring *)(rx_queue); 1993 unsigned int ring_size = rx_ring->ring_size; 1994 unsigned int ring_mask = ring_size - 1; 1995 uint16_t next_to_clean = rx_ring->next_to_clean; 1996 uint16_t desc_in_use = 0; 1997 uint16_t req_id; 1998 unsigned int recv_idx = 0; 1999 struct rte_mbuf *mbuf = NULL; 2000 struct rte_mbuf *mbuf_head = NULL; 2001 struct rte_mbuf *mbuf_prev = NULL; 2002 struct rte_mbuf **rx_buff_info = rx_ring->rx_buffer_info; 2003 unsigned int completed; 2004 2005 struct ena_com_rx_ctx ena_rx_ctx; 2006 int rc = 0; 2007 2008 /* Check adapter state */ 2009 if (unlikely(rx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2010 RTE_LOG(ALERT, PMD, 2011 "Trying to receive pkts while device is NOT running\n"); 2012 return 0; 2013 } 2014 2015 desc_in_use = rx_ring->next_to_use - next_to_clean; 2016 if (unlikely(nb_pkts > desc_in_use)) 2017 nb_pkts = desc_in_use; 2018 2019 for (completed = 0; completed < nb_pkts; completed++) { 2020 int segments = 0; 2021 2022 ena_rx_ctx.max_bufs = rx_ring->sgl_size; 2023 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs; 2024 ena_rx_ctx.descs = 0; 2025 /* receive packet context */ 2026 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq, 2027 rx_ring->ena_com_io_sq, 2028 &ena_rx_ctx); 2029 if (unlikely(rc)) { 2030 RTE_LOG(ERR, PMD, "ena_com_rx_pkt error %d\n", rc); 2031 rx_ring->adapter->reset_reason = 2032 ENA_REGS_RESET_TOO_MANY_RX_DESCS; 2033 rx_ring->adapter->trigger_reset = true; 2034 ++rx_ring->rx_stats.bad_desc_num; 2035 return 0; 2036 } 2037 2038 if (unlikely(ena_rx_ctx.descs == 0)) 2039 break; 2040 2041 while (segments < ena_rx_ctx.descs) { 2042 req_id = ena_rx_ctx.ena_bufs[segments].req_id; 2043 rc = validate_rx_req_id(rx_ring, req_id); 2044 if (unlikely(rc)) { 2045 if (segments != 0) 2046 rte_mbuf_raw_free(mbuf_head); 2047 break; 2048 } 2049 2050 mbuf = rx_buff_info[req_id]; 2051 rx_buff_info[req_id] = NULL; 2052 mbuf->data_len = ena_rx_ctx.ena_bufs[segments].len; 2053 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 2054 mbuf->refcnt = 1; 2055 mbuf->next = NULL; 2056 if (unlikely(segments == 0)) { 2057 mbuf->nb_segs = ena_rx_ctx.descs; 2058 mbuf->port = rx_ring->port_id; 2059 mbuf->pkt_len = 0; 2060 mbuf_head = mbuf; 2061 } else { 2062 /* for multi-segment pkts create mbuf chain */ 2063 mbuf_prev->next = mbuf; 2064 } 2065 mbuf_head->pkt_len += mbuf->data_len; 2066 2067 mbuf_prev = mbuf; 2068 rx_ring->empty_rx_reqs[next_to_clean & ring_mask] = 2069 req_id; 2070 segments++; 2071 next_to_clean++; 2072 } 2073 if (unlikely(rc)) 2074 break; 2075 2076 /* fill mbuf attributes if any */ 2077 ena_rx_mbuf_prepare(mbuf_head, &ena_rx_ctx); 2078 2079 if (unlikely(mbuf_head->ol_flags & 2080 (PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD))) { 2081 rte_atomic64_inc(&rx_ring->adapter->drv_stats->ierrors); 2082 ++rx_ring->rx_stats.bad_csum; 2083 } 2084 2085 mbuf_head->hash.rss = ena_rx_ctx.hash; 2086 2087 /* pass to DPDK application head mbuf */ 2088 rx_pkts[recv_idx] = mbuf_head; 2089 recv_idx++; 2090 rx_ring->rx_stats.bytes += mbuf_head->pkt_len; 2091 } 2092 2093 rx_ring->rx_stats.cnt += recv_idx; 2094 rx_ring->next_to_clean = next_to_clean; 2095 2096 desc_in_use = desc_in_use - completed + 1; 2097 /* Burst refill to save doorbells, memory barriers, const interval */ 2098 if (ring_size - desc_in_use > ENA_RING_DESCS_RATIO(ring_size)) { 2099 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq); 2100 ena_populate_rx_queue(rx_ring, ring_size - desc_in_use); 2101 } 2102 2103 return recv_idx; 2104 } 2105 2106 static uint16_t 2107 eth_ena_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2108 uint16_t nb_pkts) 2109 { 2110 int32_t ret; 2111 uint32_t i; 2112 struct rte_mbuf *m; 2113 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2114 struct rte_ipv4_hdr *ip_hdr; 2115 uint64_t ol_flags; 2116 uint16_t frag_field; 2117 2118 for (i = 0; i != nb_pkts; i++) { 2119 m = tx_pkts[i]; 2120 ol_flags = m->ol_flags; 2121 2122 if (!(ol_flags & PKT_TX_IPV4)) 2123 continue; 2124 2125 /* If there was not L2 header length specified, assume it is 2126 * length of the ethernet header. 2127 */ 2128 if (unlikely(m->l2_len == 0)) 2129 m->l2_len = sizeof(struct rte_ether_hdr); 2130 2131 ip_hdr = rte_pktmbuf_mtod_offset(m, struct rte_ipv4_hdr *, 2132 m->l2_len); 2133 frag_field = rte_be_to_cpu_16(ip_hdr->fragment_offset); 2134 2135 if ((frag_field & RTE_IPV4_HDR_DF_FLAG) != 0) { 2136 m->packet_type |= RTE_PTYPE_L4_NONFRAG; 2137 2138 /* If IPv4 header has DF flag enabled and TSO support is 2139 * disabled, partial chcecksum should not be calculated. 2140 */ 2141 if (!tx_ring->adapter->offloads.tso4_supported) 2142 continue; 2143 } 2144 2145 if ((ol_flags & ENA_TX_OFFLOAD_NOTSUP_MASK) != 0 || 2146 (ol_flags & PKT_TX_L4_MASK) == 2147 PKT_TX_SCTP_CKSUM) { 2148 rte_errno = ENOTSUP; 2149 return i; 2150 } 2151 2152 #ifdef RTE_LIBRTE_ETHDEV_DEBUG 2153 ret = rte_validate_tx_offload(m); 2154 if (ret != 0) { 2155 rte_errno = -ret; 2156 return i; 2157 } 2158 #endif 2159 2160 /* In case we are supposed to TSO and have DF not set (DF=0) 2161 * hardware must be provided with partial checksum, otherwise 2162 * it will take care of necessary calculations. 2163 */ 2164 2165 ret = rte_net_intel_cksum_flags_prepare(m, 2166 ol_flags & ~PKT_TX_TCP_SEG); 2167 if (ret != 0) { 2168 rte_errno = -ret; 2169 return i; 2170 } 2171 } 2172 2173 return i; 2174 } 2175 2176 static void ena_update_hints(struct ena_adapter *adapter, 2177 struct ena_admin_ena_hw_hints *hints) 2178 { 2179 if (hints->admin_completion_tx_timeout) 2180 adapter->ena_dev.admin_queue.completion_timeout = 2181 hints->admin_completion_tx_timeout * 1000; 2182 2183 if (hints->mmio_read_timeout) 2184 /* convert to usec */ 2185 adapter->ena_dev.mmio_read.reg_read_to = 2186 hints->mmio_read_timeout * 1000; 2187 2188 if (hints->driver_watchdog_timeout) { 2189 if (hints->driver_watchdog_timeout == ENA_HW_HINTS_NO_TIMEOUT) 2190 adapter->keep_alive_timeout = ENA_HW_HINTS_NO_TIMEOUT; 2191 else 2192 // Convert msecs to ticks 2193 adapter->keep_alive_timeout = 2194 (hints->driver_watchdog_timeout * 2195 rte_get_timer_hz()) / 1000; 2196 } 2197 } 2198 2199 static int ena_check_and_linearize_mbuf(struct ena_ring *tx_ring, 2200 struct rte_mbuf *mbuf) 2201 { 2202 struct ena_com_dev *ena_dev; 2203 int num_segments, header_len, rc; 2204 2205 ena_dev = &tx_ring->adapter->ena_dev; 2206 num_segments = mbuf->nb_segs; 2207 header_len = mbuf->data_len; 2208 2209 if (likely(num_segments < tx_ring->sgl_size)) 2210 return 0; 2211 2212 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV && 2213 (num_segments == tx_ring->sgl_size) && 2214 (header_len < tx_ring->tx_max_header_size)) 2215 return 0; 2216 2217 ++tx_ring->tx_stats.linearize; 2218 rc = rte_pktmbuf_linearize(mbuf); 2219 if (unlikely(rc)) { 2220 RTE_LOG(WARNING, PMD, "Mbuf linearize failed\n"); 2221 rte_atomic64_inc(&tx_ring->adapter->drv_stats->ierrors); 2222 ++tx_ring->tx_stats.linearize_failed; 2223 return rc; 2224 } 2225 2226 return rc; 2227 } 2228 2229 static uint16_t eth_ena_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 2230 uint16_t nb_pkts) 2231 { 2232 struct ena_ring *tx_ring = (struct ena_ring *)(tx_queue); 2233 uint16_t next_to_use = tx_ring->next_to_use; 2234 uint16_t next_to_clean = tx_ring->next_to_clean; 2235 struct rte_mbuf *mbuf; 2236 uint16_t seg_len; 2237 unsigned int ring_size = tx_ring->ring_size; 2238 unsigned int ring_mask = ring_size - 1; 2239 struct ena_com_tx_ctx ena_tx_ctx; 2240 struct ena_tx_buffer *tx_info; 2241 struct ena_com_buf *ebuf; 2242 uint16_t rc, req_id, total_tx_descs = 0; 2243 uint16_t sent_idx = 0, empty_tx_reqs; 2244 uint16_t push_len = 0; 2245 uint16_t delta = 0; 2246 int nb_hw_desc; 2247 uint32_t total_length; 2248 2249 /* Check adapter state */ 2250 if (unlikely(tx_ring->adapter->state != ENA_ADAPTER_STATE_RUNNING)) { 2251 RTE_LOG(ALERT, PMD, 2252 "Trying to xmit pkts while device is NOT running\n"); 2253 return 0; 2254 } 2255 2256 empty_tx_reqs = ring_size - (next_to_use - next_to_clean); 2257 if (nb_pkts > empty_tx_reqs) 2258 nb_pkts = empty_tx_reqs; 2259 2260 for (sent_idx = 0; sent_idx < nb_pkts; sent_idx++) { 2261 mbuf = tx_pkts[sent_idx]; 2262 total_length = 0; 2263 2264 rc = ena_check_and_linearize_mbuf(tx_ring, mbuf); 2265 if (unlikely(rc)) 2266 break; 2267 2268 req_id = tx_ring->empty_tx_reqs[next_to_use & ring_mask]; 2269 tx_info = &tx_ring->tx_buffer_info[req_id]; 2270 tx_info->mbuf = mbuf; 2271 tx_info->num_of_bufs = 0; 2272 ebuf = tx_info->bufs; 2273 2274 /* Prepare TX context */ 2275 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx)); 2276 memset(&ena_tx_ctx.ena_meta, 0x0, 2277 sizeof(struct ena_com_tx_meta)); 2278 ena_tx_ctx.ena_bufs = ebuf; 2279 ena_tx_ctx.req_id = req_id; 2280 2281 delta = 0; 2282 seg_len = mbuf->data_len; 2283 2284 if (tx_ring->tx_mem_queue_type == 2285 ENA_ADMIN_PLACEMENT_POLICY_DEV) { 2286 push_len = RTE_MIN(mbuf->pkt_len, 2287 tx_ring->tx_max_header_size); 2288 ena_tx_ctx.header_len = push_len; 2289 2290 if (likely(push_len <= seg_len)) { 2291 /* If the push header is in the single segment, 2292 * then just point it to the 1st mbuf data. 2293 */ 2294 ena_tx_ctx.push_header = 2295 rte_pktmbuf_mtod(mbuf, uint8_t *); 2296 } else { 2297 /* If the push header lays in the several 2298 * segments, copy it to the intermediate buffer. 2299 */ 2300 rte_pktmbuf_read(mbuf, 0, push_len, 2301 tx_ring->push_buf_intermediate_buf); 2302 ena_tx_ctx.push_header = 2303 tx_ring->push_buf_intermediate_buf; 2304 delta = push_len - seg_len; 2305 } 2306 } /* there's no else as we take advantage of memset zeroing */ 2307 2308 /* Set TX offloads flags, if applicable */ 2309 ena_tx_mbuf_prepare(mbuf, &ena_tx_ctx, tx_ring->offloads); 2310 2311 rte_prefetch0(tx_pkts[(sent_idx + 4) & ring_mask]); 2312 2313 /* Process first segment taking into 2314 * consideration pushed header 2315 */ 2316 if (seg_len > push_len) { 2317 ebuf->paddr = mbuf->buf_iova + 2318 mbuf->data_off + 2319 push_len; 2320 ebuf->len = seg_len - push_len; 2321 ebuf++; 2322 tx_info->num_of_bufs++; 2323 } 2324 total_length += mbuf->data_len; 2325 2326 while ((mbuf = mbuf->next) != NULL) { 2327 seg_len = mbuf->data_len; 2328 2329 /* Skip mbufs if whole data is pushed as a header */ 2330 if (unlikely(delta > seg_len)) { 2331 delta -= seg_len; 2332 continue; 2333 } 2334 2335 ebuf->paddr = mbuf->buf_iova + mbuf->data_off + delta; 2336 ebuf->len = seg_len - delta; 2337 total_length += ebuf->len; 2338 ebuf++; 2339 tx_info->num_of_bufs++; 2340 2341 delta = 0; 2342 } 2343 2344 ena_tx_ctx.num_bufs = tx_info->num_of_bufs; 2345 2346 if (ena_com_is_doorbell_needed(tx_ring->ena_com_io_sq, 2347 &ena_tx_ctx)) { 2348 RTE_LOG(DEBUG, PMD, "llq tx max burst size of queue %d" 2349 " achieved, writing doorbell to send burst\n", 2350 tx_ring->id); 2351 rte_wmb(); 2352 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2353 } 2354 2355 /* prepare the packet's descriptors to dma engine */ 2356 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, 2357 &ena_tx_ctx, &nb_hw_desc); 2358 if (unlikely(rc)) { 2359 ++tx_ring->tx_stats.prepare_ctx_err; 2360 break; 2361 } 2362 tx_info->tx_descs = nb_hw_desc; 2363 2364 next_to_use++; 2365 tx_ring->tx_stats.cnt++; 2366 tx_ring->tx_stats.bytes += total_length; 2367 } 2368 tx_ring->tx_stats.available_desc = 2369 ena_com_free_desc(tx_ring->ena_com_io_sq); 2370 2371 /* If there are ready packets to be xmitted... */ 2372 if (sent_idx > 0) { 2373 /* ...let HW do its best :-) */ 2374 rte_wmb(); 2375 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq); 2376 tx_ring->tx_stats.doorbells++; 2377 tx_ring->next_to_use = next_to_use; 2378 } 2379 2380 /* Clear complete packets */ 2381 while (ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq, &req_id) >= 0) { 2382 rc = validate_tx_req_id(tx_ring, req_id); 2383 if (rc) 2384 break; 2385 2386 /* Get Tx info & store how many descs were processed */ 2387 tx_info = &tx_ring->tx_buffer_info[req_id]; 2388 total_tx_descs += tx_info->tx_descs; 2389 2390 /* Free whole mbuf chain */ 2391 mbuf = tx_info->mbuf; 2392 rte_pktmbuf_free(mbuf); 2393 tx_info->mbuf = NULL; 2394 2395 /* Put back descriptor to the ring for reuse */ 2396 tx_ring->empty_tx_reqs[next_to_clean & ring_mask] = req_id; 2397 next_to_clean++; 2398 2399 /* If too many descs to clean, leave it for another run */ 2400 if (unlikely(total_tx_descs > ENA_RING_DESCS_RATIO(ring_size))) 2401 break; 2402 } 2403 tx_ring->tx_stats.available_desc = 2404 ena_com_free_desc(tx_ring->ena_com_io_sq); 2405 2406 if (total_tx_descs > 0) { 2407 /* acknowledge completion of sent packets */ 2408 tx_ring->next_to_clean = next_to_clean; 2409 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_tx_descs); 2410 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq); 2411 } 2412 2413 tx_ring->tx_stats.tx_poll++; 2414 2415 return sent_idx; 2416 } 2417 2418 /** 2419 * DPDK callback to retrieve names of extended device statistics 2420 * 2421 * @param dev 2422 * Pointer to Ethernet device structure. 2423 * @param[out] xstats_names 2424 * Buffer to insert names into. 2425 * @param n 2426 * Number of names. 2427 * 2428 * @return 2429 * Number of xstats names. 2430 */ 2431 static int ena_xstats_get_names(struct rte_eth_dev *dev, 2432 struct rte_eth_xstat_name *xstats_names, 2433 unsigned int n) 2434 { 2435 unsigned int xstats_count = ena_xstats_calc_num(dev); 2436 unsigned int stat, i, count = 0; 2437 2438 if (n < xstats_count || !xstats_names) 2439 return xstats_count; 2440 2441 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) 2442 strcpy(xstats_names[count].name, 2443 ena_stats_global_strings[stat].name); 2444 2445 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) 2446 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) 2447 snprintf(xstats_names[count].name, 2448 sizeof(xstats_names[count].name), 2449 "rx_q%d_%s", i, 2450 ena_stats_rx_strings[stat].name); 2451 2452 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) 2453 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) 2454 snprintf(xstats_names[count].name, 2455 sizeof(xstats_names[count].name), 2456 "tx_q%d_%s", i, 2457 ena_stats_tx_strings[stat].name); 2458 2459 return xstats_count; 2460 } 2461 2462 /** 2463 * DPDK callback to get extended device statistics. 2464 * 2465 * @param dev 2466 * Pointer to Ethernet device structure. 2467 * @param[out] stats 2468 * Stats table output buffer. 2469 * @param n 2470 * The size of the stats table. 2471 * 2472 * @return 2473 * Number of xstats on success, negative on failure. 2474 */ 2475 static int ena_xstats_get(struct rte_eth_dev *dev, 2476 struct rte_eth_xstat *xstats, 2477 unsigned int n) 2478 { 2479 struct ena_adapter *adapter = dev->data->dev_private; 2480 unsigned int xstats_count = ena_xstats_calc_num(dev); 2481 unsigned int stat, i, count = 0; 2482 int stat_offset; 2483 void *stats_begin; 2484 2485 if (n < xstats_count) 2486 return xstats_count; 2487 2488 if (!xstats) 2489 return 0; 2490 2491 for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) { 2492 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2493 stats_begin = &adapter->dev_stats; 2494 2495 xstats[count].id = count; 2496 xstats[count].value = *((uint64_t *) 2497 ((char *)stats_begin + stat_offset)); 2498 } 2499 2500 for (stat = 0; stat < ENA_STATS_ARRAY_RX; stat++) { 2501 for (i = 0; i < dev->data->nb_rx_queues; i++, count++) { 2502 stat_offset = ena_stats_rx_strings[stat].stat_offset; 2503 stats_begin = &adapter->rx_ring[i].rx_stats; 2504 2505 xstats[count].id = count; 2506 xstats[count].value = *((uint64_t *) 2507 ((char *)stats_begin + stat_offset)); 2508 } 2509 } 2510 2511 for (stat = 0; stat < ENA_STATS_ARRAY_TX; stat++) { 2512 for (i = 0; i < dev->data->nb_tx_queues; i++, count++) { 2513 stat_offset = ena_stats_tx_strings[stat].stat_offset; 2514 stats_begin = &adapter->tx_ring[i].rx_stats; 2515 2516 xstats[count].id = count; 2517 xstats[count].value = *((uint64_t *) 2518 ((char *)stats_begin + stat_offset)); 2519 } 2520 } 2521 2522 return count; 2523 } 2524 2525 static int ena_xstats_get_by_id(struct rte_eth_dev *dev, 2526 const uint64_t *ids, 2527 uint64_t *values, 2528 unsigned int n) 2529 { 2530 struct ena_adapter *adapter = dev->data->dev_private; 2531 uint64_t id; 2532 uint64_t rx_entries, tx_entries; 2533 unsigned int i; 2534 int qid; 2535 int valid = 0; 2536 for (i = 0; i < n; ++i) { 2537 id = ids[i]; 2538 /* Check if id belongs to global statistics */ 2539 if (id < ENA_STATS_ARRAY_GLOBAL) { 2540 values[i] = *((uint64_t *)&adapter->dev_stats + id); 2541 ++valid; 2542 continue; 2543 } 2544 2545 /* Check if id belongs to rx queue statistics */ 2546 id -= ENA_STATS_ARRAY_GLOBAL; 2547 rx_entries = ENA_STATS_ARRAY_RX * dev->data->nb_rx_queues; 2548 if (id < rx_entries) { 2549 qid = id % dev->data->nb_rx_queues; 2550 id /= dev->data->nb_rx_queues; 2551 values[i] = *((uint64_t *) 2552 &adapter->rx_ring[qid].rx_stats + id); 2553 ++valid; 2554 continue; 2555 } 2556 /* Check if id belongs to rx queue statistics */ 2557 id -= rx_entries; 2558 tx_entries = ENA_STATS_ARRAY_TX * dev->data->nb_tx_queues; 2559 if (id < tx_entries) { 2560 qid = id % dev->data->nb_tx_queues; 2561 id /= dev->data->nb_tx_queues; 2562 values[i] = *((uint64_t *) 2563 &adapter->tx_ring[qid].tx_stats + id); 2564 ++valid; 2565 continue; 2566 } 2567 } 2568 2569 return valid; 2570 } 2571 2572 /********************************************************************* 2573 * PMD configuration 2574 *********************************************************************/ 2575 static int eth_ena_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2576 struct rte_pci_device *pci_dev) 2577 { 2578 return rte_eth_dev_pci_generic_probe(pci_dev, 2579 sizeof(struct ena_adapter), eth_ena_dev_init); 2580 } 2581 2582 static int eth_ena_pci_remove(struct rte_pci_device *pci_dev) 2583 { 2584 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ena_dev_uninit); 2585 } 2586 2587 static struct rte_pci_driver rte_ena_pmd = { 2588 .id_table = pci_id_ena_map, 2589 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 2590 RTE_PCI_DRV_WC_ACTIVATE, 2591 .probe = eth_ena_pci_probe, 2592 .remove = eth_ena_pci_remove, 2593 }; 2594 2595 RTE_PMD_REGISTER_PCI(net_ena, rte_ena_pmd); 2596 RTE_PMD_REGISTER_PCI_TABLE(net_ena, pci_id_ena_map); 2597 RTE_PMD_REGISTER_KMOD_DEP(net_ena, "* igb_uio | uio_pci_generic | vfio-pci"); 2598 2599 RTE_INIT(ena_init_log) 2600 { 2601 ena_logtype_init = rte_log_register("pmd.net.ena.init"); 2602 if (ena_logtype_init >= 0) 2603 rte_log_set_level(ena_logtype_init, RTE_LOG_NOTICE); 2604 ena_logtype_driver = rte_log_register("pmd.net.ena.driver"); 2605 if (ena_logtype_driver >= 0) 2606 rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE); 2607 } 2608 2609 /****************************************************************************** 2610 ******************************** AENQ Handlers ******************************* 2611 *****************************************************************************/ 2612 static void ena_update_on_link_change(void *adapter_data, 2613 struct ena_admin_aenq_entry *aenq_e) 2614 { 2615 struct rte_eth_dev *eth_dev; 2616 struct ena_adapter *adapter; 2617 struct ena_admin_aenq_link_change_desc *aenq_link_desc; 2618 uint32_t status; 2619 2620 adapter = adapter_data; 2621 aenq_link_desc = (struct ena_admin_aenq_link_change_desc *)aenq_e; 2622 eth_dev = adapter->rte_dev; 2623 2624 status = get_ena_admin_aenq_link_change_desc_link_status(aenq_link_desc); 2625 adapter->link_status = status; 2626 2627 ena_link_update(eth_dev, 0); 2628 _rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_INTR_LSC, NULL); 2629 } 2630 2631 static void ena_notification(void *data, 2632 struct ena_admin_aenq_entry *aenq_e) 2633 { 2634 struct ena_adapter *adapter = data; 2635 struct ena_admin_ena_hw_hints *hints; 2636 2637 if (aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION) 2638 RTE_LOG(WARNING, PMD, "Invalid group(%x) expected %x\n", 2639 aenq_e->aenq_common_desc.group, 2640 ENA_ADMIN_NOTIFICATION); 2641 2642 switch (aenq_e->aenq_common_desc.syndrom) { 2643 case ENA_ADMIN_UPDATE_HINTS: 2644 hints = (struct ena_admin_ena_hw_hints *) 2645 (&aenq_e->inline_data_w4); 2646 ena_update_hints(adapter, hints); 2647 break; 2648 default: 2649 RTE_LOG(ERR, PMD, "Invalid aenq notification link state %d\n", 2650 aenq_e->aenq_common_desc.syndrom); 2651 } 2652 } 2653 2654 static void ena_keep_alive(void *adapter_data, 2655 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2656 { 2657 struct ena_adapter *adapter = adapter_data; 2658 struct ena_admin_aenq_keep_alive_desc *desc; 2659 uint64_t rx_drops; 2660 2661 adapter->timestamp_wd = rte_get_timer_cycles(); 2662 2663 desc = (struct ena_admin_aenq_keep_alive_desc *)aenq_e; 2664 rx_drops = ((uint64_t)desc->rx_drops_high << 32) | desc->rx_drops_low; 2665 rte_atomic64_set(&adapter->drv_stats->rx_drops, rx_drops); 2666 } 2667 2668 /** 2669 * This handler will called for unknown event group or unimplemented handlers 2670 **/ 2671 static void unimplemented_aenq_handler(__rte_unused void *data, 2672 __rte_unused struct ena_admin_aenq_entry *aenq_e) 2673 { 2674 RTE_LOG(ERR, PMD, "Unknown event was received or event with " 2675 "unimplemented handler\n"); 2676 } 2677 2678 static struct ena_aenq_handlers aenq_handlers = { 2679 .handlers = { 2680 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change, 2681 [ENA_ADMIN_NOTIFICATION] = ena_notification, 2682 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive 2683 }, 2684 .unimplemented_handler = unimplemented_aenq_handler 2685 }; 2686