10817d41fSNipun Gupta /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 20817d41fSNipun Gupta * 30817d41fSNipun Gupta * Copyright 2013-2016 Freescale Semiconductor Inc. 4*591200efSGagandeep Singh * Copyright 2018-2023 NXP 50817d41fSNipun Gupta * 60817d41fSNipun Gupta */ 70817d41fSNipun Gupta #ifndef _FSL_DPDMUX_CMD_H 80817d41fSNipun Gupta #define _FSL_DPDMUX_CMD_H 90817d41fSNipun Gupta 100817d41fSNipun Gupta /* DPDMUX Version */ 110817d41fSNipun Gupta #define DPDMUX_VER_MAJOR 6 12*591200efSGagandeep Singh #define DPDMUX_VER_MINOR 10 130817d41fSNipun Gupta 140817d41fSNipun Gupta #define DPDMUX_CMD_BASE_VERSION 1 150817d41fSNipun Gupta #define DPDMUX_CMD_VERSION_2 2 163d43972bSHemant Agrawal #define DPDMUX_CMD_VERSION_3 3 173d43972bSHemant Agrawal #define DPDMUX_CMD_VERSION_4 4 180817d41fSNipun Gupta #define DPDMUX_CMD_ID_OFFSET 4 190817d41fSNipun Gupta 200817d41fSNipun Gupta #define DPDMUX_CMD(id) (((id) << DPDMUX_CMD_ID_OFFSET) |\ 210817d41fSNipun Gupta DPDMUX_CMD_BASE_VERSION) 220817d41fSNipun Gupta #define DPDMUX_CMD_V2(id) (((id) << DPDMUX_CMD_ID_OFFSET) | \ 230817d41fSNipun Gupta DPDMUX_CMD_VERSION_2) 243d43972bSHemant Agrawal #define DPDMUX_CMD_V3(id) (((id) << DPDMUX_CMD_ID_OFFSET) |\ 253d43972bSHemant Agrawal DPDMUX_CMD_VERSION_3) 263d43972bSHemant Agrawal #define DPDMUX_CMD_V4(id) (((id) << DPDMUX_CMD_ID_OFFSET) |\ 273d43972bSHemant Agrawal DPDMUX_CMD_VERSION_4) 280817d41fSNipun Gupta 290817d41fSNipun Gupta /* Command IDs */ 300817d41fSNipun Gupta #define DPDMUX_CMDID_CLOSE DPDMUX_CMD(0x800) 310817d41fSNipun Gupta #define DPDMUX_CMDID_OPEN DPDMUX_CMD(0x806) 323d43972bSHemant Agrawal #define DPDMUX_CMDID_CREATE DPDMUX_CMD_V4(0x906) 330817d41fSNipun Gupta #define DPDMUX_CMDID_DESTROY DPDMUX_CMD(0x986) 340817d41fSNipun Gupta #define DPDMUX_CMDID_GET_API_VERSION DPDMUX_CMD(0xa06) 350817d41fSNipun Gupta 360817d41fSNipun Gupta #define DPDMUX_CMDID_ENABLE DPDMUX_CMD(0x002) 370817d41fSNipun Gupta #define DPDMUX_CMDID_DISABLE DPDMUX_CMD(0x003) 38f48cd6c6SNipun Gupta #define DPDMUX_CMDID_GET_ATTR DPDMUX_CMD_V3(0x004) 390817d41fSNipun Gupta #define DPDMUX_CMDID_RESET DPDMUX_CMD(0x005) 400817d41fSNipun Gupta #define DPDMUX_CMDID_IS_ENABLED DPDMUX_CMD(0x006) 410817d41fSNipun Gupta #define DPDMUX_CMDID_SET_MAX_FRAME_LENGTH DPDMUX_CMD(0x0a1) 422cb2abf3SHemant Agrawal #define DPDMUX_CMDID_GET_MAX_FRAME_LENGTH DPDMUX_CMD(0x0a2) 430817d41fSNipun Gupta 440817d41fSNipun Gupta #define DPDMUX_CMDID_UL_RESET_COUNTERS DPDMUX_CMD(0x0a3) 450817d41fSNipun Gupta 460817d41fSNipun Gupta #define DPDMUX_CMDID_IF_SET_ACCEPTED_FRAMES DPDMUX_CMD(0x0a7) 470817d41fSNipun Gupta #define DPDMUX_CMDID_IF_GET_ATTR DPDMUX_CMD(0x0a8) 480817d41fSNipun Gupta #define DPDMUX_CMDID_IF_ENABLE DPDMUX_CMD(0x0a9) 490817d41fSNipun Gupta #define DPDMUX_CMDID_IF_DISABLE DPDMUX_CMD(0x0aa) 500817d41fSNipun Gupta 510817d41fSNipun Gupta #define DPDMUX_CMDID_IF_ADD_L2_RULE DPDMUX_CMD(0x0b0) 520817d41fSNipun Gupta #define DPDMUX_CMDID_IF_REMOVE_L2_RULE DPDMUX_CMD(0x0b1) 530817d41fSNipun Gupta #define DPDMUX_CMDID_IF_GET_COUNTER DPDMUX_CMD(0x0b2) 540817d41fSNipun Gupta #define DPDMUX_CMDID_IF_SET_LINK_CFG DPDMUX_CMD_V2(0x0b3) 550817d41fSNipun Gupta #define DPDMUX_CMDID_IF_GET_LINK_STATE DPDMUX_CMD_V2(0x0b4) 560817d41fSNipun Gupta 570817d41fSNipun Gupta #define DPDMUX_CMDID_SET_CUSTOM_KEY DPDMUX_CMD(0x0b5) 583d43972bSHemant Agrawal #define DPDMUX_CMDID_ADD_CUSTOM_CLS_ENTRY DPDMUX_CMD_V2(0x0b6) 590817d41fSNipun Gupta #define DPDMUX_CMDID_REMOVE_CUSTOM_CLS_ENTRY DPDMUX_CMD(0x0b7) 600817d41fSNipun Gupta 610817d41fSNipun Gupta #define DPDMUX_CMDID_IF_SET_DEFAULT DPDMUX_CMD(0x0b8) 620817d41fSNipun Gupta #define DPDMUX_CMDID_IF_GET_DEFAULT DPDMUX_CMD(0x0b9) 630817d41fSNipun Gupta 64914450baSApeksha Gupta #define DPDMUX_CMDID_SET_RESETABLE DPDMUX_CMD(0x0ba) 65914450baSApeksha Gupta #define DPDMUX_CMDID_GET_RESETABLE DPDMUX_CMD(0x0bb) 66*591200efSGagandeep Singh 67*591200efSGagandeep Singh #define DPDMUX_CMDID_IF_SET_TAILDROP DPDMUX_CMD(0x0bc) 68*591200efSGagandeep Singh #define DPDMUX_CMDID_IF_GET_TAILDROP DPDMUX_CMD(0x0bd) 69*591200efSGagandeep Singh 70*591200efSGagandeep Singh #define DPDMUX_CMDID_DUMP_TABLE DPDMUX_CMD(0x0be) 71*591200efSGagandeep Singh 723d43972bSHemant Agrawal #define DPDMUX_CMDID_SET_ERRORS_BEHAVIOR DPDMUX_CMD(0x0bf) 73914450baSApeksha Gupta 74*591200efSGagandeep Singh #define DPDMUX_CMDID_SET_SP_PROFILE DPDMUX_CMD(0x0c0) 75*591200efSGagandeep Singh #define DPDMUX_CMDID_SP_ENABLE DPDMUX_CMD(0x0c1) 76*591200efSGagandeep Singh 770817d41fSNipun Gupta #define DPDMUX_MASK(field) \ 780817d41fSNipun Gupta GENMASK(DPDMUX_##field##_SHIFT + DPDMUX_##field##_SIZE - 1, \ 790817d41fSNipun Gupta DPDMUX_##field##_SHIFT) 800817d41fSNipun Gupta #define dpdmux_set_field(var, field, val) \ 810817d41fSNipun Gupta ((var) |= (((val) << DPDMUX_##field##_SHIFT) & DPDMUX_MASK(field))) 820817d41fSNipun Gupta #define dpdmux_get_field(var, field) \ 830817d41fSNipun Gupta (((var) & DPDMUX_MASK(field)) >> DPDMUX_##field##_SHIFT) 840817d41fSNipun Gupta 850817d41fSNipun Gupta #pragma pack(push, 1) 860817d41fSNipun Gupta struct dpdmux_cmd_open { 870817d41fSNipun Gupta uint32_t dpdmux_id; 880817d41fSNipun Gupta }; 890817d41fSNipun Gupta 900817d41fSNipun Gupta struct dpdmux_cmd_create { 910817d41fSNipun Gupta uint8_t method; 920817d41fSNipun Gupta uint8_t manip; 930817d41fSNipun Gupta uint16_t num_ifs; 94914450baSApeksha Gupta uint16_t default_if; 95914450baSApeksha Gupta uint16_t pad; 960817d41fSNipun Gupta 970817d41fSNipun Gupta uint16_t adv_max_dmat_entries; 980817d41fSNipun Gupta uint16_t adv_max_mc_groups; 990817d41fSNipun Gupta uint16_t adv_max_vlan_ids; 100914450baSApeksha Gupta uint16_t mem_size; 1010817d41fSNipun Gupta 1020817d41fSNipun Gupta uint64_t options; 1030817d41fSNipun Gupta }; 1040817d41fSNipun Gupta 1050817d41fSNipun Gupta struct dpdmux_cmd_destroy { 1060817d41fSNipun Gupta uint32_t dpdmux_id; 1070817d41fSNipun Gupta }; 1080817d41fSNipun Gupta 1090817d41fSNipun Gupta #define DPDMUX_ENABLE_SHIFT 0 1100817d41fSNipun Gupta #define DPDMUX_ENABLE_SIZE 1 1110817d41fSNipun Gupta #define DPDMUX_IS_DEFAULT_SHIFT 1 1120817d41fSNipun Gupta #define DPDMUX_IS_DEFAULT_SIZE 1 1130817d41fSNipun Gupta 1140817d41fSNipun Gupta struct dpdmux_rsp_is_enabled { 1150817d41fSNipun Gupta uint8_t en; 1160817d41fSNipun Gupta }; 1170817d41fSNipun Gupta 1180817d41fSNipun Gupta struct dpdmux_rsp_get_attr { 1190817d41fSNipun Gupta uint8_t method; 1200817d41fSNipun Gupta uint8_t manip; 1210817d41fSNipun Gupta uint16_t num_ifs; 1220817d41fSNipun Gupta uint16_t mem_size; 123914450baSApeksha Gupta uint16_t default_if; 1240817d41fSNipun Gupta 1250817d41fSNipun Gupta uint64_t pad1; 1260817d41fSNipun Gupta 1270817d41fSNipun Gupta uint32_t id; 1280817d41fSNipun Gupta uint32_t pad2; 1290817d41fSNipun Gupta 1300817d41fSNipun Gupta uint64_t options; 131f48cd6c6SNipun Gupta uint16_t max_dmat_entries; 132f48cd6c6SNipun Gupta uint16_t max_mc_groups; 133f48cd6c6SNipun Gupta uint16_t max_vlan_ids; 1340817d41fSNipun Gupta }; 1350817d41fSNipun Gupta 1360817d41fSNipun Gupta struct dpdmux_cmd_set_max_frame_length { 1370817d41fSNipun Gupta uint16_t max_frame_length; 1380817d41fSNipun Gupta }; 1390817d41fSNipun Gupta 1402cb2abf3SHemant Agrawal struct dpdmux_cmd_get_max_frame_len { 1412cb2abf3SHemant Agrawal uint16_t if_id; 1422cb2abf3SHemant Agrawal }; 1432cb2abf3SHemant Agrawal 1442cb2abf3SHemant Agrawal struct dpdmux_rsp_get_max_frame_len { 1452cb2abf3SHemant Agrawal uint16_t max_len; 1462cb2abf3SHemant Agrawal }; 1472cb2abf3SHemant Agrawal 1480817d41fSNipun Gupta #define DPDMUX_ACCEPTED_FRAMES_TYPE_SHIFT 0 1490817d41fSNipun Gupta #define DPDMUX_ACCEPTED_FRAMES_TYPE_SIZE 4 1500817d41fSNipun Gupta #define DPDMUX_UNACCEPTED_FRAMES_ACTION_SHIFT 4 1510817d41fSNipun Gupta #define DPDMUX_UNACCEPTED_FRAMES_ACTION_SIZE 4 1520817d41fSNipun Gupta 1530817d41fSNipun Gupta struct dpdmux_cmd_if_set_accepted_frames { 1540817d41fSNipun Gupta uint16_t if_id; 1550817d41fSNipun Gupta uint8_t frames_options; 1560817d41fSNipun Gupta }; 1570817d41fSNipun Gupta 1580817d41fSNipun Gupta struct dpdmux_cmd_if { 1590817d41fSNipun Gupta uint16_t if_id; 1600817d41fSNipun Gupta }; 1610817d41fSNipun Gupta 1620817d41fSNipun Gupta struct dpdmux_rsp_if_get_attr { 1630817d41fSNipun Gupta uint8_t pad[3]; 1640817d41fSNipun Gupta uint8_t enabled; 1650817d41fSNipun Gupta uint8_t pad1[3]; 1660817d41fSNipun Gupta uint8_t accepted_frames_type; 1670817d41fSNipun Gupta uint32_t rate; 1680817d41fSNipun Gupta }; 1690817d41fSNipun Gupta 1700817d41fSNipun Gupta struct dpdmux_cmd_if_l2_rule { 1710817d41fSNipun Gupta uint16_t if_id; 1720817d41fSNipun Gupta uint8_t mac_addr5; 1730817d41fSNipun Gupta uint8_t mac_addr4; 1740817d41fSNipun Gupta uint8_t mac_addr3; 1750817d41fSNipun Gupta uint8_t mac_addr2; 1760817d41fSNipun Gupta uint8_t mac_addr1; 1770817d41fSNipun Gupta uint8_t mac_addr0; 1780817d41fSNipun Gupta 1790817d41fSNipun Gupta uint32_t pad; 1800817d41fSNipun Gupta uint16_t vlan_id; 1810817d41fSNipun Gupta }; 1820817d41fSNipun Gupta 1830817d41fSNipun Gupta struct dpdmux_cmd_if_get_counter { 1840817d41fSNipun Gupta uint16_t if_id; 1850817d41fSNipun Gupta uint8_t counter_type; 1860817d41fSNipun Gupta }; 1870817d41fSNipun Gupta 1880817d41fSNipun Gupta struct dpdmux_rsp_if_get_counter { 1890817d41fSNipun Gupta uint64_t pad; 1900817d41fSNipun Gupta uint64_t counter; 1910817d41fSNipun Gupta }; 1920817d41fSNipun Gupta 1930817d41fSNipun Gupta struct dpdmux_cmd_if_set_link_cfg { 1940817d41fSNipun Gupta uint16_t if_id; 1950817d41fSNipun Gupta uint16_t pad[3]; 1960817d41fSNipun Gupta 1970817d41fSNipun Gupta uint32_t rate; 1980817d41fSNipun Gupta uint32_t pad1; 1990817d41fSNipun Gupta 2000817d41fSNipun Gupta uint64_t options; 2010817d41fSNipun Gupta uint64_t advertising; 2020817d41fSNipun Gupta }; 2030817d41fSNipun Gupta 2040817d41fSNipun Gupta struct dpdmux_cmd_if_get_link_state { 2050817d41fSNipun Gupta uint16_t if_id; 2060817d41fSNipun Gupta }; 2070817d41fSNipun Gupta 2080817d41fSNipun Gupta #define DPDMUX_UP_SHIFT 0 2090817d41fSNipun Gupta #define DPDMUX_UP_SIZE 1 2100817d41fSNipun Gupta #define DPDMUX_STATE_VALID_SHIFT 1 2110817d41fSNipun Gupta #define DPDMUX_STATE_VALID_SIZE 1 2120817d41fSNipun Gupta struct dpdmux_rsp_if_get_link_state { 2130817d41fSNipun Gupta uint32_t pad; 2140817d41fSNipun Gupta uint8_t up; 2150817d41fSNipun Gupta uint8_t pad1[3]; 2160817d41fSNipun Gupta 2170817d41fSNipun Gupta uint32_t rate; 2180817d41fSNipun Gupta uint32_t pad2; 2190817d41fSNipun Gupta 2200817d41fSNipun Gupta uint64_t options; 2210817d41fSNipun Gupta uint64_t supported; 2220817d41fSNipun Gupta uint64_t advertising; 2230817d41fSNipun Gupta }; 2240817d41fSNipun Gupta 2250817d41fSNipun Gupta struct dpdmux_rsp_get_api_version { 2260817d41fSNipun Gupta uint16_t major; 2270817d41fSNipun Gupta uint16_t minor; 2280817d41fSNipun Gupta }; 2290817d41fSNipun Gupta 2300817d41fSNipun Gupta struct dpdmux_set_custom_key { 2310817d41fSNipun Gupta uint64_t pad[6]; 2320817d41fSNipun Gupta uint64_t key_cfg_iova; 2330817d41fSNipun Gupta }; 2340817d41fSNipun Gupta 2350817d41fSNipun Gupta struct dpdmux_cmd_add_custom_cls_entry { 2360817d41fSNipun Gupta uint8_t pad[3]; 2370817d41fSNipun Gupta uint8_t key_size; 238e5e9ef72SAkhil Goyal uint16_t entry_index; 2390817d41fSNipun Gupta uint16_t dest_if; 2400817d41fSNipun Gupta uint64_t key_iova; 2410817d41fSNipun Gupta uint64_t mask_iova; 2420817d41fSNipun Gupta }; 2430817d41fSNipun Gupta 2440817d41fSNipun Gupta struct dpdmux_cmd_remove_custom_cls_entry { 2450817d41fSNipun Gupta uint8_t pad[3]; 2460817d41fSNipun Gupta uint8_t key_size; 2470817d41fSNipun Gupta uint32_t pad1; 2480817d41fSNipun Gupta uint64_t key_iova; 2490817d41fSNipun Gupta uint64_t mask_iova; 2500817d41fSNipun Gupta }; 251914450baSApeksha Gupta 252914450baSApeksha Gupta #define DPDMUX_SKIP_RESET_FLAGS_SHIFT 0 253*591200efSGagandeep Singh #define DPDMUX_SKIP_RESET_FLAGS_SIZE 4 254914450baSApeksha Gupta 255914450baSApeksha Gupta struct dpdmux_cmd_set_skip_reset_flags { 256914450baSApeksha Gupta uint8_t skip_reset_flags; 257914450baSApeksha Gupta }; 258914450baSApeksha Gupta 259914450baSApeksha Gupta struct dpdmux_rsp_get_skip_reset_flags { 260914450baSApeksha Gupta uint8_t skip_reset_flags; 261914450baSApeksha Gupta }; 262914450baSApeksha Gupta 263*591200efSGagandeep Singh struct dpdmux_cmd_set_taildrop { 264*591200efSGagandeep Singh uint32_t pad1; 265*591200efSGagandeep Singh uint16_t if_id; 266*591200efSGagandeep Singh uint16_t pad2; 267*591200efSGagandeep Singh uint16_t oal_en; 268*591200efSGagandeep Singh uint8_t units; 269*591200efSGagandeep Singh uint8_t pad3; 270*591200efSGagandeep Singh uint32_t threshold; 271*591200efSGagandeep Singh }; 272*591200efSGagandeep Singh 273*591200efSGagandeep Singh struct dpdmux_cmd_get_taildrop { 274*591200efSGagandeep Singh uint32_t pad1; 275*591200efSGagandeep Singh uint16_t if_id; 276*591200efSGagandeep Singh }; 277*591200efSGagandeep Singh 278*591200efSGagandeep Singh struct dpdmux_rsp_get_taildrop { 279*591200efSGagandeep Singh uint16_t pad1; 280*591200efSGagandeep Singh uint16_t pad2; 281*591200efSGagandeep Singh uint16_t if_id; 282*591200efSGagandeep Singh uint16_t pad3; 283*591200efSGagandeep Singh uint16_t oal_en; 284*591200efSGagandeep Singh uint8_t units; 285*591200efSGagandeep Singh uint8_t pad4; 286*591200efSGagandeep Singh uint32_t threshold; 287*591200efSGagandeep Singh }; 288*591200efSGagandeep Singh 289*591200efSGagandeep Singh struct dpdmux_cmd_dump_table { 290*591200efSGagandeep Singh uint16_t table_type; 291*591200efSGagandeep Singh uint16_t table_index; 292*591200efSGagandeep Singh uint32_t pad0; 293*591200efSGagandeep Singh uint64_t iova_addr; 294*591200efSGagandeep Singh uint32_t iova_size; 295*591200efSGagandeep Singh }; 296*591200efSGagandeep Singh 297*591200efSGagandeep Singh struct dpdmux_rsp_dump_table { 298*591200efSGagandeep Singh uint16_t num_entries; 299*591200efSGagandeep Singh }; 300*591200efSGagandeep Singh 301*591200efSGagandeep Singh struct dpdmux_dump_table_header { 302*591200efSGagandeep Singh uint16_t table_type; 303*591200efSGagandeep Singh uint16_t table_num_entries; 304*591200efSGagandeep Singh uint16_t table_max_entries; 305*591200efSGagandeep Singh uint8_t default_action; 306*591200efSGagandeep Singh uint8_t match_type; 307*591200efSGagandeep Singh uint8_t reserved[24]; 308*591200efSGagandeep Singh }; 309*591200efSGagandeep Singh 310*591200efSGagandeep Singh struct dpdmux_dump_table_entry { 311*591200efSGagandeep Singh uint8_t key[DPDMUX_MAX_KEY_SIZE]; 312*591200efSGagandeep Singh uint8_t mask[DPDMUX_MAX_KEY_SIZE]; 313*591200efSGagandeep Singh uint8_t key_action; 314*591200efSGagandeep Singh uint16_t result[3]; 315*591200efSGagandeep Singh uint8_t reserved[21]; 316*591200efSGagandeep Singh }; 317*591200efSGagandeep Singh 3183d43972bSHemant Agrawal #define DPDMUX_ERROR_ACTION_SHIFT 0 3193d43972bSHemant Agrawal #define DPDMUX_ERROR_ACTION_SIZE 4 3203d43972bSHemant Agrawal 3213d43972bSHemant Agrawal struct dpdmux_cmd_set_errors_behavior { 3223d43972bSHemant Agrawal uint32_t errors; 3233d43972bSHemant Agrawal uint16_t flags; 3243d43972bSHemant Agrawal uint16_t if_id; 3253d43972bSHemant Agrawal }; 3263d43972bSHemant Agrawal 327*591200efSGagandeep Singh #define MAX_SP_PROFILE_ID_SIZE 8 328*591200efSGagandeep Singh 329*591200efSGagandeep Singh struct dpdmux_cmd_set_sp_profile { 330*591200efSGagandeep Singh uint8_t sp_profile[MAX_SP_PROFILE_ID_SIZE]; 331*591200efSGagandeep Singh uint8_t type; 332*591200efSGagandeep Singh }; 333*591200efSGagandeep Singh 334*591200efSGagandeep Singh struct dpdmux_cmd_sp_enable { 335*591200efSGagandeep Singh uint16_t if_id; 336*591200efSGagandeep Singh uint8_t type; 337*591200efSGagandeep Singh uint8_t en; 338*591200efSGagandeep Singh }; 339*591200efSGagandeep Singh 3400817d41fSNipun Gupta #pragma pack(pop) 3410817d41fSNipun Gupta #endif /* _FSL_DPDMUX_CMD_H */ 342