1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_rxtx.h" 7 #include "axgbe_ethdev.h" 8 #include "axgbe_common.h" 9 #include "axgbe_phy.h" 10 11 static int eth_axgbe_dev_init(struct rte_eth_dev *eth_dev); 12 static int eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev); 13 static int axgbe_dev_configure(struct rte_eth_dev *dev); 14 static int axgbe_dev_start(struct rte_eth_dev *dev); 15 static void axgbe_dev_stop(struct rte_eth_dev *dev); 16 static void axgbe_dev_interrupt_handler(void *param); 17 static void axgbe_dev_close(struct rte_eth_dev *dev); 18 static void axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev); 19 static void axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev); 20 static void axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev); 21 static void axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev); 22 static int axgbe_dev_link_update(struct rte_eth_dev *dev, 23 int wait_to_complete); 24 static int axgbe_dev_stats_get(struct rte_eth_dev *dev, 25 struct rte_eth_stats *stats); 26 static void axgbe_dev_stats_reset(struct rte_eth_dev *dev); 27 static int axgbe_dev_info_get(struct rte_eth_dev *dev, 28 struct rte_eth_dev_info *dev_info); 29 30 /* The set of PCI devices this driver supports */ 31 #define AMD_PCI_VENDOR_ID 0x1022 32 #define AMD_PCI_AXGBE_DEVICE_V2A 0x1458 33 #define AMD_PCI_AXGBE_DEVICE_V2B 0x1459 34 35 int axgbe_logtype_init; 36 int axgbe_logtype_driver; 37 38 static const struct rte_pci_id pci_id_axgbe_map[] = { 39 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2A)}, 40 {RTE_PCI_DEVICE(AMD_PCI_VENDOR_ID, AMD_PCI_AXGBE_DEVICE_V2B)}, 41 { .vendor_id = 0, }, 42 }; 43 44 static struct axgbe_version_data axgbe_v2a = { 45 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 46 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 47 .mmc_64bit = 1, 48 .tx_max_fifo_size = 229376, 49 .rx_max_fifo_size = 229376, 50 .tx_tstamp_workaround = 1, 51 .ecc_support = 1, 52 .i2c_support = 1, 53 .an_cdr_workaround = 1, 54 }; 55 56 static struct axgbe_version_data axgbe_v2b = { 57 .init_function_ptrs_phy_impl = axgbe_init_function_ptrs_phy_v2, 58 .xpcs_access = AXGBE_XPCS_ACCESS_V2, 59 .mmc_64bit = 1, 60 .tx_max_fifo_size = 65536, 61 .rx_max_fifo_size = 65536, 62 .tx_tstamp_workaround = 1, 63 .ecc_support = 1, 64 .i2c_support = 1, 65 .an_cdr_workaround = 1, 66 }; 67 68 static const struct rte_eth_desc_lim rx_desc_lim = { 69 .nb_max = AXGBE_MAX_RING_DESC, 70 .nb_min = AXGBE_MIN_RING_DESC, 71 .nb_align = 8, 72 }; 73 74 static const struct rte_eth_desc_lim tx_desc_lim = { 75 .nb_max = AXGBE_MAX_RING_DESC, 76 .nb_min = AXGBE_MIN_RING_DESC, 77 .nb_align = 8, 78 }; 79 80 static const struct eth_dev_ops axgbe_eth_dev_ops = { 81 .dev_configure = axgbe_dev_configure, 82 .dev_start = axgbe_dev_start, 83 .dev_stop = axgbe_dev_stop, 84 .dev_close = axgbe_dev_close, 85 .promiscuous_enable = axgbe_dev_promiscuous_enable, 86 .promiscuous_disable = axgbe_dev_promiscuous_disable, 87 .allmulticast_enable = axgbe_dev_allmulticast_enable, 88 .allmulticast_disable = axgbe_dev_allmulticast_disable, 89 .link_update = axgbe_dev_link_update, 90 .stats_get = axgbe_dev_stats_get, 91 .stats_reset = axgbe_dev_stats_reset, 92 .dev_infos_get = axgbe_dev_info_get, 93 .rx_queue_setup = axgbe_dev_rx_queue_setup, 94 .rx_queue_release = axgbe_dev_rx_queue_release, 95 .tx_queue_setup = axgbe_dev_tx_queue_setup, 96 .tx_queue_release = axgbe_dev_tx_queue_release, 97 }; 98 99 static int axgbe_phy_reset(struct axgbe_port *pdata) 100 { 101 pdata->phy_link = -1; 102 pdata->phy_speed = SPEED_UNKNOWN; 103 return pdata->phy_if.phy_reset(pdata); 104 } 105 106 /* 107 * Interrupt handler triggered by NIC for handling 108 * specific interrupt. 109 * 110 * @param handle 111 * Pointer to interrupt handle. 112 * @param param 113 * The address of parameter (struct rte_eth_dev *) regsitered before. 114 * 115 * @return 116 * void 117 */ 118 static void 119 axgbe_dev_interrupt_handler(void *param) 120 { 121 struct rte_eth_dev *dev = (struct rte_eth_dev *)param; 122 struct axgbe_port *pdata = dev->data->dev_private; 123 unsigned int dma_isr, dma_ch_isr; 124 125 pdata->phy_if.an_isr(pdata); 126 /*DMA related interrupts*/ 127 dma_isr = AXGMAC_IOREAD(pdata, DMA_ISR); 128 if (dma_isr) { 129 if (dma_isr & 1) { 130 dma_ch_isr = 131 AXGMAC_DMA_IOREAD((struct axgbe_rx_queue *) 132 pdata->rx_queues[0], 133 DMA_CH_SR); 134 AXGMAC_DMA_IOWRITE((struct axgbe_rx_queue *) 135 pdata->rx_queues[0], 136 DMA_CH_SR, dma_ch_isr); 137 } 138 } 139 /* Unmask interrupts since disabled after generation */ 140 rte_intr_ack(&pdata->pci_dev->intr_handle); 141 } 142 143 /* 144 * Configure device link speed and setup link. 145 * It returns 0 on success. 146 */ 147 static int 148 axgbe_dev_configure(struct rte_eth_dev *dev) 149 { 150 struct axgbe_port *pdata = dev->data->dev_private; 151 /* Checksum offload to hardware */ 152 pdata->rx_csum_enable = dev->data->dev_conf.rxmode.offloads & 153 DEV_RX_OFFLOAD_CHECKSUM; 154 return 0; 155 } 156 157 static int 158 axgbe_dev_rx_mq_config(struct rte_eth_dev *dev) 159 { 160 struct axgbe_port *pdata = dev->data->dev_private; 161 162 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS) 163 pdata->rss_enable = 1; 164 else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE) 165 pdata->rss_enable = 0; 166 else 167 return -1; 168 return 0; 169 } 170 171 static int 172 axgbe_dev_start(struct rte_eth_dev *dev) 173 { 174 struct axgbe_port *pdata = dev->data->dev_private; 175 int ret; 176 177 PMD_INIT_FUNC_TRACE(); 178 179 /* Multiqueue RSS */ 180 ret = axgbe_dev_rx_mq_config(dev); 181 if (ret) { 182 PMD_DRV_LOG(ERR, "Unable to config RX MQ\n"); 183 return ret; 184 } 185 ret = axgbe_phy_reset(pdata); 186 if (ret) { 187 PMD_DRV_LOG(ERR, "phy reset failed\n"); 188 return ret; 189 } 190 ret = pdata->hw_if.init(pdata); 191 if (ret) { 192 PMD_DRV_LOG(ERR, "dev_init failed\n"); 193 return ret; 194 } 195 196 /* enable uio/vfio intr/eventfd mapping */ 197 rte_intr_enable(&pdata->pci_dev->intr_handle); 198 199 /* phy start*/ 200 pdata->phy_if.phy_start(pdata); 201 axgbe_dev_enable_tx(dev); 202 axgbe_dev_enable_rx(dev); 203 204 axgbe_clear_bit(AXGBE_STOPPED, &pdata->dev_state); 205 axgbe_clear_bit(AXGBE_DOWN, &pdata->dev_state); 206 return 0; 207 } 208 209 /* Stop device: disable rx and tx functions to allow for reconfiguring. */ 210 static void 211 axgbe_dev_stop(struct rte_eth_dev *dev) 212 { 213 struct axgbe_port *pdata = dev->data->dev_private; 214 215 PMD_INIT_FUNC_TRACE(); 216 217 rte_intr_disable(&pdata->pci_dev->intr_handle); 218 219 if (axgbe_test_bit(AXGBE_STOPPED, &pdata->dev_state)) 220 return; 221 222 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); 223 axgbe_dev_disable_tx(dev); 224 axgbe_dev_disable_rx(dev); 225 226 pdata->phy_if.phy_stop(pdata); 227 pdata->hw_if.exit(pdata); 228 memset(&dev->data->dev_link, 0, sizeof(struct rte_eth_link)); 229 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); 230 } 231 232 /* Clear all resources like TX/RX queues. */ 233 static void 234 axgbe_dev_close(struct rte_eth_dev *dev) 235 { 236 axgbe_dev_clear_queues(dev); 237 } 238 239 static void 240 axgbe_dev_promiscuous_enable(struct rte_eth_dev *dev) 241 { 242 struct axgbe_port *pdata = dev->data->dev_private; 243 244 PMD_INIT_FUNC_TRACE(); 245 246 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1); 247 } 248 249 static void 250 axgbe_dev_promiscuous_disable(struct rte_eth_dev *dev) 251 { 252 struct axgbe_port *pdata = dev->data->dev_private; 253 254 PMD_INIT_FUNC_TRACE(); 255 256 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0); 257 } 258 259 static void 260 axgbe_dev_allmulticast_enable(struct rte_eth_dev *dev) 261 { 262 struct axgbe_port *pdata = dev->data->dev_private; 263 264 PMD_INIT_FUNC_TRACE(); 265 266 if (AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 267 return; 268 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 1); 269 } 270 271 static void 272 axgbe_dev_allmulticast_disable(struct rte_eth_dev *dev) 273 { 274 struct axgbe_port *pdata = dev->data->dev_private; 275 276 PMD_INIT_FUNC_TRACE(); 277 278 if (!AXGMAC_IOREAD_BITS(pdata, MAC_PFR, PM)) 279 return; 280 AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, 0); 281 } 282 283 /* return 0 means link status changed, -1 means not changed */ 284 static int 285 axgbe_dev_link_update(struct rte_eth_dev *dev, 286 int wait_to_complete __rte_unused) 287 { 288 struct axgbe_port *pdata = dev->data->dev_private; 289 struct rte_eth_link link; 290 int ret = 0; 291 292 PMD_INIT_FUNC_TRACE(); 293 rte_delay_ms(800); 294 295 pdata->phy_if.phy_status(pdata); 296 297 memset(&link, 0, sizeof(struct rte_eth_link)); 298 link.link_duplex = pdata->phy.duplex; 299 link.link_status = pdata->phy_link; 300 link.link_speed = pdata->phy_speed; 301 link.link_autoneg = !(dev->data->dev_conf.link_speeds & 302 ETH_LINK_SPEED_FIXED); 303 ret = rte_eth_linkstatus_set(dev, &link); 304 if (ret == -1) 305 PMD_DRV_LOG(ERR, "No change in link status\n"); 306 307 return ret; 308 } 309 310 static int 311 axgbe_dev_stats_get(struct rte_eth_dev *dev, 312 struct rte_eth_stats *stats) 313 { 314 struct axgbe_rx_queue *rxq; 315 struct axgbe_tx_queue *txq; 316 unsigned int i; 317 318 for (i = 0; i < dev->data->nb_rx_queues; i++) { 319 rxq = dev->data->rx_queues[i]; 320 stats->q_ipackets[i] = rxq->pkts; 321 stats->ipackets += rxq->pkts; 322 stats->q_ibytes[i] = rxq->bytes; 323 stats->ibytes += rxq->bytes; 324 } 325 for (i = 0; i < dev->data->nb_tx_queues; i++) { 326 txq = dev->data->tx_queues[i]; 327 stats->q_opackets[i] = txq->pkts; 328 stats->opackets += txq->pkts; 329 stats->q_obytes[i] = txq->bytes; 330 stats->obytes += txq->bytes; 331 } 332 333 return 0; 334 } 335 336 static void 337 axgbe_dev_stats_reset(struct rte_eth_dev *dev) 338 { 339 struct axgbe_rx_queue *rxq; 340 struct axgbe_tx_queue *txq; 341 unsigned int i; 342 343 for (i = 0; i < dev->data->nb_rx_queues; i++) { 344 rxq = dev->data->rx_queues[i]; 345 rxq->pkts = 0; 346 rxq->bytes = 0; 347 rxq->errors = 0; 348 } 349 for (i = 0; i < dev->data->nb_tx_queues; i++) { 350 txq = dev->data->tx_queues[i]; 351 txq->pkts = 0; 352 txq->bytes = 0; 353 txq->errors = 0; 354 } 355 } 356 357 static int 358 axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 359 { 360 struct axgbe_port *pdata = dev->data->dev_private; 361 362 dev_info->max_rx_queues = pdata->rx_ring_count; 363 dev_info->max_tx_queues = pdata->tx_ring_count; 364 dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; 365 dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; 366 dev_info->max_mac_addrs = AXGBE_MAX_MAC_ADDRS; 367 dev_info->speed_capa = ETH_LINK_SPEED_10G; 368 369 dev_info->rx_offload_capa = 370 DEV_RX_OFFLOAD_IPV4_CKSUM | 371 DEV_RX_OFFLOAD_UDP_CKSUM | 372 DEV_RX_OFFLOAD_TCP_CKSUM | 373 DEV_RX_OFFLOAD_KEEP_CRC; 374 375 dev_info->tx_offload_capa = 376 DEV_TX_OFFLOAD_IPV4_CKSUM | 377 DEV_TX_OFFLOAD_UDP_CKSUM | 378 DEV_TX_OFFLOAD_TCP_CKSUM; 379 380 if (pdata->hw_feat.rss) { 381 dev_info->flow_type_rss_offloads = AXGBE_RSS_OFFLOAD; 382 dev_info->reta_size = pdata->hw_feat.hash_table_size; 383 dev_info->hash_key_size = AXGBE_RSS_HASH_KEY_SIZE; 384 } 385 386 dev_info->rx_desc_lim = rx_desc_lim; 387 dev_info->tx_desc_lim = tx_desc_lim; 388 389 dev_info->default_rxconf = (struct rte_eth_rxconf) { 390 .rx_free_thresh = AXGBE_RX_FREE_THRESH, 391 }; 392 393 dev_info->default_txconf = (struct rte_eth_txconf) { 394 .tx_free_thresh = AXGBE_TX_FREE_THRESH, 395 }; 396 397 return 0; 398 } 399 400 static void axgbe_get_all_hw_features(struct axgbe_port *pdata) 401 { 402 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 403 struct axgbe_hw_features *hw_feat = &pdata->hw_feat; 404 405 mac_hfr0 = AXGMAC_IOREAD(pdata, MAC_HWF0R); 406 mac_hfr1 = AXGMAC_IOREAD(pdata, MAC_HWF1R); 407 mac_hfr2 = AXGMAC_IOREAD(pdata, MAC_HWF2R); 408 409 memset(hw_feat, 0, sizeof(*hw_feat)); 410 411 hw_feat->version = AXGMAC_IOREAD(pdata, MAC_VR); 412 413 /* Hardware feature register 0 */ 414 hw_feat->gmii = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); 415 hw_feat->vlhash = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH); 416 hw_feat->sma = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL); 417 hw_feat->rwk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL); 418 hw_feat->mgk = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL); 419 hw_feat->mmc = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL); 420 hw_feat->aoe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL); 421 hw_feat->ts = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL); 422 hw_feat->eee = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL); 423 hw_feat->tx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL); 424 hw_feat->rx_coe = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL); 425 hw_feat->addn_mac = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, 426 ADDMACADRSEL); 427 hw_feat->ts_src = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL); 428 hw_feat->sa_vlan_ins = AXGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS); 429 430 /* Hardware feature register 1 */ 431 hw_feat->rx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 432 RXFIFOSIZE); 433 hw_feat->tx_fifo_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 434 TXFIFOSIZE); 435 hw_feat->adv_ts_hi = AXGMAC_GET_BITS(mac_hfr1, 436 MAC_HWF1R, ADVTHWORD); 437 hw_feat->dma_width = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64); 438 hw_feat->dcb = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN); 439 hw_feat->sph = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN); 440 hw_feat->tso = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN); 441 hw_feat->dma_debug = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA); 442 hw_feat->rss = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN); 443 hw_feat->tc_cnt = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC); 444 hw_feat->hash_table_size = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 445 HASHTBLSZ); 446 hw_feat->l3l4_filter_num = AXGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, 447 L3L4FNUM); 448 449 /* Hardware feature register 2 */ 450 hw_feat->rx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT); 451 hw_feat->tx_q_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT); 452 hw_feat->rx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT); 453 hw_feat->tx_ch_cnt = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT); 454 hw_feat->pps_out_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM); 455 hw_feat->aux_snap_num = AXGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, 456 AUXSNAPNUM); 457 458 /* Translate the Hash Table size into actual number */ 459 switch (hw_feat->hash_table_size) { 460 case 0: 461 break; 462 case 1: 463 hw_feat->hash_table_size = 64; 464 break; 465 case 2: 466 hw_feat->hash_table_size = 128; 467 break; 468 case 3: 469 hw_feat->hash_table_size = 256; 470 break; 471 } 472 473 /* Translate the address width setting into actual number */ 474 switch (hw_feat->dma_width) { 475 case 0: 476 hw_feat->dma_width = 32; 477 break; 478 case 1: 479 hw_feat->dma_width = 40; 480 break; 481 case 2: 482 hw_feat->dma_width = 48; 483 break; 484 default: 485 hw_feat->dma_width = 32; 486 } 487 488 /* The Queue, Channel and TC counts are zero based so increment them 489 * to get the actual number 490 */ 491 hw_feat->rx_q_cnt++; 492 hw_feat->tx_q_cnt++; 493 hw_feat->rx_ch_cnt++; 494 hw_feat->tx_ch_cnt++; 495 hw_feat->tc_cnt++; 496 497 /* Translate the fifo sizes into actual numbers */ 498 hw_feat->rx_fifo_size = 1 << (hw_feat->rx_fifo_size + 7); 499 hw_feat->tx_fifo_size = 1 << (hw_feat->tx_fifo_size + 7); 500 } 501 502 static void axgbe_init_all_fptrs(struct axgbe_port *pdata) 503 { 504 axgbe_init_function_ptrs_dev(&pdata->hw_if); 505 axgbe_init_function_ptrs_phy(&pdata->phy_if); 506 axgbe_init_function_ptrs_i2c(&pdata->i2c_if); 507 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if); 508 } 509 510 static void axgbe_set_counts(struct axgbe_port *pdata) 511 { 512 /* Set all the function pointers */ 513 axgbe_init_all_fptrs(pdata); 514 515 /* Populate the hardware features */ 516 axgbe_get_all_hw_features(pdata); 517 518 /* Set default max values if not provided */ 519 if (!pdata->tx_max_channel_count) 520 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt; 521 if (!pdata->rx_max_channel_count) 522 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt; 523 524 if (!pdata->tx_max_q_count) 525 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt; 526 if (!pdata->rx_max_q_count) 527 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt; 528 529 /* Calculate the number of Tx and Rx rings to be created 530 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set 531 * the number of Tx queues to the number of Tx channels 532 * enabled 533 * -Rx (DMA) Channels do not map 1-to-1 so use the actual 534 * number of Rx queues or maximum allowed 535 */ 536 pdata->tx_ring_count = RTE_MIN(pdata->hw_feat.tx_ch_cnt, 537 pdata->tx_max_channel_count); 538 pdata->tx_ring_count = RTE_MIN(pdata->tx_ring_count, 539 pdata->tx_max_q_count); 540 541 pdata->tx_q_count = pdata->tx_ring_count; 542 543 pdata->rx_ring_count = RTE_MIN(pdata->hw_feat.rx_ch_cnt, 544 pdata->rx_max_channel_count); 545 546 pdata->rx_q_count = RTE_MIN(pdata->hw_feat.rx_q_cnt, 547 pdata->rx_max_q_count); 548 } 549 550 static void axgbe_default_config(struct axgbe_port *pdata) 551 { 552 pdata->pblx8 = DMA_PBL_X8_ENABLE; 553 pdata->tx_sf_mode = MTL_TSF_ENABLE; 554 pdata->tx_threshold = MTL_TX_THRESHOLD_64; 555 pdata->tx_pbl = DMA_PBL_32; 556 pdata->tx_osp_mode = DMA_OSP_ENABLE; 557 pdata->rx_sf_mode = MTL_RSF_ENABLE; 558 pdata->rx_threshold = MTL_RX_THRESHOLD_64; 559 pdata->rx_pbl = DMA_PBL_32; 560 pdata->pause_autoneg = 1; 561 pdata->tx_pause = 0; 562 pdata->rx_pause = 0; 563 pdata->phy_speed = SPEED_UNKNOWN; 564 pdata->power_down = 0; 565 } 566 567 /* 568 * It returns 0 on success. 569 */ 570 static int 571 eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) 572 { 573 PMD_INIT_FUNC_TRACE(); 574 struct axgbe_port *pdata; 575 struct rte_pci_device *pci_dev; 576 uint32_t reg, mac_lo, mac_hi; 577 int ret; 578 579 eth_dev->dev_ops = &axgbe_eth_dev_ops; 580 eth_dev->rx_pkt_burst = &axgbe_recv_pkts; 581 582 /* 583 * For secondary processes, we don't initialise any further as primary 584 * has already done this work. 585 */ 586 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 587 return 0; 588 589 pdata = eth_dev->data->dev_private; 590 /* initial state */ 591 axgbe_set_bit(AXGBE_DOWN, &pdata->dev_state); 592 axgbe_set_bit(AXGBE_STOPPED, &pdata->dev_state); 593 pdata->eth_dev = eth_dev; 594 595 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 596 pdata->pci_dev = pci_dev; 597 598 pdata->xgmac_regs = 599 (void *)pci_dev->mem_resource[AXGBE_AXGMAC_BAR].addr; 600 pdata->xprop_regs = (void *)((uint8_t *)pdata->xgmac_regs 601 + AXGBE_MAC_PROP_OFFSET); 602 pdata->xi2c_regs = (void *)((uint8_t *)pdata->xgmac_regs 603 + AXGBE_I2C_CTRL_OFFSET); 604 pdata->xpcs_regs = (void *)pci_dev->mem_resource[AXGBE_XPCS_BAR].addr; 605 606 /* version specific driver data*/ 607 if (pci_dev->id.device_id == AMD_PCI_AXGBE_DEVICE_V2A) 608 pdata->vdata = &axgbe_v2a; 609 else 610 pdata->vdata = &axgbe_v2b; 611 612 /* Configure the PCS indirect addressing support */ 613 reg = XPCS32_IOREAD(pdata, PCS_V2_WINDOW_DEF); 614 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET); 615 pdata->xpcs_window <<= 6; 616 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE); 617 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7); 618 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1; 619 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF; 620 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT; 621 PMD_INIT_LOG(DEBUG, 622 "xpcs window :%x, size :%x, mask :%x ", pdata->xpcs_window, 623 pdata->xpcs_window_size, pdata->xpcs_window_mask); 624 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff); 625 626 /* Retrieve the MAC address */ 627 mac_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO); 628 mac_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI); 629 pdata->mac_addr.addr_bytes[0] = mac_lo & 0xff; 630 pdata->mac_addr.addr_bytes[1] = (mac_lo >> 8) & 0xff; 631 pdata->mac_addr.addr_bytes[2] = (mac_lo >> 16) & 0xff; 632 pdata->mac_addr.addr_bytes[3] = (mac_lo >> 24) & 0xff; 633 pdata->mac_addr.addr_bytes[4] = mac_hi & 0xff; 634 pdata->mac_addr.addr_bytes[5] = (mac_hi >> 8) & 0xff; 635 636 eth_dev->data->mac_addrs = rte_zmalloc("axgbe_mac_addr", 637 RTE_ETHER_ADDR_LEN, 0); 638 if (!eth_dev->data->mac_addrs) { 639 PMD_INIT_LOG(ERR, 640 "Failed to alloc %u bytes needed to store MAC addr tbl", 641 RTE_ETHER_ADDR_LEN); 642 return -ENOMEM; 643 } 644 645 if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) 646 rte_eth_random_addr(pdata->mac_addr.addr_bytes); 647 648 /* Copy the permanent MAC address */ 649 rte_ether_addr_copy(&pdata->mac_addr, ð_dev->data->mac_addrs[0]); 650 651 /* Clock settings */ 652 pdata->sysclk_rate = AXGBE_V2_DMA_CLOCK_FREQ; 653 pdata->ptpclk_rate = AXGBE_V2_PTP_CLOCK_FREQ; 654 655 /* Set the DMA coherency values */ 656 pdata->coherent = 1; 657 pdata->axdomain = AXGBE_DMA_OS_AXDOMAIN; 658 pdata->arcache = AXGBE_DMA_OS_ARCACHE; 659 pdata->awcache = AXGBE_DMA_OS_AWCACHE; 660 661 /* Set the maximum channels and queues */ 662 reg = XP_IOREAD(pdata, XP_PROP_1); 663 pdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA); 664 pdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA); 665 pdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES); 666 pdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES); 667 668 /* Set the hardware channel and queue counts */ 669 axgbe_set_counts(pdata); 670 671 /* Set the maximum fifo amounts */ 672 reg = XP_IOREAD(pdata, XP_PROP_2); 673 pdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE); 674 pdata->tx_max_fifo_size *= 16384; 675 pdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size, 676 pdata->vdata->tx_max_fifo_size); 677 pdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE); 678 pdata->rx_max_fifo_size *= 16384; 679 pdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size, 680 pdata->vdata->rx_max_fifo_size); 681 /* Issue software reset to DMA */ 682 ret = pdata->hw_if.exit(pdata); 683 if (ret) 684 PMD_DRV_LOG(ERR, "hw_if->exit EBUSY error\n"); 685 686 /* Set default configuration data */ 687 axgbe_default_config(pdata); 688 689 /* Set default max values if not provided */ 690 if (!pdata->tx_max_fifo_size) 691 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size; 692 if (!pdata->rx_max_fifo_size) 693 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size; 694 695 pdata->tx_desc_count = AXGBE_MAX_RING_DESC; 696 pdata->rx_desc_count = AXGBE_MAX_RING_DESC; 697 pthread_mutex_init(&pdata->xpcs_mutex, NULL); 698 pthread_mutex_init(&pdata->i2c_mutex, NULL); 699 pthread_mutex_init(&pdata->an_mutex, NULL); 700 pthread_mutex_init(&pdata->phy_mutex, NULL); 701 702 ret = pdata->phy_if.phy_init(pdata); 703 if (ret) { 704 rte_free(eth_dev->data->mac_addrs); 705 eth_dev->data->mac_addrs = NULL; 706 return ret; 707 } 708 709 rte_intr_callback_register(&pci_dev->intr_handle, 710 axgbe_dev_interrupt_handler, 711 (void *)eth_dev); 712 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x", 713 eth_dev->data->port_id, pci_dev->id.vendor_id, 714 pci_dev->id.device_id); 715 716 return 0; 717 } 718 719 static int 720 eth_axgbe_dev_uninit(struct rte_eth_dev *eth_dev) 721 { 722 struct rte_pci_device *pci_dev; 723 724 PMD_INIT_FUNC_TRACE(); 725 726 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 727 return 0; 728 729 pci_dev = RTE_DEV_TO_PCI(eth_dev->device); 730 eth_dev->dev_ops = NULL; 731 eth_dev->rx_pkt_burst = NULL; 732 eth_dev->tx_pkt_burst = NULL; 733 axgbe_dev_clear_queues(eth_dev); 734 735 /* disable uio intr before callback unregister */ 736 rte_intr_disable(&pci_dev->intr_handle); 737 rte_intr_callback_unregister(&pci_dev->intr_handle, 738 axgbe_dev_interrupt_handler, 739 (void *)eth_dev); 740 741 return 0; 742 } 743 744 static int eth_axgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 745 struct rte_pci_device *pci_dev) 746 { 747 return rte_eth_dev_pci_generic_probe(pci_dev, 748 sizeof(struct axgbe_port), eth_axgbe_dev_init); 749 } 750 751 static int eth_axgbe_pci_remove(struct rte_pci_device *pci_dev) 752 { 753 return rte_eth_dev_pci_generic_remove(pci_dev, eth_axgbe_dev_uninit); 754 } 755 756 static struct rte_pci_driver rte_axgbe_pmd = { 757 .id_table = pci_id_axgbe_map, 758 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 759 .probe = eth_axgbe_pci_probe, 760 .remove = eth_axgbe_pci_remove, 761 }; 762 763 RTE_PMD_REGISTER_PCI(net_axgbe, rte_axgbe_pmd); 764 RTE_PMD_REGISTER_PCI_TABLE(net_axgbe, pci_id_axgbe_map); 765 RTE_PMD_REGISTER_KMOD_DEP(net_axgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 766 767 RTE_INIT(axgbe_init_log) 768 { 769 axgbe_logtype_init = rte_log_register("pmd.net.axgbe.init"); 770 if (axgbe_logtype_init >= 0) 771 rte_log_set_level(axgbe_logtype_init, RTE_LOG_NOTICE); 772 axgbe_logtype_driver = rte_log_register("pmd.net.axgbe.driver"); 773 if (axgbe_logtype_driver >= 0) 774 rte_log_set_level(axgbe_logtype_driver, RTE_LOG_NOTICE); 775 } 776