15438e4ecSFan Zhang /* SPDX-License-Identifier: BSD-3-Clause 25438e4ecSFan Zhang * Copyright(c) 2021 Intel Corporation 35438e4ecSFan Zhang */ 45438e4ecSFan Zhang 55438e4ecSFan Zhang #ifndef _QAT_DEV_GENS_H_ 65438e4ecSFan Zhang #define _QAT_DEV_GENS_H_ 75438e4ecSFan Zhang 85438e4ecSFan Zhang #include "qat_device.h" 95438e4ecSFan Zhang #include "qat_qp.h" 105438e4ecSFan Zhang 115438e4ecSFan Zhang #include <stdint.h> 125438e4ecSFan Zhang 135438e4ecSFan Zhang extern const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES] 145438e4ecSFan Zhang [ADF_MAX_QPS_ON_ANY_SERVICE]; 155438e4ecSFan Zhang 165438e4ecSFan Zhang int 175438e4ecSFan Zhang qat_dev_get_extra_size_gen1(void); 185438e4ecSFan Zhang 194c778f1aSFan Zhang const struct qat_qp_hw_data * 204c778f1aSFan Zhang qat_qp_get_hw_data_gen1(struct qat_pci_device *dev, 214c778f1aSFan Zhang enum qat_service_type service_type, uint16_t qp_id); 224c778f1aSFan Zhang 234c778f1aSFan Zhang int 244c778f1aSFan Zhang qat_qp_rings_per_service_gen1(struct qat_pci_device *qat_dev, 254c778f1aSFan Zhang enum qat_service_type service); 264c778f1aSFan Zhang 274c778f1aSFan Zhang void 284c778f1aSFan Zhang qat_qp_csr_build_ring_base_gen1(void *io_addr, 294c778f1aSFan Zhang struct qat_queue *queue); 304c778f1aSFan Zhang 314c778f1aSFan Zhang void 324c778f1aSFan Zhang qat_qp_adf_arb_enable_gen1(const struct qat_queue *txq, 334c778f1aSFan Zhang void *base_addr, rte_spinlock_t *lock); 344c778f1aSFan Zhang 354c778f1aSFan Zhang void 364c778f1aSFan Zhang qat_qp_adf_arb_disable_gen1(const struct qat_queue *txq, 374c778f1aSFan Zhang void *base_addr, rte_spinlock_t *lock); 384c778f1aSFan Zhang 394c778f1aSFan Zhang void 404c778f1aSFan Zhang qat_qp_adf_configure_queues_gen1(struct qat_qp *qp); 414c778f1aSFan Zhang 424c778f1aSFan Zhang void 434c778f1aSFan Zhang qat_qp_csr_write_tail_gen1(struct qat_qp *qp, struct qat_queue *q); 444c778f1aSFan Zhang 454c778f1aSFan Zhang void 464c778f1aSFan Zhang qat_qp_csr_write_head_gen1(struct qat_qp *qp, struct qat_queue *q, 474c778f1aSFan Zhang uint32_t new_head); 484c778f1aSFan Zhang 494c778f1aSFan Zhang void 504c778f1aSFan Zhang qat_qp_csr_setup_gen1(struct qat_pci_device *qat_dev, 514c778f1aSFan Zhang void *io_addr, struct qat_qp *qp); 524c778f1aSFan Zhang 535438e4ecSFan Zhang int 545438e4ecSFan Zhang qat_reset_ring_pairs_gen1( 555438e4ecSFan Zhang struct qat_pci_device *qat_pci_dev); 565438e4ecSFan Zhang const struct 575438e4ecSFan Zhang rte_mem_resource *qat_dev_get_transport_bar_gen1( 585438e4ecSFan Zhang struct rte_pci_device *pci_dev); 595438e4ecSFan Zhang int 605438e4ecSFan Zhang qat_dev_get_misc_bar_gen1(struct rte_mem_resource **mem_resource, 615438e4ecSFan Zhang struct rte_pci_device *pci_dev); 625438e4ecSFan Zhang int 635438e4ecSFan Zhang qat_dev_read_config_gen1(struct qat_pci_device *qat_dev); 645438e4ecSFan Zhang 65*59cda512SCiara Power int 66*59cda512SCiara Power qat_reset_ring_pairs_gen4(struct qat_pci_device *qat_pci_dev); 67*59cda512SCiara Power 68*59cda512SCiara Power const struct rte_mem_resource * 69*59cda512SCiara Power qat_dev_get_transport_bar_gen4(struct rte_pci_device *pci_dev); 70*59cda512SCiara Power 71*59cda512SCiara Power int 72*59cda512SCiara Power qat_dev_get_misc_bar_gen4(struct rte_mem_resource **mem_resource, 73*59cda512SCiara Power struct rte_pci_device *pci_dev); 74*59cda512SCiara Power 75*59cda512SCiara Power int 76*59cda512SCiara Power qat_dev_read_config_gen4(struct qat_pci_device *qat_dev); 77*59cda512SCiara Power 78*59cda512SCiara Power int 79*59cda512SCiara Power qat_dev_get_extra_size_gen4(void); 80*59cda512SCiara Power 81*59cda512SCiara Power int 82*59cda512SCiara Power qat_dev_get_slice_map_gen4(uint32_t *map __rte_unused, 83*59cda512SCiara Power const struct rte_pci_device *pci_dev __rte_unused); 84*59cda512SCiara Power 85*59cda512SCiara Power int 86*59cda512SCiara Power qat_qp_rings_per_service_gen4(struct qat_pci_device *qat_dev, 87*59cda512SCiara Power enum qat_service_type service); 88*59cda512SCiara Power 89*59cda512SCiara Power void 90*59cda512SCiara Power qat_qp_build_ring_base_gen4(void *io_addr, 91*59cda512SCiara Power struct qat_queue *queue); 92*59cda512SCiara Power 93*59cda512SCiara Power void 94*59cda512SCiara Power qat_qp_adf_arb_enable_gen4(const struct qat_queue *txq, 95*59cda512SCiara Power void *base_addr, rte_spinlock_t *lock); 96*59cda512SCiara Power 97*59cda512SCiara Power void 98*59cda512SCiara Power qat_qp_adf_arb_disable_gen4(const struct qat_queue *txq, 99*59cda512SCiara Power void *base_addr, rte_spinlock_t *lock); 100*59cda512SCiara Power 101*59cda512SCiara Power void 102*59cda512SCiara Power qat_qp_adf_configure_queues_gen4(struct qat_qp *qp); 103*59cda512SCiara Power 104*59cda512SCiara Power void 105*59cda512SCiara Power qat_qp_csr_write_tail_gen4(struct qat_qp *qp, struct qat_queue *q); 106*59cda512SCiara Power 107*59cda512SCiara Power void 108*59cda512SCiara Power qat_qp_csr_write_head_gen4(struct qat_qp *qp, struct qat_queue *q, 109*59cda512SCiara Power uint32_t new_head); 110*59cda512SCiara Power 111*59cda512SCiara Power void 112*59cda512SCiara Power qat_qp_csr_setup_gen4(struct qat_pci_device *qat_dev, 113*59cda512SCiara Power void *io_addr, struct qat_qp *qp); 114*59cda512SCiara Power 115*59cda512SCiara Power const struct qat_qp_hw_data * 116*59cda512SCiara Power qat_qp_get_hw_data_gen4(struct qat_pci_device *qat_dev, 117*59cda512SCiara Power enum qat_service_type service_type, uint16_t qp_id); 118*59cda512SCiara Power 1195438e4ecSFan Zhang #endif 120