xref: /dpdk/drivers/common/cnxk/hw/tim.h (revision f3c7b60769f997be0c49788d7bfc515c59910f83)
1fa8f86a1SJerin Jacob /* SPDX-License-Identifier: BSD-3-Clause
2fa8f86a1SJerin Jacob  * Copyright(C) 2021 Marvell.
3fa8f86a1SJerin Jacob  */
4fa8f86a1SJerin Jacob 
5fa8f86a1SJerin Jacob #ifndef __TIM_HW_H__
6fa8f86a1SJerin Jacob #define __TIM_HW_H__
7fa8f86a1SJerin Jacob 
8fa8f86a1SJerin Jacob /* TIM */
9fa8f86a1SJerin Jacob #define TIM_AF_CONST		   (0x90)
10fa8f86a1SJerin Jacob #define TIM_PRIV_LFX_CFG(a)	   (0x20000 | (a) << 3)
11fa8f86a1SJerin Jacob #define TIM_PRIV_LFX_INT_CFG(a)	   (0x24000 | (a) << 3)
12fa8f86a1SJerin Jacob #define TIM_AF_RVU_LF_CFG_DEBUG	   (0x30000)
13fa8f86a1SJerin Jacob #define TIM_AF_BLK_RST		   (0x10)
14fa8f86a1SJerin Jacob #define TIM_AF_LF_RST		   (0x20)
15fa8f86a1SJerin Jacob #define TIM_AF_BLK_RST		   (0x10)
16fa8f86a1SJerin Jacob #define TIM_AF_RINGX_GMCTL(a)	   (0x2000 | (a) << 3)
17fa8f86a1SJerin Jacob #define TIM_AF_RINGX_CTL0(a)	   (0x4000 | (a) << 3)
18fa8f86a1SJerin Jacob #define TIM_AF_RINGX_CTL1(a)	   (0x6000 | (a) << 3)
19fa8f86a1SJerin Jacob #define TIM_AF_RINGX_CTL2(a)	   (0x8000 | (a) << 3)
20fa8f86a1SJerin Jacob #define TIM_AF_FLAGS_REG	   (0x80)
21fa8f86a1SJerin Jacob #define TIM_AF_FLAGS_REG_ENA_TIM   BIT_ULL(0)
22fa8f86a1SJerin Jacob #define TIM_AF_RINGX_CTL1_ENA	   BIT_ULL(47)
23fa8f86a1SJerin Jacob #define TIM_AF_RINGX_CTL1_RCF_BUSY BIT_ULL(50)
24fa8f86a1SJerin Jacob #define TIM_AF_RINGX_CLT1_CLK_10NS (0)
25fa8f86a1SJerin Jacob #define TIM_AF_RINGX_CLT1_CLK_GPIO (1)
26fa8f86a1SJerin Jacob #define TIM_AF_RINGX_CLT1_CLK_GTI  (2)
27fa8f86a1SJerin Jacob #define TIM_AF_RINGX_CLT1_CLK_PTP  (3)
28fa8f86a1SJerin Jacob 
29fa8f86a1SJerin Jacob /* ENUMS */
30fa8f86a1SJerin Jacob 
31fa8f86a1SJerin Jacob #define TIM_LF_INT_VEC_NRSPERR_INT (0x0ull)
32fa8f86a1SJerin Jacob #define TIM_LF_INT_VEC_RAS_INT	   (0x1ull)
33fa8f86a1SJerin Jacob #define TIM_LF_RING_AURA	   (0x0)
34a6d13f59SPavan Nikhilesh #define TIM_LF_FR_RN_GPIOS	   (0x020)
35a6d13f59SPavan Nikhilesh #define TIM_LF_FR_RN_GTI	   (0x030)
36a6d13f59SPavan Nikhilesh #define TIM_LF_FR_RN_PTP	   (0x040)
37a6d13f59SPavan Nikhilesh #define TIM_LF_FR_RN_TENNS	   (0x050)
38a6d13f59SPavan Nikhilesh #define TIM_LF_FR_RN_SYNCE	   (0x060)
39a6d13f59SPavan Nikhilesh #define TIM_LF_FR_RN_BTS	   (0x070)
40fa8f86a1SJerin Jacob #define TIM_LF_RING_BASE	   (0x130)
41fa8f86a1SJerin Jacob #define TIM_LF_NRSPERR_INT	   (0x200)
42fa8f86a1SJerin Jacob #define TIM_LF_NRSPERR_INT_W1S	   (0x208)
43fa8f86a1SJerin Jacob #define TIM_LF_NRSPERR_INT_ENA_W1S (0x210)
44fa8f86a1SJerin Jacob #define TIM_LF_NRSPERR_INT_ENA_W1C (0x218)
45fa8f86a1SJerin Jacob #define TIM_LF_RAS_INT		   (0x300)
46fa8f86a1SJerin Jacob #define TIM_LF_RAS_INT_W1S	   (0x308)
47fa8f86a1SJerin Jacob #define TIM_LF_RAS_INT_ENA_W1S	   (0x310)
48fa8f86a1SJerin Jacob #define TIM_LF_RAS_INT_ENA_W1C	   (0x318)
49fa8f86a1SJerin Jacob #define TIM_LF_RING_REL		   (0x400)
50*f3c7b607SPavan Nikhilesh #define TIM_LF_SCHED_TIMER0	   (0x480)
51*f3c7b607SPavan Nikhilesh #define TIM_LF_RING_FIRST_EXPIRY   (0x558)
52fa8f86a1SJerin Jacob 
53fa8f86a1SJerin Jacob #define TIM_MAX_INTERVAL_TICKS ((1ULL << 32) - 1)
54*f3c7b607SPavan Nikhilesh #define TIM_MAX_INTERVAL_EXT_TICKS ((1ULL << 34) - 1)
5537a94462SPavan Nikhilesh #define TIM_MAX_BUCKET_SIZE    ((1ULL << 20) - 2)
5637a94462SPavan Nikhilesh #define TIM_MIN_BUCKET_SIZE    1
5737a94462SPavan Nikhilesh #define TIM_BUCKET_WRAP_SIZE   3
58*f3c7b607SPavan Nikhilesh #define TIM_BUCKET_MIN_GAP     1
59*f3c7b607SPavan Nikhilesh #define TIM_NPA_TMO            0xFFFF
60fa8f86a1SJerin Jacob 
61fa8f86a1SJerin Jacob #endif /* __TIM_HW_H__ */
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