1efd45369SNicolas Chautru /* SPDX-License-Identifier: BSD-3-Clause 2efd45369SNicolas Chautru * Copyright(c) 2019 Intel Corporation 3efd45369SNicolas Chautru */ 4efd45369SNicolas Chautru 5efd45369SNicolas Chautru #ifndef _FPGA_LTE_FEC_H_ 6efd45369SNicolas Chautru #define _FPGA_LTE_FEC_H_ 7efd45369SNicolas Chautru 8efd45369SNicolas Chautru #include <stdint.h> 9efd45369SNicolas Chautru #include <stdbool.h> 10efd45369SNicolas Chautru 11*1094dd94SDavid Marchand #include <rte_compat.h> 12*1094dd94SDavid Marchand 13efd45369SNicolas Chautru /** 14efd45369SNicolas Chautru * @file fpga_lte_fec.h 15efd45369SNicolas Chautru * 16efd45369SNicolas Chautru * Interface for Intel(R) FGPA LTE FEC device configuration at the host level, 17efd45369SNicolas Chautru * directly accessible by the application. 18efd45369SNicolas Chautru * Configuration related to LTE Turbo coding functionality is done through 19efd45369SNicolas Chautru * librte_bbdev library. 20efd45369SNicolas Chautru * 21efd45369SNicolas Chautru * @warning 22efd45369SNicolas Chautru * @b EXPERIMENTAL: this API may change without prior notice 23efd45369SNicolas Chautru */ 24efd45369SNicolas Chautru 25efd45369SNicolas Chautru #ifdef __cplusplus 26efd45369SNicolas Chautru extern "C" { 27efd45369SNicolas Chautru #endif 28efd45369SNicolas Chautru 29efd45369SNicolas Chautru /**< Number of Virtual Functions FGPA 4G FEC supports */ 30efd45369SNicolas Chautru #define FPGA_LTE_FEC_NUM_VFS 8 31efd45369SNicolas Chautru 32efd45369SNicolas Chautru /** 33efd45369SNicolas Chautru * Structure to pass FPGA 4G FEC configuration. 34efd45369SNicolas Chautru */ 35e6925585SMaxime Coquelin struct rte_fpga_lte_fec_conf { 36efd45369SNicolas Chautru /**< 1 if PF is used for dataplane, 0 for VFs */ 37efd45369SNicolas Chautru bool pf_mode_en; 38efd45369SNicolas Chautru /**< Number of UL queues per VF */ 39efd45369SNicolas Chautru uint8_t vf_ul_queues_number[FPGA_LTE_FEC_NUM_VFS]; 40efd45369SNicolas Chautru /**< Number of DL queues per VF */ 41efd45369SNicolas Chautru uint8_t vf_dl_queues_number[FPGA_LTE_FEC_NUM_VFS]; 42efd45369SNicolas Chautru /**< UL bandwidth. Needed for schedule algorithm */ 43efd45369SNicolas Chautru uint8_t ul_bandwidth; 44efd45369SNicolas Chautru /**< DL bandwidth. Needed for schedule algorithm */ 45efd45369SNicolas Chautru uint8_t dl_bandwidth; 46efd45369SNicolas Chautru /**< UL Load Balance */ 47efd45369SNicolas Chautru uint8_t ul_load_balance; 48efd45369SNicolas Chautru /**< DL Load Balance */ 49efd45369SNicolas Chautru uint8_t dl_load_balance; 50efd45369SNicolas Chautru /**< FLR timeout value */ 51efd45369SNicolas Chautru uint16_t flr_time_out; 52efd45369SNicolas Chautru }; 53efd45369SNicolas Chautru 54efd45369SNicolas Chautru /** 55efd45369SNicolas Chautru * Configure Intel(R) FPGA LTE FEC device 56efd45369SNicolas Chautru * 57efd45369SNicolas Chautru * @param dev_name 58efd45369SNicolas Chautru * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0. 59efd45369SNicolas Chautru * It can also be retrieved for a bbdev device from the dev_name field in the 60efd45369SNicolas Chautru * rte_bbdev_info structure returned by rte_bbdev_info_get(). 61efd45369SNicolas Chautru * @param conf 62efd45369SNicolas Chautru * Configuration to apply to FPGA 4G FEC. 63efd45369SNicolas Chautru * 64efd45369SNicolas Chautru * @return 65efd45369SNicolas Chautru * Zero on success, negative value on failure. 66efd45369SNicolas Chautru */ 6744f45300SBruce Richardson __rte_experimental 68efd45369SNicolas Chautru int 69e6925585SMaxime Coquelin rte_fpga_lte_fec_configure(const char *dev_name, 70e6925585SMaxime Coquelin const struct rte_fpga_lte_fec_conf *conf); 71efd45369SNicolas Chautru 72efd45369SNicolas Chautru #ifdef __cplusplus 73efd45369SNicolas Chautru } 74efd45369SNicolas Chautru #endif 75efd45369SNicolas Chautru 76efd45369SNicolas Chautru #endif /* _FPGA_LTE_FEC_H_ */ 77