1*fc1f2750SBernard Iremonger.. BSD LICENSE 2*fc1f2750SBernard Iremonger Copyright(c) 2010-2014 Intel Corporation. All rights reserved. 3*fc1f2750SBernard Iremonger All rights reserved. 4*fc1f2750SBernard Iremonger 5*fc1f2750SBernard Iremonger Redistribution and use in source and binary forms, with or without 6*fc1f2750SBernard Iremonger modification, are permitted provided that the following conditions 7*fc1f2750SBernard Iremonger are met: 8*fc1f2750SBernard Iremonger 9*fc1f2750SBernard Iremonger * Redistributions of source code must retain the above copyright 10*fc1f2750SBernard Iremonger notice, this list of conditions and the following disclaimer. 11*fc1f2750SBernard Iremonger * Redistributions in binary form must reproduce the above copyright 12*fc1f2750SBernard Iremonger notice, this list of conditions and the following disclaimer in 13*fc1f2750SBernard Iremonger the documentation and/or other materials provided with the 14*fc1f2750SBernard Iremonger distribution. 15*fc1f2750SBernard Iremonger * Neither the name of Intel Corporation nor the names of its 16*fc1f2750SBernard Iremonger contributors may be used to endorse or promote products derived 17*fc1f2750SBernard Iremonger from this software without specific prior written permission. 18*fc1f2750SBernard Iremonger 19*fc1f2750SBernard Iremonger THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20*fc1f2750SBernard Iremonger "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21*fc1f2750SBernard Iremonger LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 22*fc1f2750SBernard Iremonger A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 23*fc1f2750SBernard Iremonger OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24*fc1f2750SBernard Iremonger SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25*fc1f2750SBernard Iremonger LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26*fc1f2750SBernard Iremonger DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27*fc1f2750SBernard Iremonger THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28*fc1f2750SBernard Iremonger (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29*fc1f2750SBernard Iremonger OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30*fc1f2750SBernard Iremonger 31*fc1f2750SBernard Iremonger.. _Timer_Library: 32*fc1f2750SBernard Iremonger 33*fc1f2750SBernard IremongerTimer Library 34*fc1f2750SBernard Iremonger============= 35*fc1f2750SBernard Iremonger 36*fc1f2750SBernard IremongerThe Timer library provides a timer service to Intel® DPDK execution units to enable execution of callback functions asynchronously. 37*fc1f2750SBernard IremongerFeatures of the library are: 38*fc1f2750SBernard Iremonger 39*fc1f2750SBernard Iremonger* Timers can be periodic (multi-shot) or single (one-shot). 40*fc1f2750SBernard Iremonger 41*fc1f2750SBernard Iremonger* Timers can be loaded from one core and executed on another. It has to be specified in the call to rte_timer_reset(). 42*fc1f2750SBernard Iremonger 43*fc1f2750SBernard Iremonger* Timers provide high precision (depends on the call frequency to rte_timer_manage() that checks timer expiration for the local core). 44*fc1f2750SBernard Iremonger 45*fc1f2750SBernard Iremonger* If not required in the application, timers can be disabled at compilation time by not calling the rte_timer_manage() to increase performance. 46*fc1f2750SBernard Iremonger 47*fc1f2750SBernard IremongerThe timer library uses the rte_get_timer_cycles() function that uses the High Precision Event Timer (HPET) 48*fc1f2750SBernard Iremongeror the CPUs Time Stamp Counter (TSC) to provide a reliable time reference. 49*fc1f2750SBernard Iremonger 50*fc1f2750SBernard IremongerThis library provides an interface to add, delete and restart a timer. The API is based on BSD callout() with a few differences. 51*fc1f2750SBernard IremongerRefer to the `callout manual <http://www.daemon-systems.org/man/callout.9.html>`_. 52*fc1f2750SBernard Iremonger 53*fc1f2750SBernard IremongerImplementation Details 54*fc1f2750SBernard Iremonger---------------------- 55*fc1f2750SBernard Iremonger 56*fc1f2750SBernard IremongerTimers are tracked on a per-lcore basis, 57*fc1f2750SBernard Iremongerwith all pending timers for a core being maintained in order of timer expiry in a skiplist data structure. 58*fc1f2750SBernard IremongerThe skiplist used has ten levels and each entry in the table appears in each level with probability ¼^level. 59*fc1f2750SBernard IremongerThis means that all entries are present in level 0, 1 in every 4 entries is present at level 1, 60*fc1f2750SBernard Iremongerone in every 16 at level 2 and so on up to level 9. 61*fc1f2750SBernard IremongerThis means that adding and removing entries from the timer list for a core can be done in log(n) time, 62*fc1f2750SBernard Iremongerup to 4^10 entries, that is, approximately 1,000,000 timers per lcore. 63*fc1f2750SBernard Iremonger 64*fc1f2750SBernard IremongerA timer structure contains a special field called status, 65*fc1f2750SBernard Iremongerwhich is a union of a timer state (stopped, pending, running, config) and an owner (lcore id). 66*fc1f2750SBernard IremongerDepending on the timer state, we know if a timer is present in a list or not: 67*fc1f2750SBernard Iremonger 68*fc1f2750SBernard Iremonger* STOPPED: no owner, not in a list 69*fc1f2750SBernard Iremonger 70*fc1f2750SBernard Iremonger* CONFIG: owned by a core, must not be modified by another core, maybe in a list or not, depending on previous state 71*fc1f2750SBernard Iremonger 72*fc1f2750SBernard Iremonger* PENDING: owned by a core, present in a list 73*fc1f2750SBernard Iremonger 74*fc1f2750SBernard Iremonger* RUNNING: owned by a core, must not be modified by another core, present in a list 75*fc1f2750SBernard Iremonger 76*fc1f2750SBernard IremongerResetting or stopping a timer while it is in a CONFIG or RUNNING state is not allowed. 77*fc1f2750SBernard IremongerWhen modifying the state of a timer, 78*fc1f2750SBernard Iremongera Compare And Swap instruction should be used to guarantee that the status (state+owner) is modified atomically. 79*fc1f2750SBernard Iremonger 80*fc1f2750SBernard IremongerInside the rte_timer_manage() function, 81*fc1f2750SBernard Iremongerthe skiplist is used as a regular list by iterating along the level 0 list, which contains all timer entries, 82*fc1f2750SBernard Iremongeruntil an entry which has not yet expired has been encountered. 83*fc1f2750SBernard IremongerTo improve performance in the case where there are entries in the timer list but none of those timers have yet expired, 84*fc1f2750SBernard Iremongerthe expiry time of the first list entry is maintained within the per-core timer list structure itself. 85*fc1f2750SBernard IremongerOn 64-bit platforms, this value can be checked without the need to take a lock on the overall structure. 86*fc1f2750SBernard Iremonger(Since expiry times are maintained as 64-bit values, 87*fc1f2750SBernard Iremongera check on the value cannot be done on 32-bit platforms without using either a compare-and-swap (CAS) instruction or using a lock, 88*fc1f2750SBernard Iremongerso this additional check is skipped in favour of checking as normal once the lock has been taken.) 89*fc1f2750SBernard IremongerOn both 64-bit and 32-bit platforms, 90*fc1f2750SBernard Iremongera call to rte_timer_manage() returns without taking a lock in the case where the timer list for the calling core is empty. 91*fc1f2750SBernard Iremonger 92*fc1f2750SBernard IremongerUse Cases 93*fc1f2750SBernard Iremonger--------- 94*fc1f2750SBernard Iremonger 95*fc1f2750SBernard IremongerThe timer library is used for periodic calls, such as garbage collectors, or some state machines (ARP, bridging, and so on). 96*fc1f2750SBernard Iremonger 97*fc1f2750SBernard IremongerReferences 98*fc1f2750SBernard Iremonger---------- 99*fc1f2750SBernard Iremonger 100*fc1f2750SBernard Iremonger* `callout manual <http://www.daemon-systems.org/man/callout.9.html>`_ 101*fc1f2750SBernard Iremonger - The callout facility that provides timers with a mechanism to execute a function at a given time. 102*fc1f2750SBernard Iremonger 103*fc1f2750SBernard Iremonger* `HPET <http://en.wikipedia.org/wiki/HPET>`_ 104*fc1f2750SBernard Iremonger - Information about the High Precision Event Timer (HPET). 105