1*fd501800SSascha Wildner /*- 2*fd501800SSascha Wildner * Copyright (c) 2012-2015 LSI Corp. 3*fd501800SSascha Wildner * Copyright (c) 2013-2016 Avago Technologies 4*fd501800SSascha Wildner * All rights reserved. 5*fd501800SSascha Wildner * 6*fd501800SSascha Wildner * Redistribution and use in source and binary forms, with or without 7*fd501800SSascha Wildner * modification, are permitted provided that the following conditions 8*fd501800SSascha Wildner * are met: 9*fd501800SSascha Wildner * 1. Redistributions of source code must retain the above copyright 10*fd501800SSascha Wildner * notice, this list of conditions and the following disclaimer. 11*fd501800SSascha Wildner * 2. Redistributions in binary form must reproduce the above copyright 12*fd501800SSascha Wildner * notice, this list of conditions and the following disclaimer in the 13*fd501800SSascha Wildner * documentation and/or other materials provided with the distribution. 14*fd501800SSascha Wildner * 3. Neither the name of the author nor the names of any co-contributors 15*fd501800SSascha Wildner * may be used to endorse or promote products derived from this software 16*fd501800SSascha Wildner * without specific prior written permission. 17*fd501800SSascha Wildner * 18*fd501800SSascha Wildner * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19*fd501800SSascha Wildner * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*fd501800SSascha Wildner * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*fd501800SSascha Wildner * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22*fd501800SSascha Wildner * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23*fd501800SSascha Wildner * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24*fd501800SSascha Wildner * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25*fd501800SSascha Wildner * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26*fd501800SSascha Wildner * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27*fd501800SSascha Wildner * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28*fd501800SSascha Wildner * SUCH DAMAGE. 29*fd501800SSascha Wildner * 30*fd501800SSascha Wildner * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 31*fd501800SSascha Wildner * 32*fd501800SSascha Wildner * $FreeBSD: head/sys/dev/mpr/mpi/mpi2_ra.h 299263 2016-05-09 16:12:32Z slm $ 33*fd501800SSascha Wildner */ 34*fd501800SSascha Wildner 35*fd501800SSascha Wildner /* 36*fd501800SSascha Wildner * Copyright (c) 2012-2015 LSI Corporation. 37*fd501800SSascha Wildner * Copyright (c) 2013-2016 Avago Technologies 38*fd501800SSascha Wildner * All rights reserved. 39*fd501800SSascha Wildner * 40*fd501800SSascha Wildner * 41*fd501800SSascha Wildner * Name: mpi2_ra.h 42*fd501800SSascha Wildner * Title: MPI RAID Accelerator messages and structures 43*fd501800SSascha Wildner * Creation Date: April 13, 2009 44*fd501800SSascha Wildner * 45*fd501800SSascha Wildner * mpi2_ra.h Version: 02.00.01 46*fd501800SSascha Wildner * 47*fd501800SSascha Wildner * Version History 48*fd501800SSascha Wildner * --------------- 49*fd501800SSascha Wildner * 50*fd501800SSascha Wildner * Date Version Description 51*fd501800SSascha Wildner * -------- -------- ------------------------------------------------------ 52*fd501800SSascha Wildner * 05-06-09 02.00.00 Initial version. 53*fd501800SSascha Wildner * 11-18-14 02.00.01 Updated copyright information. 54*fd501800SSascha Wildner * -------------------------------------------------------------------------- 55*fd501800SSascha Wildner */ 56*fd501800SSascha Wildner 57*fd501800SSascha Wildner #ifndef MPI2_RA_H 58*fd501800SSascha Wildner #define MPI2_RA_H 59*fd501800SSascha Wildner 60*fd501800SSascha Wildner /* generic structure for RAID Accelerator Control Block */ 61*fd501800SSascha Wildner typedef struct _MPI2_RAID_ACCELERATOR_CONTROL_BLOCK 62*fd501800SSascha Wildner { 63*fd501800SSascha Wildner U32 Reserved[8]; /* 0x00 */ 64*fd501800SSascha Wildner U32 RaidAcceleratorCDB[1]; /* 0x20 */ 65*fd501800SSascha Wildner } MPI2_RAID_ACCELERATOR_CONTROL_BLOCK, 66*fd501800SSascha Wildner MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_CONTROL_BLOCK, 67*fd501800SSascha Wildner Mpi2RAIDAcceleratorControlBlock_t, 68*fd501800SSascha Wildner MPI2_POINTER pMpi2RAIDAcceleratorControlBlock_t; 69*fd501800SSascha Wildner 70*fd501800SSascha Wildner 71*fd501800SSascha Wildner /****************************************************************************** 72*fd501800SSascha Wildner * 73*fd501800SSascha Wildner * RAID Accelerator Messages 74*fd501800SSascha Wildner * 75*fd501800SSascha Wildner *******************************************************************************/ 76*fd501800SSascha Wildner 77*fd501800SSascha Wildner /* RAID Accelerator Request Message */ 78*fd501800SSascha Wildner typedef struct _MPI2_RAID_ACCELERATOR_REQUEST 79*fd501800SSascha Wildner { 80*fd501800SSascha Wildner U16 Reserved0; /* 0x00 */ 81*fd501800SSascha Wildner U8 ChainOffset; /* 0x02 */ 82*fd501800SSascha Wildner U8 Function; /* 0x03 */ 83*fd501800SSascha Wildner U16 Reserved1; /* 0x04 */ 84*fd501800SSascha Wildner U8 Reserved2; /* 0x06 */ 85*fd501800SSascha Wildner U8 MsgFlags; /* 0x07 */ 86*fd501800SSascha Wildner U8 VP_ID; /* 0x08 */ 87*fd501800SSascha Wildner U8 VF_ID; /* 0x09 */ 88*fd501800SSascha Wildner U16 Reserved3; /* 0x0A */ 89*fd501800SSascha Wildner U64 RaidAcceleratorControlBlockAddress; /* 0x0C */ 90*fd501800SSascha Wildner U8 DmaEngineNumber; /* 0x14 */ 91*fd501800SSascha Wildner U8 Reserved4; /* 0x15 */ 92*fd501800SSascha Wildner U16 Reserved5; /* 0x16 */ 93*fd501800SSascha Wildner U32 Reserved6; /* 0x18 */ 94*fd501800SSascha Wildner U32 Reserved7; /* 0x1C */ 95*fd501800SSascha Wildner U32 Reserved8; /* 0x20 */ 96*fd501800SSascha Wildner } MPI2_RAID_ACCELERATOR_REQUEST, MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_REQUEST, 97*fd501800SSascha Wildner Mpi2RAIDAcceleratorRequest_t, MPI2_POINTER pMpi2RAIDAcceleratorRequest_t; 98*fd501800SSascha Wildner 99*fd501800SSascha Wildner 100*fd501800SSascha Wildner /* RAID Accelerator Error Reply Message */ 101*fd501800SSascha Wildner typedef struct _MPI2_RAID_ACCELERATOR_REPLY 102*fd501800SSascha Wildner { 103*fd501800SSascha Wildner U16 Reserved0; /* 0x00 */ 104*fd501800SSascha Wildner U8 MsgLength; /* 0x02 */ 105*fd501800SSascha Wildner U8 Function; /* 0x03 */ 106*fd501800SSascha Wildner U16 Reserved1; /* 0x04 */ 107*fd501800SSascha Wildner U8 Reserved2; /* 0x06 */ 108*fd501800SSascha Wildner U8 MsgFlags; /* 0x07 */ 109*fd501800SSascha Wildner U8 VP_ID; /* 0x08 */ 110*fd501800SSascha Wildner U8 VF_ID; /* 0x09 */ 111*fd501800SSascha Wildner U16 Reserved3; /* 0x0A */ 112*fd501800SSascha Wildner U16 Reserved4; /* 0x0C */ 113*fd501800SSascha Wildner U16 IOCStatus; /* 0x0E */ 114*fd501800SSascha Wildner U32 IOCLogInfo; /* 0x10 */ 115*fd501800SSascha Wildner U32 ProductSpecificData[3]; /* 0x14 */ 116*fd501800SSascha Wildner } MPI2_RAID_ACCELERATOR_REPLY, MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_REPLY, 117*fd501800SSascha Wildner Mpi2RAIDAcceleratorReply_t, MPI2_POINTER pMpi2RAIDAcceleratorReply_t; 118*fd501800SSascha Wildner 119*fd501800SSascha Wildner 120*fd501800SSascha Wildner #endif 121*fd501800SSascha Wildner 122*fd501800SSascha Wildner 123