xref: /dflybsd-src/sys/dev/drm/i915/intel_dsi.h (revision a85cb24f18e3804e75ab8bcda7692564d0563317)
19edbd4a0SFrançois Tigeot /*
29edbd4a0SFrançois Tigeot  * Copyright © 2013 Intel Corporation
39edbd4a0SFrançois Tigeot  *
49edbd4a0SFrançois Tigeot  * Permission is hereby granted, free of charge, to any person obtaining a
59edbd4a0SFrançois Tigeot  * copy of this software and associated documentation files (the "Software"),
69edbd4a0SFrançois Tigeot  * to deal in the Software without restriction, including without limitation
79edbd4a0SFrançois Tigeot  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
89edbd4a0SFrançois Tigeot  * and/or sell copies of the Software, and to permit persons to whom the
99edbd4a0SFrançois Tigeot  * Software is furnished to do so, subject to the following conditions:
109edbd4a0SFrançois Tigeot  *
119edbd4a0SFrançois Tigeot  * The above copyright notice and this permission notice (including the next
129edbd4a0SFrançois Tigeot  * paragraph) shall be included in all copies or substantial portions of the
139edbd4a0SFrançois Tigeot  * Software.
149edbd4a0SFrançois Tigeot  *
159edbd4a0SFrançois Tigeot  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
169edbd4a0SFrançois Tigeot  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
179edbd4a0SFrançois Tigeot  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
189edbd4a0SFrançois Tigeot  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
199edbd4a0SFrançois Tigeot  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
209edbd4a0SFrançois Tigeot  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
219edbd4a0SFrançois Tigeot  * DEALINGS IN THE SOFTWARE.
229edbd4a0SFrançois Tigeot  */
239edbd4a0SFrançois Tigeot 
249edbd4a0SFrançois Tigeot #ifndef _INTEL_DSI_H
259edbd4a0SFrançois Tigeot #define _INTEL_DSI_H
269edbd4a0SFrançois Tigeot 
279edbd4a0SFrançois Tigeot #include <drm/drmP.h>
289edbd4a0SFrançois Tigeot #include <drm/drm_crtc.h>
292c9916cdSFrançois Tigeot #include <drm/drm_mipi_dsi.h>
309edbd4a0SFrançois Tigeot #include "intel_drv.h"
319edbd4a0SFrançois Tigeot 
322c9916cdSFrançois Tigeot /* Dual Link support */
332c9916cdSFrançois Tigeot #define DSI_DUAL_LINK_NONE		0
342c9916cdSFrançois Tigeot #define DSI_DUAL_LINK_FRONT_BACK	1
352c9916cdSFrançois Tigeot #define DSI_DUAL_LINK_PIXEL_ALT		2
369edbd4a0SFrançois Tigeot 
372c9916cdSFrançois Tigeot struct intel_dsi_host;
389edbd4a0SFrançois Tigeot 
399edbd4a0SFrançois Tigeot struct intel_dsi {
409edbd4a0SFrançois Tigeot 	struct intel_encoder base;
419edbd4a0SFrançois Tigeot 
422c9916cdSFrançois Tigeot 	struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
439edbd4a0SFrançois Tigeot 
44a05eeebfSFrançois Tigeot 	/* GPIO Desc for CRC based Panel control */
45a05eeebfSFrançois Tigeot 	struct gpio_desc *gpio_panel;
46a05eeebfSFrançois Tigeot 
479edbd4a0SFrançois Tigeot 	struct intel_connector *attached_connector;
489edbd4a0SFrançois Tigeot 
492c9916cdSFrançois Tigeot 	/* bit mask of ports being driven */
502c9916cdSFrançois Tigeot 	u16 ports;
512c9916cdSFrançois Tigeot 
529edbd4a0SFrançois Tigeot 	/* if true, use HS mode, otherwise LP */
539edbd4a0SFrançois Tigeot 	bool hs;
549edbd4a0SFrançois Tigeot 
559edbd4a0SFrançois Tigeot 	/* virtual channel */
569edbd4a0SFrançois Tigeot 	int channel;
579edbd4a0SFrançois Tigeot 
58ba55f2f5SFrançois Tigeot 	/* Video mode or command mode */
59ba55f2f5SFrançois Tigeot 	u16 operation_mode;
60ba55f2f5SFrançois Tigeot 
619edbd4a0SFrançois Tigeot 	/* number of DSI lanes */
629edbd4a0SFrançois Tigeot 	unsigned int lane_count;
639edbd4a0SFrançois Tigeot 
648621f407SFrançois Tigeot 	/*
658621f407SFrançois Tigeot 	 * video mode pixel format
668621f407SFrançois Tigeot 	 *
678621f407SFrançois Tigeot 	 * XXX: consolidate on .format in struct mipi_dsi_device.
688621f407SFrançois Tigeot 	 */
698621f407SFrançois Tigeot 	enum mipi_dsi_pixel_format pixel_format;
709edbd4a0SFrançois Tigeot 
719edbd4a0SFrançois Tigeot 	/* video mode format for MIPI_VIDEO_MODE_FORMAT register */
729edbd4a0SFrançois Tigeot 	u32 video_mode_format;
739edbd4a0SFrançois Tigeot 
749edbd4a0SFrançois Tigeot 	/* eot for MIPI_EOT_DISABLE register */
75ba55f2f5SFrançois Tigeot 	u8 eotp_pkt;
76ba55f2f5SFrançois Tigeot 	u8 clock_stop;
779edbd4a0SFrançois Tigeot 
78ba55f2f5SFrançois Tigeot 	u8 escape_clk_div;
792c9916cdSFrançois Tigeot 	u8 dual_link;
801487f786SFrançois Tigeot 
811487f786SFrançois Tigeot 	u16 dcs_backlight_ports;
821487f786SFrançois Tigeot 	u16 dcs_cabc_ports;
831487f786SFrançois Tigeot 
842c9916cdSFrançois Tigeot 	u8 pixel_overlap;
859edbd4a0SFrançois Tigeot 	u32 port_bits;
869edbd4a0SFrançois Tigeot 	u32 bw_timer;
879edbd4a0SFrançois Tigeot 	u32 dphy_reg;
889edbd4a0SFrançois Tigeot 	u32 video_frmt_cfg_bits;
899edbd4a0SFrançois Tigeot 	u16 lp_byte_clk;
909edbd4a0SFrançois Tigeot 
919edbd4a0SFrançois Tigeot 	/* timeouts in byte clocks */
929edbd4a0SFrançois Tigeot 	u16 lp_rx_timeout;
939edbd4a0SFrançois Tigeot 	u16 turn_arnd_val;
949edbd4a0SFrançois Tigeot 	u16 rst_timer_val;
959edbd4a0SFrançois Tigeot 	u16 hs_to_lp_count;
969edbd4a0SFrançois Tigeot 	u16 clk_lp_to_hs_count;
979edbd4a0SFrançois Tigeot 	u16 clk_hs_to_lp_count;
98ba55f2f5SFrançois Tigeot 
99ba55f2f5SFrançois Tigeot 	u16 init_count;
1001b13d190SFrançois Tigeot 	u32 pclk;
1011b13d190SFrançois Tigeot 	u16 burst_mode_ratio;
102ba55f2f5SFrançois Tigeot 
103ba55f2f5SFrançois Tigeot 	/* all delays in ms */
104ba55f2f5SFrançois Tigeot 	u16 backlight_off_delay;
105ba55f2f5SFrançois Tigeot 	u16 backlight_on_delay;
106ba55f2f5SFrançois Tigeot 	u16 panel_on_delay;
107ba55f2f5SFrançois Tigeot 	u16 panel_off_delay;
108ba55f2f5SFrançois Tigeot 	u16 panel_pwr_cycle_delay;
1099edbd4a0SFrançois Tigeot };
1109edbd4a0SFrançois Tigeot 
1112c9916cdSFrançois Tigeot struct intel_dsi_host {
1122c9916cdSFrançois Tigeot 	struct mipi_dsi_host base;
1132c9916cdSFrançois Tigeot 	struct intel_dsi *intel_dsi;
1142c9916cdSFrançois Tigeot 	enum port port;
1152c9916cdSFrançois Tigeot 
1162c9916cdSFrançois Tigeot 	/* our little hack */
1172c9916cdSFrançois Tigeot 	struct mipi_dsi_device *device;
1182c9916cdSFrançois Tigeot };
1192c9916cdSFrançois Tigeot 
to_intel_dsi_host(struct mipi_dsi_host * h)1202c9916cdSFrançois Tigeot static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
1212c9916cdSFrançois Tigeot {
1222c9916cdSFrançois Tigeot 	return container_of(h, struct intel_dsi_host, base);
1232c9916cdSFrançois Tigeot }
1242c9916cdSFrançois Tigeot 
1258621f407SFrançois Tigeot #define for_each_dsi_port(__port, __ports_mask) for_each_port_masked(__port, __ports_mask)
1262c9916cdSFrançois Tigeot 
enc_to_intel_dsi(struct drm_encoder * encoder)1279edbd4a0SFrançois Tigeot static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
1289edbd4a0SFrançois Tigeot {
1299edbd4a0SFrançois Tigeot 	return container_of(encoder, struct intel_dsi, base.base);
1309edbd4a0SFrançois Tigeot }
1319edbd4a0SFrançois Tigeot 
132*a85cb24fSFrançois Tigeot /* intel_dsi.c */
133*a85cb24fSFrançois Tigeot void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
134*a85cb24fSFrançois Tigeot enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
135*a85cb24fSFrançois Tigeot 
136*a85cb24fSFrançois Tigeot /* intel_dsi_pll.c */
1378621f407SFrançois Tigeot bool intel_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
1388621f407SFrançois Tigeot int intel_compute_dsi_pll(struct intel_encoder *encoder,
1398621f407SFrançois Tigeot 			  struct intel_crtc_state *config);
1408621f407SFrançois Tigeot void intel_enable_dsi_pll(struct intel_encoder *encoder,
1418621f407SFrançois Tigeot 			  const struct intel_crtc_state *config);
1428621f407SFrançois Tigeot void intel_disable_dsi_pll(struct intel_encoder *encoder);
1438621f407SFrançois Tigeot u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp,
1448621f407SFrançois Tigeot 		       struct intel_crtc_state *config);
1458621f407SFrançois Tigeot void intel_dsi_reset_clocks(struct intel_encoder *encoder,
146352ff8bdSFrançois Tigeot 			    enum port port);
1479edbd4a0SFrançois Tigeot 
148*a85cb24fSFrançois Tigeot /* intel_dsi_vbt.c */
149*a85cb24fSFrançois Tigeot bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
150*a85cb24fSFrançois Tigeot int intel_dsi_vbt_get_modes(struct intel_dsi *intel_dsi);
151*a85cb24fSFrançois Tigeot void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
152*a85cb24fSFrançois Tigeot 				 enum mipi_seq seq_id);
153ba55f2f5SFrançois Tigeot 
1549edbd4a0SFrançois Tigeot #endif /* _INTEL_DSI_H */
155