xref: /dflybsd-src/sys/dev/drm/amd/include/amd_pcie.h (revision b843c749addef9340ee7d4e250b09fdd492602a1)
1d78d3a22SFrançois Tigeot /*
2d78d3a22SFrançois Tigeot  * Copyright 2015 Advanced Micro Devices, Inc.
3d78d3a22SFrançois Tigeot  *
4d78d3a22SFrançois Tigeot  * Permission is hereby granted, free of charge, to any person obtaining a
5d78d3a22SFrançois Tigeot  * copy of this software and associated documentation files (the "Software"),
6d78d3a22SFrançois Tigeot  * to deal in the Software without restriction, including without limitation
7d78d3a22SFrançois Tigeot  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8d78d3a22SFrançois Tigeot  * and/or sell copies of the Software, and to permit persons to whom the
9d78d3a22SFrançois Tigeot  * Software is furnished to do so, subject to the following conditions:
10d78d3a22SFrançois Tigeot  *
11d78d3a22SFrançois Tigeot  * The above copyright notice and this permission notice shall be included in
12d78d3a22SFrançois Tigeot  * all copies or substantial portions of the Software.
13d78d3a22SFrançois Tigeot  *
14d78d3a22SFrançois Tigeot  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15d78d3a22SFrançois Tigeot  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16d78d3a22SFrançois Tigeot  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17d78d3a22SFrançois Tigeot  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18d78d3a22SFrançois Tigeot  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19d78d3a22SFrançois Tigeot  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20d78d3a22SFrançois Tigeot  * OTHER DEALINGS IN THE SOFTWARE.
21d78d3a22SFrançois Tigeot  */
22d78d3a22SFrançois Tigeot 
23d78d3a22SFrançois Tigeot #ifndef __AMD_PCIE_H__
24d78d3a22SFrançois Tigeot #define __AMD_PCIE_H__
25d78d3a22SFrançois Tigeot 
26d78d3a22SFrançois Tigeot /* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
27d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
28d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
29d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
30*b843c749SSergey Zigachev #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4        0x00080000
31d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
32d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
33d78d3a22SFrançois Tigeot 
34d78d3a22SFrançois Tigeot /* Following flags shows PCIe link speed supported by ASIC H/W.*/
35d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
36d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
37d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
38*b843c749SSergey Zigachev #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4   0x00000008
39d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
40d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
41d78d3a22SFrançois Tigeot 
42*b843c749SSergey Zigachev /* gen: chipset 1/2, asic 1/2/3 */
43*b843c749SSergey Zigachev #define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \
44*b843c749SSergey Zigachev 				      | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \
45*b843c749SSergey Zigachev 				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \
46*b843c749SSergey Zigachev 				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \
47*b843c749SSergey Zigachev 				      | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3)
48*b843c749SSergey Zigachev 
49d78d3a22SFrançois Tigeot /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
50d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
51d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
52d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
53d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
54d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
55d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
56d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
57d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
58d78d3a22SFrançois Tigeot 
59*b843c749SSergey Zigachev /* 1/2/4/8/16 lanes */
60*b843c749SSergey Zigachev #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \
61*b843c749SSergey Zigachev 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \
62*b843c749SSergey Zigachev 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \
63*b843c749SSergey Zigachev 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \
64*b843c749SSergey Zigachev 				      | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
65*b843c749SSergey Zigachev 
66d78d3a22SFrançois Tigeot #endif
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