xref: /dflybsd-src/sys/dev/drm/amd/display/dc/gpio/hw_gpio.h (revision b843c749addef9340ee7d4e250b09fdd492602a1)
1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev  * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev  *
4*b843c749SSergey Zigachev  * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev  * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev  * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev  * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev  * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev  *
11*b843c749SSergey Zigachev  * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev  * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev  *
14*b843c749SSergey Zigachev  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*b843c749SSergey Zigachev  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev  * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev  *
22*b843c749SSergey Zigachev  * Authors: AMD
23*b843c749SSergey Zigachev  *
24*b843c749SSergey Zigachev  */
25*b843c749SSergey Zigachev 
26*b843c749SSergey Zigachev #ifndef __DAL_HW_GPIO_H__
27*b843c749SSergey Zigachev #define __DAL_HW_GPIO_H__
28*b843c749SSergey Zigachev 
29*b843c749SSergey Zigachev #include "gpio_regs.h"
30*b843c749SSergey Zigachev 
31*b843c749SSergey Zigachev #define FROM_HW_GPIO_PIN(ptr) \
32*b843c749SSergey Zigachev 	container_of((ptr), struct hw_gpio, base)
33*b843c749SSergey Zigachev 
34*b843c749SSergey Zigachev struct addr_mask {
35*b843c749SSergey Zigachev 	uint32_t addr;
36*b843c749SSergey Zigachev 	uint32_t mask;
37*b843c749SSergey Zigachev };
38*b843c749SSergey Zigachev 
39*b843c749SSergey Zigachev struct hw_gpio_pin {
40*b843c749SSergey Zigachev 	const struct hw_gpio_pin_funcs *funcs;
41*b843c749SSergey Zigachev 	enum gpio_id id;
42*b843c749SSergey Zigachev 	uint32_t en;
43*b843c749SSergey Zigachev 	enum gpio_mode mode;
44*b843c749SSergey Zigachev 	bool opened;
45*b843c749SSergey Zigachev 	struct dc_context *ctx;
46*b843c749SSergey Zigachev };
47*b843c749SSergey Zigachev 
48*b843c749SSergey Zigachev struct hw_gpio_pin_funcs {
49*b843c749SSergey Zigachev 	void (*destroy)(
50*b843c749SSergey Zigachev 		struct hw_gpio_pin **ptr);
51*b843c749SSergey Zigachev 	bool (*open)(
52*b843c749SSergey Zigachev 		struct hw_gpio_pin *pin,
53*b843c749SSergey Zigachev 		enum gpio_mode mode);
54*b843c749SSergey Zigachev 	enum gpio_result (*get_value)(
55*b843c749SSergey Zigachev 		const struct hw_gpio_pin *pin,
56*b843c749SSergey Zigachev 		uint32_t *value);
57*b843c749SSergey Zigachev 	enum gpio_result (*set_value)(
58*b843c749SSergey Zigachev 		const struct hw_gpio_pin *pin,
59*b843c749SSergey Zigachev 		uint32_t value);
60*b843c749SSergey Zigachev 	enum gpio_result (*set_config)(
61*b843c749SSergey Zigachev 		struct hw_gpio_pin *pin,
62*b843c749SSergey Zigachev 		const struct gpio_config_data *config_data);
63*b843c749SSergey Zigachev 	enum gpio_result (*change_mode)(
64*b843c749SSergey Zigachev 		struct hw_gpio_pin *pin,
65*b843c749SSergey Zigachev 		enum gpio_mode mode);
66*b843c749SSergey Zigachev 	void (*close)(
67*b843c749SSergey Zigachev 		struct hw_gpio_pin *pin);
68*b843c749SSergey Zigachev };
69*b843c749SSergey Zigachev 
70*b843c749SSergey Zigachev 
71*b843c749SSergey Zigachev struct hw_gpio;
72*b843c749SSergey Zigachev 
73*b843c749SSergey Zigachev /* Register indices are represented by member variables
74*b843c749SSergey Zigachev  * and are to be filled in by constructors of derived classes.
75*b843c749SSergey Zigachev  * These members permit the use of common code
76*b843c749SSergey Zigachev  * for programming registers, where the sequence is the same
77*b843c749SSergey Zigachev  * but register sets are different.
78*b843c749SSergey Zigachev  * Some GPIOs have HW mux which allows to choose
79*b843c749SSergey Zigachev  * what is the source of the signal in HW mode */
80*b843c749SSergey Zigachev 
81*b843c749SSergey Zigachev struct hw_gpio_pin_reg {
82*b843c749SSergey Zigachev 	struct addr_mask DC_GPIO_DATA_MASK;
83*b843c749SSergey Zigachev 	struct addr_mask DC_GPIO_DATA_A;
84*b843c749SSergey Zigachev 	struct addr_mask DC_GPIO_DATA_EN;
85*b843c749SSergey Zigachev 	struct addr_mask DC_GPIO_DATA_Y;
86*b843c749SSergey Zigachev };
87*b843c749SSergey Zigachev 
88*b843c749SSergey Zigachev struct hw_gpio_mux_reg {
89*b843c749SSergey Zigachev 	struct addr_mask GPIO_MUX_CONTROL;
90*b843c749SSergey Zigachev 	struct addr_mask GPIO_MUX_STEREO_SEL;
91*b843c749SSergey Zigachev };
92*b843c749SSergey Zigachev 
93*b843c749SSergey Zigachev struct hw_gpio {
94*b843c749SSergey Zigachev 	struct hw_gpio_pin base;
95*b843c749SSergey Zigachev 
96*b843c749SSergey Zigachev 	/* variables to save register value */
97*b843c749SSergey Zigachev 	struct {
98*b843c749SSergey Zigachev 		uint32_t mask;
99*b843c749SSergey Zigachev 		uint32_t a;
100*b843c749SSergey Zigachev 		uint32_t en;
101*b843c749SSergey Zigachev 		uint32_t mux;
102*b843c749SSergey Zigachev 	} store;
103*b843c749SSergey Zigachev 
104*b843c749SSergey Zigachev 	/* GPIO MUX support */
105*b843c749SSergey Zigachev 	bool mux_supported;
106*b843c749SSergey Zigachev 	const struct gpio_registers *regs;
107*b843c749SSergey Zigachev };
108*b843c749SSergey Zigachev 
109*b843c749SSergey Zigachev #define HW_GPIO_FROM_BASE(hw_gpio_pin) \
110*b843c749SSergey Zigachev 	container_of((hw_gpio_pin), struct hw_gpio, base)
111*b843c749SSergey Zigachev 
112*b843c749SSergey Zigachev void dal_hw_gpio_construct(
113*b843c749SSergey Zigachev 	struct hw_gpio *pin,
114*b843c749SSergey Zigachev 	enum gpio_id id,
115*b843c749SSergey Zigachev 	uint32_t en,
116*b843c749SSergey Zigachev 	struct dc_context *ctx);
117*b843c749SSergey Zigachev 
118*b843c749SSergey Zigachev bool dal_hw_gpio_open(
119*b843c749SSergey Zigachev 	struct hw_gpio_pin *pin,
120*b843c749SSergey Zigachev 	enum gpio_mode mode);
121*b843c749SSergey Zigachev 
122*b843c749SSergey Zigachev enum gpio_result dal_hw_gpio_get_value(
123*b843c749SSergey Zigachev 	const struct hw_gpio_pin *pin,
124*b843c749SSergey Zigachev 	uint32_t *value);
125*b843c749SSergey Zigachev 
126*b843c749SSergey Zigachev enum gpio_result dal_hw_gpio_config_mode(
127*b843c749SSergey Zigachev 	struct hw_gpio *pin,
128*b843c749SSergey Zigachev 	enum gpio_mode mode);
129*b843c749SSergey Zigachev 
130*b843c749SSergey Zigachev void dal_hw_gpio_destruct(
131*b843c749SSergey Zigachev 	struct hw_gpio *pin);
132*b843c749SSergey Zigachev 
133*b843c749SSergey Zigachev enum gpio_result dal_hw_gpio_set_value(
134*b843c749SSergey Zigachev 	const struct hw_gpio_pin *ptr,
135*b843c749SSergey Zigachev 	uint32_t value);
136*b843c749SSergey Zigachev 
137*b843c749SSergey Zigachev enum gpio_result dal_hw_gpio_change_mode(
138*b843c749SSergey Zigachev 	struct hw_gpio_pin *ptr,
139*b843c749SSergey Zigachev 	enum gpio_mode mode);
140*b843c749SSergey Zigachev 
141*b843c749SSergey Zigachev void dal_hw_gpio_close(
142*b843c749SSergey Zigachev 	struct hw_gpio_pin *ptr);
143*b843c749SSergey Zigachev 
144*b843c749SSergey Zigachev #endif
145