1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef __DAL_AUX_ENGINE_DCE110_H__ 27*b843c749SSergey Zigachev #define __DAL_AUX_ENGINE_DCE110_H__ 28*b843c749SSergey Zigachev #include "aux_engine.h" 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define AUX_COMMON_REG_LIST(id)\ 31*b843c749SSergey Zigachev SRI(AUX_CONTROL, DP_AUX, id), \ 32*b843c749SSergey Zigachev SRI(AUX_ARB_CONTROL, DP_AUX, id), \ 33*b843c749SSergey Zigachev SRI(AUX_SW_DATA, DP_AUX, id), \ 34*b843c749SSergey Zigachev SRI(AUX_SW_CONTROL, DP_AUX, id), \ 35*b843c749SSergey Zigachev SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \ 36*b843c749SSergey Zigachev SRI(AUX_SW_STATUS, DP_AUX, id), \ 37*b843c749SSergey Zigachev SR(AUXN_IMPCAL), \ 38*b843c749SSergey Zigachev SR(AUXP_IMPCAL) 39*b843c749SSergey Zigachev 40*b843c749SSergey Zigachev struct dce110_aux_registers { 41*b843c749SSergey Zigachev uint32_t AUX_CONTROL; 42*b843c749SSergey Zigachev uint32_t AUX_ARB_CONTROL; 43*b843c749SSergey Zigachev uint32_t AUX_SW_DATA; 44*b843c749SSergey Zigachev uint32_t AUX_SW_CONTROL; 45*b843c749SSergey Zigachev uint32_t AUX_INTERRUPT_CONTROL; 46*b843c749SSergey Zigachev uint32_t AUX_SW_STATUS; 47*b843c749SSergey Zigachev uint32_t AUXN_IMPCAL; 48*b843c749SSergey Zigachev uint32_t AUXP_IMPCAL; 49*b843c749SSergey Zigachev 50*b843c749SSergey Zigachev uint32_t AUX_RESET_MASK; 51*b843c749SSergey Zigachev }; 52*b843c749SSergey Zigachev 53*b843c749SSergey Zigachev enum { /* This is the timeout as defined in DP 1.2a, 54*b843c749SSergey Zigachev * 2.3.4 "Detailed uPacket TX AUX CH State Description". 55*b843c749SSergey Zigachev */ 56*b843c749SSergey Zigachev AUX_TIMEOUT_PERIOD = 400, 57*b843c749SSergey Zigachev 58*b843c749SSergey Zigachev /* Ideally, the SW timeout should be just above 550usec 59*b843c749SSergey Zigachev * which is programmed in HW. 60*b843c749SSergey Zigachev * But the SW timeout of 600usec is not reliable, 61*b843c749SSergey Zigachev * because on some systems, delay_in_microseconds() 62*b843c749SSergey Zigachev * returns faster than it should. 63*b843c749SSergey Zigachev * EPR #379763: by trial-and-error on different systems, 64*b843c749SSergey Zigachev * 700usec is the minimum reliable SW timeout for polling 65*b843c749SSergey Zigachev * the AUX_SW_STATUS.AUX_SW_DONE bit. 66*b843c749SSergey Zigachev * This timeout expires *only* when there is 67*b843c749SSergey Zigachev * AUX Error or AUX Timeout conditions - not during normal operation. 68*b843c749SSergey Zigachev * During normal operation, AUX_SW_STATUS.AUX_SW_DONE bit is set 69*b843c749SSergey Zigachev * at most within ~240usec. That means, 70*b843c749SSergey Zigachev * increasing this timeout will not affect normal operation, 71*b843c749SSergey Zigachev * and we'll timeout after 72*b843c749SSergey Zigachev * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD = 2400usec. 73*b843c749SSergey Zigachev * This timeout is especially important for 74*b843c749SSergey Zigachev * converters, resume from S3, and CTS. 75*b843c749SSergey Zigachev */ 76*b843c749SSergey Zigachev SW_AUX_TIMEOUT_PERIOD_MULTIPLIER = 6 77*b843c749SSergey Zigachev }; 78*b843c749SSergey Zigachev struct aux_engine_dce110 { 79*b843c749SSergey Zigachev struct aux_engine base; 80*b843c749SSergey Zigachev const struct dce110_aux_registers *regs; 81*b843c749SSergey Zigachev struct { 82*b843c749SSergey Zigachev uint32_t aux_control; 83*b843c749SSergey Zigachev uint32_t aux_arb_control; 84*b843c749SSergey Zigachev uint32_t aux_sw_data; 85*b843c749SSergey Zigachev uint32_t aux_sw_control; 86*b843c749SSergey Zigachev uint32_t aux_interrupt_control; 87*b843c749SSergey Zigachev uint32_t aux_sw_status; 88*b843c749SSergey Zigachev } addr; 89*b843c749SSergey Zigachev uint32_t timeout_period; 90*b843c749SSergey Zigachev }; 91*b843c749SSergey Zigachev 92*b843c749SSergey Zigachev struct aux_engine_dce110_init_data { 93*b843c749SSergey Zigachev uint32_t engine_id; 94*b843c749SSergey Zigachev uint32_t timeout_period; 95*b843c749SSergey Zigachev struct dc_context *ctx; 96*b843c749SSergey Zigachev const struct dce110_aux_registers *regs; 97*b843c749SSergey Zigachev }; 98*b843c749SSergey Zigachev 99*b843c749SSergey Zigachev struct aux_engine *dce110_aux_engine_construct( 100*b843c749SSergey Zigachev struct aux_engine_dce110 *aux_engine110, 101*b843c749SSergey Zigachev struct dc_context *ctx, 102*b843c749SSergey Zigachev uint32_t inst, 103*b843c749SSergey Zigachev uint32_t timeout_period, 104*b843c749SSergey Zigachev const struct dce110_aux_registers *regs); 105*b843c749SSergey Zigachev 106*b843c749SSergey Zigachev void dce110_engine_destroy(struct aux_engine **engine); 107*b843c749SSergey Zigachev 108*b843c749SSergey Zigachev bool dce110_aux_engine_acquire( 109*b843c749SSergey Zigachev struct aux_engine *aux_engine, 110*b843c749SSergey Zigachev struct ddc *ddc); 111*b843c749SSergey Zigachev #endif 112