1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2017 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev */ 22*b843c749SSergey Zigachev 23*b843c749SSergey Zigachev #ifndef __MXGPU_VI_H__ 24*b843c749SSergey Zigachev #define __MXGPU_VI_H__ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #define VI_MAILBOX_TIMEDOUT 12000 27*b843c749SSergey Zigachev #define VI_MAILBOX_RESET_TIME 12 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev /* VI mailbox messages request */ 30*b843c749SSergey Zigachev enum idh_request { 31*b843c749SSergey Zigachev IDH_REQ_GPU_INIT_ACCESS = 1, 32*b843c749SSergey Zigachev IDH_REL_GPU_INIT_ACCESS, 33*b843c749SSergey Zigachev IDH_REQ_GPU_FINI_ACCESS, 34*b843c749SSergey Zigachev IDH_REL_GPU_FINI_ACCESS, 35*b843c749SSergey Zigachev IDH_REQ_GPU_RESET_ACCESS, 36*b843c749SSergey Zigachev 37*b843c749SSergey Zigachev IDH_LOG_VF_ERROR = 200, 38*b843c749SSergey Zigachev }; 39*b843c749SSergey Zigachev 40*b843c749SSergey Zigachev /* VI mailbox messages data */ 41*b843c749SSergey Zigachev enum idh_event { 42*b843c749SSergey Zigachev IDH_CLR_MSG_BUF = 0, 43*b843c749SSergey Zigachev IDH_READY_TO_ACCESS_GPU, 44*b843c749SSergey Zigachev IDH_FLR_NOTIFICATION, 45*b843c749SSergey Zigachev IDH_FLR_NOTIFICATION_CMPL, 46*b843c749SSergey Zigachev IDH_EVENT_MAX 47*b843c749SSergey Zigachev }; 48*b843c749SSergey Zigachev 49*b843c749SSergey Zigachev extern const struct amdgpu_virt_ops xgpu_vi_virt_ops; 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev void xgpu_vi_init_golden_registers(struct amdgpu_device *adev); 52*b843c749SSergey Zigachev void xgpu_vi_mailbox_set_irq_funcs(struct amdgpu_device *adev); 53*b843c749SSergey Zigachev int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev); 54*b843c749SSergey Zigachev int xgpu_vi_mailbox_get_irq(struct amdgpu_device *adev); 55*b843c749SSergey Zigachev void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev); 56*b843c749SSergey Zigachev 57*b843c749SSergey Zigachev #endif 58