1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2018 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev */
23*b843c749SSergey Zigachev #include "amdgpu.h"
24*b843c749SSergey Zigachev #include "df_v3_6.h"
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "df/df_3_6_default.h"
27*b843c749SSergey Zigachev #include "df/df_3_6_offset.h"
28*b843c749SSergey Zigachev #include "df/df_3_6_sh_mask.h"
29*b843c749SSergey Zigachev
30*b843c749SSergey Zigachev static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0,
31*b843c749SSergey Zigachev 16, 32, 0, 0, 0, 2, 4, 8};
32*b843c749SSergey Zigachev
df_v3_6_init(struct amdgpu_device * adev)33*b843c749SSergey Zigachev static void df_v3_6_init(struct amdgpu_device *adev)
34*b843c749SSergey Zigachev {
35*b843c749SSergey Zigachev }
36*b843c749SSergey Zigachev
df_v3_6_enable_broadcast_mode(struct amdgpu_device * adev,bool enable)37*b843c749SSergey Zigachev static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev,
38*b843c749SSergey Zigachev bool enable)
39*b843c749SSergey Zigachev {
40*b843c749SSergey Zigachev u32 tmp;
41*b843c749SSergey Zigachev
42*b843c749SSergey Zigachev if (enable) {
43*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
44*b843c749SSergey Zigachev tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
45*b843c749SSergey Zigachev WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
46*b843c749SSergey Zigachev } else
47*b843c749SSergey Zigachev WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
48*b843c749SSergey Zigachev mmFabricConfigAccessControl_DEFAULT);
49*b843c749SSergey Zigachev }
50*b843c749SSergey Zigachev
df_v3_6_get_fb_channel_number(struct amdgpu_device * adev)51*b843c749SSergey Zigachev static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev)
52*b843c749SSergey Zigachev {
53*b843c749SSergey Zigachev u32 tmp;
54*b843c749SSergey Zigachev
55*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0);
56*b843c749SSergey Zigachev tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK;
57*b843c749SSergey Zigachev tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
58*b843c749SSergey Zigachev
59*b843c749SSergey Zigachev return tmp;
60*b843c749SSergey Zigachev }
61*b843c749SSergey Zigachev
df_v3_6_get_hbm_channel_number(struct amdgpu_device * adev)62*b843c749SSergey Zigachev static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev)
63*b843c749SSergey Zigachev {
64*b843c749SSergey Zigachev int fb_channel_number;
65*b843c749SSergey Zigachev
66*b843c749SSergey Zigachev fb_channel_number = adev->df_funcs->get_fb_channel_number(adev);
67*b843c749SSergey Zigachev if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number))
68*b843c749SSergey Zigachev fb_channel_number = 0;
69*b843c749SSergey Zigachev
70*b843c749SSergey Zigachev return df_v3_6_channel_number[fb_channel_number];
71*b843c749SSergey Zigachev }
72*b843c749SSergey Zigachev
df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)73*b843c749SSergey Zigachev static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev,
74*b843c749SSergey Zigachev bool enable)
75*b843c749SSergey Zigachev {
76*b843c749SSergey Zigachev u32 tmp;
77*b843c749SSergey Zigachev
78*b843c749SSergey Zigachev if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) {
79*b843c749SSergey Zigachev /* Put DF on broadcast mode */
80*b843c749SSergey Zigachev adev->df_funcs->enable_broadcast_mode(adev, true);
81*b843c749SSergey Zigachev
82*b843c749SSergey Zigachev if (enable) {
83*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0,
84*b843c749SSergey Zigachev mmDF_PIE_AON0_DfGlobalClkGater);
85*b843c749SSergey Zigachev tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
86*b843c749SSergey Zigachev tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY;
87*b843c749SSergey Zigachev WREG32_SOC15(DF, 0,
88*b843c749SSergey Zigachev mmDF_PIE_AON0_DfGlobalClkGater, tmp);
89*b843c749SSergey Zigachev } else {
90*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0,
91*b843c749SSergey Zigachev mmDF_PIE_AON0_DfGlobalClkGater);
92*b843c749SSergey Zigachev tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
93*b843c749SSergey Zigachev tmp |= DF_V3_6_MGCG_DISABLE;
94*b843c749SSergey Zigachev WREG32_SOC15(DF, 0,
95*b843c749SSergey Zigachev mmDF_PIE_AON0_DfGlobalClkGater, tmp);
96*b843c749SSergey Zigachev }
97*b843c749SSergey Zigachev
98*b843c749SSergey Zigachev /* Exit broadcast mode */
99*b843c749SSergey Zigachev adev->df_funcs->enable_broadcast_mode(adev, false);
100*b843c749SSergey Zigachev }
101*b843c749SSergey Zigachev }
102*b843c749SSergey Zigachev
df_v3_6_get_clockgating_state(struct amdgpu_device * adev,u32 * flags)103*b843c749SSergey Zigachev static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev,
104*b843c749SSergey Zigachev u32 *flags)
105*b843c749SSergey Zigachev {
106*b843c749SSergey Zigachev u32 tmp;
107*b843c749SSergey Zigachev
108*b843c749SSergey Zigachev /* AMD_CG_SUPPORT_DF_MGCG */
109*b843c749SSergey Zigachev tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
110*b843c749SSergey Zigachev if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY)
111*b843c749SSergey Zigachev *flags |= AMD_CG_SUPPORT_DF_MGCG;
112*b843c749SSergey Zigachev }
113*b843c749SSergey Zigachev
114*b843c749SSergey Zigachev const struct amdgpu_df_funcs df_v3_6_funcs = {
115*b843c749SSergey Zigachev .init = df_v3_6_init,
116*b843c749SSergey Zigachev .enable_broadcast_mode = df_v3_6_enable_broadcast_mode,
117*b843c749SSergey Zigachev .get_fb_channel_number = df_v3_6_get_fb_channel_number,
118*b843c749SSergey Zigachev .get_hbm_channel_number = df_v3_6_get_hbm_channel_number,
119*b843c749SSergey Zigachev .update_medium_grain_clock_gating =
120*b843c749SSergey Zigachev df_v3_6_update_medium_grain_clock_gating,
121*b843c749SSergey Zigachev .get_clockgating_state = df_v3_6_get_clockgating_state,
122*b843c749SSergey Zigachev };
123