1b843c749SSergey Zigachev /*
2b843c749SSergey Zigachev * Copyright 2008 Advanced Micro Devices, Inc.
3b843c749SSergey Zigachev * Copyright 2008 Red Hat Inc.
4b843c749SSergey Zigachev * Copyright 2009 Jerome Glisse.
5b843c749SSergey Zigachev *
6b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
7b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
8b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
9b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
11b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
12b843c749SSergey Zigachev *
13b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
14b843c749SSergey Zigachev * all copies or substantial portions of the Software.
15b843c749SSergey Zigachev *
16b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
23b843c749SSergey Zigachev *
24b843c749SSergey Zigachev * Authors: Dave Airlie
25b843c749SSergey Zigachev * Alex Deucher
26b843c749SSergey Zigachev * Jerome Glisse
27b843c749SSergey Zigachev */
28b843c749SSergey Zigachev #include <drm/drmP.h>
29b843c749SSergey Zigachev #include "amdgpu.h"
30b843c749SSergey Zigachev #include <drm/amdgpu_drm.h>
31b843c749SSergey Zigachev #include "amdgpu_sched.h"
32b843c749SSergey Zigachev #include "amdgpu_uvd.h"
33b843c749SSergey Zigachev #include "amdgpu_vce.h"
34b843c749SSergey Zigachev #include "atom.h"
35b843c749SSergey Zigachev
36b843c749SSergey Zigachev #include <linux/vga_switcheroo.h>
37b843c749SSergey Zigachev #include <linux/slab.h>
38b843c749SSergey Zigachev #include <linux/pm_runtime.h>
39b843c749SSergey Zigachev #include "amdgpu_amdkfd.h"
40b843c749SSergey Zigachev
41b843c749SSergey Zigachev /**
42b843c749SSergey Zigachev * amdgpu_driver_unload_kms - Main unload function for KMS.
43b843c749SSergey Zigachev *
44b843c749SSergey Zigachev * @dev: drm dev pointer
45b843c749SSergey Zigachev *
46b843c749SSergey Zigachev * This is the main unload function for KMS (all asics).
47b843c749SSergey Zigachev * Returns 0 on success.
48b843c749SSergey Zigachev */
amdgpu_driver_unload_kms(struct drm_device * dev)49b843c749SSergey Zigachev void amdgpu_driver_unload_kms(struct drm_device *dev)
50b843c749SSergey Zigachev {
51b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
52b843c749SSergey Zigachev
53b843c749SSergey Zigachev if (adev == NULL)
54b843c749SSergey Zigachev return;
55b843c749SSergey Zigachev
56b843c749SSergey Zigachev if (adev->rmmio == NULL)
57b843c749SSergey Zigachev goto done_free;
58b843c749SSergey Zigachev
59b843c749SSergey Zigachev if (amdgpu_sriov_vf(adev))
60b843c749SSergey Zigachev amdgpu_virt_request_full_gpu(adev, false);
61b843c749SSergey Zigachev
62b843c749SSergey Zigachev if (amdgpu_device_is_px(dev)) {
63*78973132SSergey Zigachev #if 0
64b843c749SSergey Zigachev pm_runtime_get_sync(dev->dev);
65b843c749SSergey Zigachev pm_runtime_forbid(dev->dev);
66*78973132SSergey Zigachev #endif
67b843c749SSergey Zigachev }
68b843c749SSergey Zigachev
69b843c749SSergey Zigachev amdgpu_acpi_fini(adev);
70b843c749SSergey Zigachev
71b843c749SSergey Zigachev amdgpu_device_fini(adev);
72b843c749SSergey Zigachev
73b843c749SSergey Zigachev done_free:
74b843c749SSergey Zigachev kfree(adev);
75b843c749SSergey Zigachev dev->dev_private = NULL;
76b843c749SSergey Zigachev }
77b843c749SSergey Zigachev
78b843c749SSergey Zigachev /**
79b843c749SSergey Zigachev * amdgpu_driver_load_kms - Main load function for KMS.
80b843c749SSergey Zigachev *
81b843c749SSergey Zigachev * @dev: drm dev pointer
82b843c749SSergey Zigachev * @flags: device flags
83b843c749SSergey Zigachev *
84b843c749SSergey Zigachev * This is the main load function for KMS (all asics).
85b843c749SSergey Zigachev * Returns 0 on success, error on failure.
86b843c749SSergey Zigachev */
amdgpu_driver_load_kms(struct drm_device * dev,unsigned long flags)87b843c749SSergey Zigachev int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
88b843c749SSergey Zigachev {
89b843c749SSergey Zigachev struct amdgpu_device *adev;
90b843c749SSergey Zigachev int r, acpi_status;
91b843c749SSergey Zigachev
92b843c749SSergey Zigachev adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
93b843c749SSergey Zigachev if (adev == NULL) {
94b843c749SSergey Zigachev return -ENOMEM;
95b843c749SSergey Zigachev }
96b843c749SSergey Zigachev dev->dev_private = (void *)adev;
97*78973132SSergey Zigachev kprintf("amdgpu_driver_load_kms(): flags=%ld drm_device=%p adev=%p\n",
98*78973132SSergey Zigachev flags, dev, adev);
99b843c749SSergey Zigachev
100b843c749SSergey Zigachev if ((amdgpu_runtime_pm != 0) &&
101b843c749SSergey Zigachev amdgpu_has_atpx() &&
102b843c749SSergey Zigachev (amdgpu_is_atpx_hybrid() ||
103b843c749SSergey Zigachev amdgpu_has_atpx_dgpu_power_cntl()) &&
104*78973132SSergey Zigachev ((flags & AMD_IS_APU) == 0)
105*78973132SSergey Zigachev #if 0
106*78973132SSergey Zigachev && !pci_is_thunderbolt_attached(dev->pdev)
107*78973132SSergey Zigachev #endif
108*78973132SSergey Zigachev )
109b843c749SSergey Zigachev flags |= AMD_IS_PX;
110b843c749SSergey Zigachev
111b843c749SSergey Zigachev /* amdgpu_device_init should report only fatal error
112b843c749SSergey Zigachev * like memory allocation failure or iomapping failure,
113b843c749SSergey Zigachev * or memory manager initialization failure, it must
114b843c749SSergey Zigachev * properly initialize the GPU MC controller and permit
115b843c749SSergey Zigachev * VRAM allocation
116b843c749SSergey Zigachev */
117b843c749SSergey Zigachev r = amdgpu_device_init(adev, dev, dev->pdev, flags);
118b843c749SSergey Zigachev if (r) {
119b843c749SSergey Zigachev dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
120b843c749SSergey Zigachev goto out;
121b843c749SSergey Zigachev }
122b843c749SSergey Zigachev
123b843c749SSergey Zigachev /* Call ACPI methods: require modeset init
124b843c749SSergey Zigachev * but failure is not fatal
125b843c749SSergey Zigachev */
126b843c749SSergey Zigachev if (!r) {
127b843c749SSergey Zigachev acpi_status = amdgpu_acpi_init(adev);
128b843c749SSergey Zigachev if (acpi_status)
129b843c749SSergey Zigachev dev_dbg(&dev->pdev->dev,
130b843c749SSergey Zigachev "Error during ACPI methods call\n");
131b843c749SSergey Zigachev }
132b843c749SSergey Zigachev
133b843c749SSergey Zigachev if (amdgpu_device_is_px(dev)) {
134b843c749SSergey Zigachev dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NEVER_SKIP);
135*78973132SSergey Zigachev #if 0
136b843c749SSergey Zigachev pm_runtime_use_autosuspend(dev->dev);
137b843c749SSergey Zigachev pm_runtime_set_autosuspend_delay(dev->dev, 5000);
138*78973132SSergey Zigachev #endif
139b843c749SSergey Zigachev pm_runtime_set_active(dev->dev);
140*78973132SSergey Zigachev #if 0
141b843c749SSergey Zigachev pm_runtime_allow(dev->dev);
142*78973132SSergey Zigachev #endif
143b843c749SSergey Zigachev pm_runtime_mark_last_busy(dev->dev);
144*78973132SSergey Zigachev #if 0
145b843c749SSergey Zigachev pm_runtime_put_autosuspend(dev->dev);
146*78973132SSergey Zigachev #endif
147b843c749SSergey Zigachev }
148b843c749SSergey Zigachev
149b843c749SSergey Zigachev out:
150b843c749SSergey Zigachev if (r) {
151b843c749SSergey Zigachev /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
152*78973132SSergey Zigachev #if 0
153b843c749SSergey Zigachev if (adev->rmmio && amdgpu_device_is_px(dev))
154b843c749SSergey Zigachev pm_runtime_put_noidle(dev->dev);
155*78973132SSergey Zigachev #endif
156b843c749SSergey Zigachev amdgpu_driver_unload_kms(dev);
157b843c749SSergey Zigachev }
158b843c749SSergey Zigachev
159b843c749SSergey Zigachev return r;
160b843c749SSergey Zigachev }
161b843c749SSergey Zigachev
amdgpu_firmware_info(struct drm_amdgpu_info_firmware * fw_info,struct drm_amdgpu_query_fw * query_fw,struct amdgpu_device * adev)162b843c749SSergey Zigachev static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
163b843c749SSergey Zigachev struct drm_amdgpu_query_fw *query_fw,
164b843c749SSergey Zigachev struct amdgpu_device *adev)
165b843c749SSergey Zigachev {
166b843c749SSergey Zigachev switch (query_fw->fw_type) {
167b843c749SSergey Zigachev case AMDGPU_INFO_FW_VCE:
168b843c749SSergey Zigachev fw_info->ver = adev->vce.fw_version;
169b843c749SSergey Zigachev fw_info->feature = adev->vce.fb_version;
170b843c749SSergey Zigachev break;
171b843c749SSergey Zigachev case AMDGPU_INFO_FW_UVD:
172b843c749SSergey Zigachev fw_info->ver = adev->uvd.fw_version;
173b843c749SSergey Zigachev fw_info->feature = 0;
174b843c749SSergey Zigachev break;
175b843c749SSergey Zigachev case AMDGPU_INFO_FW_VCN:
176b843c749SSergey Zigachev fw_info->ver = adev->vcn.fw_version;
177b843c749SSergey Zigachev fw_info->feature = 0;
178b843c749SSergey Zigachev break;
179b843c749SSergey Zigachev case AMDGPU_INFO_FW_GMC:
180b843c749SSergey Zigachev fw_info->ver = adev->gmc.fw_version;
181b843c749SSergey Zigachev fw_info->feature = 0;
182b843c749SSergey Zigachev break;
183b843c749SSergey Zigachev case AMDGPU_INFO_FW_GFX_ME:
184b843c749SSergey Zigachev fw_info->ver = adev->gfx.me_fw_version;
185b843c749SSergey Zigachev fw_info->feature = adev->gfx.me_feature_version;
186b843c749SSergey Zigachev break;
187b843c749SSergey Zigachev case AMDGPU_INFO_FW_GFX_PFP:
188b843c749SSergey Zigachev fw_info->ver = adev->gfx.pfp_fw_version;
189b843c749SSergey Zigachev fw_info->feature = adev->gfx.pfp_feature_version;
190b843c749SSergey Zigachev break;
191b843c749SSergey Zigachev case AMDGPU_INFO_FW_GFX_CE:
192b843c749SSergey Zigachev fw_info->ver = adev->gfx.ce_fw_version;
193b843c749SSergey Zigachev fw_info->feature = adev->gfx.ce_feature_version;
194b843c749SSergey Zigachev break;
195b843c749SSergey Zigachev case AMDGPU_INFO_FW_GFX_RLC:
196b843c749SSergey Zigachev fw_info->ver = adev->gfx.rlc_fw_version;
197b843c749SSergey Zigachev fw_info->feature = adev->gfx.rlc_feature_version;
198b843c749SSergey Zigachev break;
199b843c749SSergey Zigachev case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
200b843c749SSergey Zigachev fw_info->ver = adev->gfx.rlc_srlc_fw_version;
201b843c749SSergey Zigachev fw_info->feature = adev->gfx.rlc_srlc_feature_version;
202b843c749SSergey Zigachev break;
203b843c749SSergey Zigachev case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
204b843c749SSergey Zigachev fw_info->ver = adev->gfx.rlc_srlg_fw_version;
205b843c749SSergey Zigachev fw_info->feature = adev->gfx.rlc_srlg_feature_version;
206b843c749SSergey Zigachev break;
207b843c749SSergey Zigachev case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
208b843c749SSergey Zigachev fw_info->ver = adev->gfx.rlc_srls_fw_version;
209b843c749SSergey Zigachev fw_info->feature = adev->gfx.rlc_srls_feature_version;
210b843c749SSergey Zigachev break;
211b843c749SSergey Zigachev case AMDGPU_INFO_FW_GFX_MEC:
212b843c749SSergey Zigachev if (query_fw->index == 0) {
213b843c749SSergey Zigachev fw_info->ver = adev->gfx.mec_fw_version;
214b843c749SSergey Zigachev fw_info->feature = adev->gfx.mec_feature_version;
215b843c749SSergey Zigachev } else if (query_fw->index == 1) {
216b843c749SSergey Zigachev fw_info->ver = adev->gfx.mec2_fw_version;
217b843c749SSergey Zigachev fw_info->feature = adev->gfx.mec2_feature_version;
218b843c749SSergey Zigachev } else
219b843c749SSergey Zigachev return -EINVAL;
220b843c749SSergey Zigachev break;
221b843c749SSergey Zigachev case AMDGPU_INFO_FW_SMC:
222b843c749SSergey Zigachev fw_info->ver = adev->pm.fw_version;
223b843c749SSergey Zigachev fw_info->feature = 0;
224b843c749SSergey Zigachev break;
225b843c749SSergey Zigachev case AMDGPU_INFO_FW_SDMA:
226b843c749SSergey Zigachev if (query_fw->index >= adev->sdma.num_instances)
227b843c749SSergey Zigachev return -EINVAL;
228b843c749SSergey Zigachev fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
229b843c749SSergey Zigachev fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
230b843c749SSergey Zigachev break;
231b843c749SSergey Zigachev case AMDGPU_INFO_FW_SOS:
232b843c749SSergey Zigachev fw_info->ver = adev->psp.sos_fw_version;
233b843c749SSergey Zigachev fw_info->feature = adev->psp.sos_feature_version;
234b843c749SSergey Zigachev break;
235b843c749SSergey Zigachev case AMDGPU_INFO_FW_ASD:
236b843c749SSergey Zigachev fw_info->ver = adev->psp.asd_fw_version;
237b843c749SSergey Zigachev fw_info->feature = adev->psp.asd_feature_version;
238b843c749SSergey Zigachev break;
239b843c749SSergey Zigachev default:
240b843c749SSergey Zigachev return -EINVAL;
241b843c749SSergey Zigachev }
242b843c749SSergey Zigachev return 0;
243b843c749SSergey Zigachev }
244b843c749SSergey Zigachev
245b843c749SSergey Zigachev /*
246b843c749SSergey Zigachev * Userspace get information ioctl
247b843c749SSergey Zigachev */
248b843c749SSergey Zigachev /**
249b843c749SSergey Zigachev * amdgpu_info_ioctl - answer a device specific request.
250b843c749SSergey Zigachev *
251b843c749SSergey Zigachev * @adev: amdgpu device pointer
252b843c749SSergey Zigachev * @data: request object
253b843c749SSergey Zigachev * @filp: drm filp
254b843c749SSergey Zigachev *
255b843c749SSergey Zigachev * This function is used to pass device specific parameters to the userspace
256b843c749SSergey Zigachev * drivers. Examples include: pci device id, pipeline parms, tiling params,
257b843c749SSergey Zigachev * etc. (all asics).
258b843c749SSergey Zigachev * Returns 0 on success, -EINVAL on failure.
259b843c749SSergey Zigachev */
amdgpu_info_ioctl(struct drm_device * dev,void * data,struct drm_file * filp)260b843c749SSergey Zigachev static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
261b843c749SSergey Zigachev {
262b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
263b843c749SSergey Zigachev struct drm_amdgpu_info *info = data;
264b843c749SSergey Zigachev struct amdgpu_mode_info *minfo = &adev->mode_info;
265b843c749SSergey Zigachev void __user *out = (void __user *)(uintptr_t)info->return_pointer;
266b843c749SSergey Zigachev uint32_t size = info->return_size;
267b843c749SSergey Zigachev struct drm_crtc *crtc;
268b843c749SSergey Zigachev uint32_t ui32 = 0;
269b843c749SSergey Zigachev uint64_t ui64 = 0;
270b843c749SSergey Zigachev int i, j, found;
271b843c749SSergey Zigachev int ui32_size = sizeof(ui32);
272b843c749SSergey Zigachev
273b843c749SSergey Zigachev if (!info->return_size || !info->return_pointer)
274b843c749SSergey Zigachev return -EINVAL;
275b843c749SSergey Zigachev
276b843c749SSergey Zigachev switch (info->query) {
277b843c749SSergey Zigachev case AMDGPU_INFO_ACCEL_WORKING:
278b843c749SSergey Zigachev ui32 = adev->accel_working;
279b843c749SSergey Zigachev return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
280b843c749SSergey Zigachev case AMDGPU_INFO_CRTC_FROM_ID:
281b843c749SSergey Zigachev for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
282b843c749SSergey Zigachev crtc = (struct drm_crtc *)minfo->crtcs[i];
283b843c749SSergey Zigachev if (crtc && crtc->base.id == info->mode_crtc.id) {
284b843c749SSergey Zigachev struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
285b843c749SSergey Zigachev ui32 = amdgpu_crtc->crtc_id;
286b843c749SSergey Zigachev found = 1;
287b843c749SSergey Zigachev break;
288b843c749SSergey Zigachev }
289b843c749SSergey Zigachev }
290b843c749SSergey Zigachev if (!found) {
291b843c749SSergey Zigachev DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
292b843c749SSergey Zigachev return -EINVAL;
293b843c749SSergey Zigachev }
294b843c749SSergey Zigachev return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
295b843c749SSergey Zigachev case AMDGPU_INFO_HW_IP_INFO: {
296b843c749SSergey Zigachev struct drm_amdgpu_info_hw_ip ip = {};
297b843c749SSergey Zigachev enum amd_ip_block_type type;
298b843c749SSergey Zigachev uint32_t ring_mask = 0;
299b843c749SSergey Zigachev uint32_t ib_start_alignment = 0;
300b843c749SSergey Zigachev uint32_t ib_size_alignment = 0;
301b843c749SSergey Zigachev
302b843c749SSergey Zigachev if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
303b843c749SSergey Zigachev return -EINVAL;
304b843c749SSergey Zigachev
305b843c749SSergey Zigachev switch (info->query_hw_ip.type) {
306b843c749SSergey Zigachev case AMDGPU_HW_IP_GFX:
307b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_GFX;
308b843c749SSergey Zigachev for (i = 0; i < adev->gfx.num_gfx_rings; i++)
309b843c749SSergey Zigachev ring_mask |= adev->gfx.gfx_ring[i].ready << i;
310b843c749SSergey Zigachev ib_start_alignment = 32;
311b843c749SSergey Zigachev ib_size_alignment = 32;
312b843c749SSergey Zigachev break;
313b843c749SSergey Zigachev case AMDGPU_HW_IP_COMPUTE:
314b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_GFX;
315b843c749SSergey Zigachev for (i = 0; i < adev->gfx.num_compute_rings; i++)
316b843c749SSergey Zigachev ring_mask |= adev->gfx.compute_ring[i].ready << i;
317b843c749SSergey Zigachev ib_start_alignment = 32;
318b843c749SSergey Zigachev ib_size_alignment = 32;
319b843c749SSergey Zigachev break;
320b843c749SSergey Zigachev case AMDGPU_HW_IP_DMA:
321b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_SDMA;
322b843c749SSergey Zigachev for (i = 0; i < adev->sdma.num_instances; i++)
323b843c749SSergey Zigachev ring_mask |= adev->sdma.instance[i].ring.ready << i;
324b843c749SSergey Zigachev ib_start_alignment = 256;
325b843c749SSergey Zigachev ib_size_alignment = 4;
326b843c749SSergey Zigachev break;
327b843c749SSergey Zigachev case AMDGPU_HW_IP_UVD:
328b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_UVD;
329b843c749SSergey Zigachev for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
330b843c749SSergey Zigachev if (adev->uvd.harvest_config & (1 << i))
331b843c749SSergey Zigachev continue;
332b843c749SSergey Zigachev ring_mask |= adev->uvd.inst[i].ring.ready;
333b843c749SSergey Zigachev }
334b843c749SSergey Zigachev ib_start_alignment = 64;
335b843c749SSergey Zigachev ib_size_alignment = 64;
336b843c749SSergey Zigachev break;
337b843c749SSergey Zigachev case AMDGPU_HW_IP_VCE:
338b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_VCE;
339b843c749SSergey Zigachev for (i = 0; i < adev->vce.num_rings; i++)
340b843c749SSergey Zigachev ring_mask |= adev->vce.ring[i].ready << i;
341b843c749SSergey Zigachev ib_start_alignment = 4;
342b843c749SSergey Zigachev ib_size_alignment = 1;
343b843c749SSergey Zigachev break;
344b843c749SSergey Zigachev case AMDGPU_HW_IP_UVD_ENC:
345b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_UVD;
346b843c749SSergey Zigachev for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
347b843c749SSergey Zigachev if (adev->uvd.harvest_config & (1 << i))
348b843c749SSergey Zigachev continue;
349b843c749SSergey Zigachev for (j = 0; j < adev->uvd.num_enc_rings; j++)
350b843c749SSergey Zigachev ring_mask |= adev->uvd.inst[i].ring_enc[j].ready << j;
351b843c749SSergey Zigachev }
352b843c749SSergey Zigachev ib_start_alignment = 64;
353b843c749SSergey Zigachev ib_size_alignment = 64;
354b843c749SSergey Zigachev break;
355b843c749SSergey Zigachev case AMDGPU_HW_IP_VCN_DEC:
356b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_VCN;
357b843c749SSergey Zigachev ring_mask = adev->vcn.ring_dec.ready;
358b843c749SSergey Zigachev ib_start_alignment = 16;
359b843c749SSergey Zigachev ib_size_alignment = 16;
360b843c749SSergey Zigachev break;
361b843c749SSergey Zigachev case AMDGPU_HW_IP_VCN_ENC:
362b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_VCN;
363b843c749SSergey Zigachev for (i = 0; i < adev->vcn.num_enc_rings; i++)
364b843c749SSergey Zigachev ring_mask |= adev->vcn.ring_enc[i].ready << i;
365b843c749SSergey Zigachev ib_start_alignment = 64;
366b843c749SSergey Zigachev ib_size_alignment = 1;
367b843c749SSergey Zigachev break;
368b843c749SSergey Zigachev case AMDGPU_HW_IP_VCN_JPEG:
369b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_VCN;
370b843c749SSergey Zigachev ring_mask = adev->vcn.ring_jpeg.ready;
371b843c749SSergey Zigachev ib_start_alignment = 16;
372b843c749SSergey Zigachev ib_size_alignment = 16;
373b843c749SSergey Zigachev break;
374b843c749SSergey Zigachev default:
375b843c749SSergey Zigachev return -EINVAL;
376b843c749SSergey Zigachev }
377b843c749SSergey Zigachev
378b843c749SSergey Zigachev for (i = 0; i < adev->num_ip_blocks; i++) {
379b843c749SSergey Zigachev if (adev->ip_blocks[i].version->type == type &&
380b843c749SSergey Zigachev adev->ip_blocks[i].status.valid) {
381b843c749SSergey Zigachev ip.hw_ip_version_major = adev->ip_blocks[i].version->major;
382b843c749SSergey Zigachev ip.hw_ip_version_minor = adev->ip_blocks[i].version->minor;
383b843c749SSergey Zigachev ip.capabilities_flags = 0;
384b843c749SSergey Zigachev ip.available_rings = ring_mask;
385b843c749SSergey Zigachev ip.ib_start_alignment = ib_start_alignment;
386b843c749SSergey Zigachev ip.ib_size_alignment = ib_size_alignment;
387b843c749SSergey Zigachev break;
388b843c749SSergey Zigachev }
389b843c749SSergey Zigachev }
390b843c749SSergey Zigachev return copy_to_user(out, &ip,
391b843c749SSergey Zigachev min((size_t)size, sizeof(ip))) ? -EFAULT : 0;
392b843c749SSergey Zigachev }
393b843c749SSergey Zigachev case AMDGPU_INFO_HW_IP_COUNT: {
394b843c749SSergey Zigachev enum amd_ip_block_type type;
395b843c749SSergey Zigachev uint32_t count = 0;
396b843c749SSergey Zigachev
397b843c749SSergey Zigachev switch (info->query_hw_ip.type) {
398b843c749SSergey Zigachev case AMDGPU_HW_IP_GFX:
399b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_GFX;
400b843c749SSergey Zigachev break;
401b843c749SSergey Zigachev case AMDGPU_HW_IP_COMPUTE:
402b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_GFX;
403b843c749SSergey Zigachev break;
404b843c749SSergey Zigachev case AMDGPU_HW_IP_DMA:
405b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_SDMA;
406b843c749SSergey Zigachev break;
407b843c749SSergey Zigachev case AMDGPU_HW_IP_UVD:
408b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_UVD;
409b843c749SSergey Zigachev break;
410b843c749SSergey Zigachev case AMDGPU_HW_IP_VCE:
411b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_VCE;
412b843c749SSergey Zigachev break;
413b843c749SSergey Zigachev case AMDGPU_HW_IP_UVD_ENC:
414b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_UVD;
415b843c749SSergey Zigachev break;
416b843c749SSergey Zigachev case AMDGPU_HW_IP_VCN_DEC:
417b843c749SSergey Zigachev case AMDGPU_HW_IP_VCN_ENC:
418b843c749SSergey Zigachev case AMDGPU_HW_IP_VCN_JPEG:
419b843c749SSergey Zigachev type = AMD_IP_BLOCK_TYPE_VCN;
420b843c749SSergey Zigachev break;
421b843c749SSergey Zigachev default:
422b843c749SSergey Zigachev return -EINVAL;
423b843c749SSergey Zigachev }
424b843c749SSergey Zigachev
425b843c749SSergey Zigachev for (i = 0; i < adev->num_ip_blocks; i++)
426b843c749SSergey Zigachev if (adev->ip_blocks[i].version->type == type &&
427b843c749SSergey Zigachev adev->ip_blocks[i].status.valid &&
428b843c749SSergey Zigachev count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
429b843c749SSergey Zigachev count++;
430b843c749SSergey Zigachev
431b843c749SSergey Zigachev return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
432b843c749SSergey Zigachev }
433b843c749SSergey Zigachev case AMDGPU_INFO_TIMESTAMP:
434b843c749SSergey Zigachev ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
435b843c749SSergey Zigachev return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
436b843c749SSergey Zigachev case AMDGPU_INFO_FW_VERSION: {
437b843c749SSergey Zigachev struct drm_amdgpu_info_firmware fw_info;
438b843c749SSergey Zigachev int ret;
439b843c749SSergey Zigachev
440b843c749SSergey Zigachev /* We only support one instance of each IP block right now. */
441b843c749SSergey Zigachev if (info->query_fw.ip_instance != 0)
442b843c749SSergey Zigachev return -EINVAL;
443b843c749SSergey Zigachev
444b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
445b843c749SSergey Zigachev if (ret)
446b843c749SSergey Zigachev return ret;
447b843c749SSergey Zigachev
448b843c749SSergey Zigachev return copy_to_user(out, &fw_info,
449b843c749SSergey Zigachev min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
450b843c749SSergey Zigachev }
451b843c749SSergey Zigachev case AMDGPU_INFO_NUM_BYTES_MOVED:
452b843c749SSergey Zigachev ui64 = atomic64_read(&adev->num_bytes_moved);
453b843c749SSergey Zigachev return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
454b843c749SSergey Zigachev case AMDGPU_INFO_NUM_EVICTIONS:
455b843c749SSergey Zigachev ui64 = atomic64_read(&adev->num_evictions);
456b843c749SSergey Zigachev return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
457b843c749SSergey Zigachev case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
458b843c749SSergey Zigachev ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
459b843c749SSergey Zigachev return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
460b843c749SSergey Zigachev case AMDGPU_INFO_VRAM_USAGE:
461b843c749SSergey Zigachev ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
462b843c749SSergey Zigachev return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
463b843c749SSergey Zigachev case AMDGPU_INFO_VIS_VRAM_USAGE:
464b843c749SSergey Zigachev ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
465b843c749SSergey Zigachev return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
466b843c749SSergey Zigachev case AMDGPU_INFO_GTT_USAGE:
467b843c749SSergey Zigachev ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
468b843c749SSergey Zigachev return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
469b843c749SSergey Zigachev case AMDGPU_INFO_GDS_CONFIG: {
470b843c749SSergey Zigachev struct drm_amdgpu_info_gds gds_info;
471b843c749SSergey Zigachev
472b843c749SSergey Zigachev memset(&gds_info, 0, sizeof(gds_info));
473b843c749SSergey Zigachev gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT;
474b843c749SSergey Zigachev gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT;
475b843c749SSergey Zigachev gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT;
476b843c749SSergey Zigachev gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT;
477b843c749SSergey Zigachev gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT;
478b843c749SSergey Zigachev gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT;
479b843c749SSergey Zigachev gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT;
480b843c749SSergey Zigachev return copy_to_user(out, &gds_info,
481b843c749SSergey Zigachev min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
482b843c749SSergey Zigachev }
483b843c749SSergey Zigachev case AMDGPU_INFO_VRAM_GTT: {
484b843c749SSergey Zigachev struct drm_amdgpu_info_vram_gtt vram_gtt;
485b843c749SSergey Zigachev
486b843c749SSergey Zigachev vram_gtt.vram_size = adev->gmc.real_vram_size -
487b843c749SSergey Zigachev atomic64_read(&adev->vram_pin_size);
488b843c749SSergey Zigachev vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size -
489b843c749SSergey Zigachev atomic64_read(&adev->visible_pin_size);
490b843c749SSergey Zigachev vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
491b843c749SSergey Zigachev vram_gtt.gtt_size *= PAGE_SIZE;
492b843c749SSergey Zigachev vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
493b843c749SSergey Zigachev return copy_to_user(out, &vram_gtt,
494b843c749SSergey Zigachev min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
495b843c749SSergey Zigachev }
496b843c749SSergey Zigachev case AMDGPU_INFO_MEMORY: {
497b843c749SSergey Zigachev struct drm_amdgpu_memory_info mem;
498b843c749SSergey Zigachev
499b843c749SSergey Zigachev memset(&mem, 0, sizeof(mem));
500b843c749SSergey Zigachev mem.vram.total_heap_size = adev->gmc.real_vram_size;
501b843c749SSergey Zigachev mem.vram.usable_heap_size = adev->gmc.real_vram_size -
502b843c749SSergey Zigachev atomic64_read(&adev->vram_pin_size);
503b843c749SSergey Zigachev mem.vram.heap_usage =
504b843c749SSergey Zigachev amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
505b843c749SSergey Zigachev mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
506b843c749SSergey Zigachev
507b843c749SSergey Zigachev mem.cpu_accessible_vram.total_heap_size =
508b843c749SSergey Zigachev adev->gmc.visible_vram_size;
509b843c749SSergey Zigachev mem.cpu_accessible_vram.usable_heap_size = adev->gmc.visible_vram_size -
510b843c749SSergey Zigachev atomic64_read(&adev->visible_pin_size);
511b843c749SSergey Zigachev mem.cpu_accessible_vram.heap_usage =
512b843c749SSergey Zigachev amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
513b843c749SSergey Zigachev mem.cpu_accessible_vram.max_allocation =
514b843c749SSergey Zigachev mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
515b843c749SSergey Zigachev
516b843c749SSergey Zigachev mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
517b843c749SSergey Zigachev mem.gtt.total_heap_size *= PAGE_SIZE;
518b843c749SSergey Zigachev mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
519b843c749SSergey Zigachev atomic64_read(&adev->gart_pin_size);
520b843c749SSergey Zigachev mem.gtt.heap_usage =
521b843c749SSergey Zigachev amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
522b843c749SSergey Zigachev mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
523b843c749SSergey Zigachev
524b843c749SSergey Zigachev return copy_to_user(out, &mem,
525b843c749SSergey Zigachev min((size_t)size, sizeof(mem)))
526b843c749SSergey Zigachev ? -EFAULT : 0;
527b843c749SSergey Zigachev }
528b843c749SSergey Zigachev case AMDGPU_INFO_READ_MMR_REG: {
529b843c749SSergey Zigachev unsigned n, alloc_size;
530b843c749SSergey Zigachev uint32_t *regs;
531b843c749SSergey Zigachev unsigned se_num = (info->read_mmr_reg.instance >>
532b843c749SSergey Zigachev AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
533b843c749SSergey Zigachev AMDGPU_INFO_MMR_SE_INDEX_MASK;
534b843c749SSergey Zigachev unsigned sh_num = (info->read_mmr_reg.instance >>
535b843c749SSergey Zigachev AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
536b843c749SSergey Zigachev AMDGPU_INFO_MMR_SH_INDEX_MASK;
537b843c749SSergey Zigachev
538b843c749SSergey Zigachev /* set full masks if the userspace set all bits
539b843c749SSergey Zigachev * in the bitfields */
540b843c749SSergey Zigachev if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
541b843c749SSergey Zigachev se_num = 0xffffffff;
542b843c749SSergey Zigachev else if (se_num >= AMDGPU_GFX_MAX_SE)
543b843c749SSergey Zigachev return -EINVAL;
544b843c749SSergey Zigachev if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
545b843c749SSergey Zigachev sh_num = 0xffffffff;
546b843c749SSergey Zigachev else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
547b843c749SSergey Zigachev return -EINVAL;
548b843c749SSergey Zigachev
549b843c749SSergey Zigachev if (info->read_mmr_reg.count > 128)
550b843c749SSergey Zigachev return -EINVAL;
551b843c749SSergey Zigachev
552b843c749SSergey Zigachev regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
553b843c749SSergey Zigachev if (!regs)
554b843c749SSergey Zigachev return -ENOMEM;
555b843c749SSergey Zigachev alloc_size = info->read_mmr_reg.count * sizeof(*regs);
556b843c749SSergey Zigachev
557b843c749SSergey Zigachev for (i = 0; i < info->read_mmr_reg.count; i++)
558b843c749SSergey Zigachev if (amdgpu_asic_read_register(adev, se_num, sh_num,
559b843c749SSergey Zigachev info->read_mmr_reg.dword_offset + i,
560b843c749SSergey Zigachev ®s[i])) {
561b843c749SSergey Zigachev DRM_DEBUG_KMS("unallowed offset %#x\n",
562b843c749SSergey Zigachev info->read_mmr_reg.dword_offset + i);
563b843c749SSergey Zigachev kfree(regs);
564b843c749SSergey Zigachev return -EFAULT;
565b843c749SSergey Zigachev }
566b843c749SSergey Zigachev n = copy_to_user(out, regs, min(size, alloc_size));
567b843c749SSergey Zigachev kfree(regs);
568b843c749SSergey Zigachev return n ? -EFAULT : 0;
569b843c749SSergey Zigachev }
570b843c749SSergey Zigachev case AMDGPU_INFO_DEV_INFO: {
571b843c749SSergey Zigachev struct drm_amdgpu_info_device dev_info;
572b843c749SSergey Zigachev uint64_t vm_size;
573b843c749SSergey Zigachev
574b843c749SSergey Zigachev memset(&dev_info, 0, sizeof(dev_info));
575b843c749SSergey Zigachev dev_info.device_id = dev->pdev->device;
576b843c749SSergey Zigachev dev_info.chip_rev = adev->rev_id;
577b843c749SSergey Zigachev dev_info.external_rev = adev->external_rev_id;
578b843c749SSergey Zigachev dev_info.pci_rev = dev->pdev->revision;
579b843c749SSergey Zigachev dev_info.family = adev->family;
580b843c749SSergey Zigachev dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
581b843c749SSergey Zigachev dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
582b843c749SSergey Zigachev /* return all clocks in KHz */
583b843c749SSergey Zigachev dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
584b843c749SSergey Zigachev if (adev->pm.dpm_enabled) {
585b843c749SSergey Zigachev dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
586b843c749SSergey Zigachev dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
587b843c749SSergey Zigachev } else {
588b843c749SSergey Zigachev dev_info.max_engine_clock = adev->clock.default_sclk * 10;
589b843c749SSergey Zigachev dev_info.max_memory_clock = adev->clock.default_mclk * 10;
590b843c749SSergey Zigachev }
591b843c749SSergey Zigachev dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
592b843c749SSergey Zigachev dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
593b843c749SSergey Zigachev adev->gfx.config.max_shader_engines;
594b843c749SSergey Zigachev dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
595b843c749SSergey Zigachev dev_info._pad = 0;
596b843c749SSergey Zigachev dev_info.ids_flags = 0;
597b843c749SSergey Zigachev if (adev->flags & AMD_IS_APU)
598b843c749SSergey Zigachev dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
599b843c749SSergey Zigachev if (amdgpu_sriov_vf(adev))
600b843c749SSergey Zigachev dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
601b843c749SSergey Zigachev
602b843c749SSergey Zigachev vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
603b843c749SSergey Zigachev vm_size -= AMDGPU_VA_RESERVED_SIZE;
604b843c749SSergey Zigachev
605b843c749SSergey Zigachev /* Older VCE FW versions are buggy and can handle only 40bits */
606b843c749SSergey Zigachev if (adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
607b843c749SSergey Zigachev vm_size = min(vm_size, 1ULL << 40);
608b843c749SSergey Zigachev
609b843c749SSergey Zigachev dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
610b843c749SSergey Zigachev dev_info.virtual_address_max =
611b843c749SSergey Zigachev min(vm_size, AMDGPU_VA_HOLE_START);
612b843c749SSergey Zigachev
613b843c749SSergey Zigachev if (vm_size > AMDGPU_VA_HOLE_START) {
614b843c749SSergey Zigachev dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
615b843c749SSergey Zigachev dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
616b843c749SSergey Zigachev }
617b843c749SSergey Zigachev dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
618b843c749SSergey Zigachev dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
619b843c749SSergey Zigachev dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
620b843c749SSergey Zigachev dev_info.cu_active_number = adev->gfx.cu_info.number;
621b843c749SSergey Zigachev dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
622b843c749SSergey Zigachev dev_info.ce_ram_size = adev->gfx.ce_ram_size;
623b843c749SSergey Zigachev memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
624b843c749SSergey Zigachev sizeof(adev->gfx.cu_info.ao_cu_bitmap));
625b843c749SSergey Zigachev memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
626b843c749SSergey Zigachev sizeof(adev->gfx.cu_info.bitmap));
627b843c749SSergey Zigachev dev_info.vram_type = adev->gmc.vram_type;
628b843c749SSergey Zigachev dev_info.vram_bit_width = adev->gmc.vram_width;
629b843c749SSergey Zigachev dev_info.vce_harvest_config = adev->vce.harvest_config;
630b843c749SSergey Zigachev dev_info.gc_double_offchip_lds_buf =
631b843c749SSergey Zigachev adev->gfx.config.double_offchip_lds_buf;
632b843c749SSergey Zigachev
633b843c749SSergey Zigachev if (amdgpu_ngg) {
634b843c749SSergey Zigachev dev_info.prim_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PRIM].gpu_addr;
635b843c749SSergey Zigachev dev_info.prim_buf_size = adev->gfx.ngg.buf[NGG_PRIM].size;
636b843c749SSergey Zigachev dev_info.pos_buf_gpu_addr = adev->gfx.ngg.buf[NGG_POS].gpu_addr;
637b843c749SSergey Zigachev dev_info.pos_buf_size = adev->gfx.ngg.buf[NGG_POS].size;
638b843c749SSergey Zigachev dev_info.cntl_sb_buf_gpu_addr = adev->gfx.ngg.buf[NGG_CNTL].gpu_addr;
639b843c749SSergey Zigachev dev_info.cntl_sb_buf_size = adev->gfx.ngg.buf[NGG_CNTL].size;
640b843c749SSergey Zigachev dev_info.param_buf_gpu_addr = adev->gfx.ngg.buf[NGG_PARAM].gpu_addr;
641b843c749SSergey Zigachev dev_info.param_buf_size = adev->gfx.ngg.buf[NGG_PARAM].size;
642b843c749SSergey Zigachev }
643b843c749SSergey Zigachev dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
644b843c749SSergey Zigachev dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
645b843c749SSergey Zigachev dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
646b843c749SSergey Zigachev dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
647b843c749SSergey Zigachev dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
648b843c749SSergey Zigachev dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
649b843c749SSergey Zigachev dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
650b843c749SSergey Zigachev
651b843c749SSergey Zigachev return copy_to_user(out, &dev_info,
652b843c749SSergey Zigachev min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
653b843c749SSergey Zigachev }
654b843c749SSergey Zigachev case AMDGPU_INFO_VCE_CLOCK_TABLE: {
655b843c749SSergey Zigachev unsigned i;
656b843c749SSergey Zigachev struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
657b843c749SSergey Zigachev struct amd_vce_state *vce_state;
658b843c749SSergey Zigachev
659b843c749SSergey Zigachev for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
660b843c749SSergey Zigachev vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
661b843c749SSergey Zigachev if (vce_state) {
662b843c749SSergey Zigachev vce_clk_table.entries[i].sclk = vce_state->sclk;
663b843c749SSergey Zigachev vce_clk_table.entries[i].mclk = vce_state->mclk;
664b843c749SSergey Zigachev vce_clk_table.entries[i].eclk = vce_state->evclk;
665b843c749SSergey Zigachev vce_clk_table.num_valid_entries++;
666b843c749SSergey Zigachev }
667b843c749SSergey Zigachev }
668b843c749SSergey Zigachev
669b843c749SSergey Zigachev return copy_to_user(out, &vce_clk_table,
670b843c749SSergey Zigachev min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
671b843c749SSergey Zigachev }
672b843c749SSergey Zigachev case AMDGPU_INFO_VBIOS: {
673b843c749SSergey Zigachev uint32_t bios_size = adev->bios_size;
674b843c749SSergey Zigachev
675b843c749SSergey Zigachev switch (info->vbios_info.type) {
676b843c749SSergey Zigachev case AMDGPU_INFO_VBIOS_SIZE:
677b843c749SSergey Zigachev return copy_to_user(out, &bios_size,
678b843c749SSergey Zigachev min((size_t)size, sizeof(bios_size)))
679b843c749SSergey Zigachev ? -EFAULT : 0;
680b843c749SSergey Zigachev case AMDGPU_INFO_VBIOS_IMAGE: {
681b843c749SSergey Zigachev uint8_t *bios;
682b843c749SSergey Zigachev uint32_t bios_offset = info->vbios_info.offset;
683b843c749SSergey Zigachev
684b843c749SSergey Zigachev if (bios_offset >= bios_size)
685b843c749SSergey Zigachev return -EINVAL;
686b843c749SSergey Zigachev
687b843c749SSergey Zigachev bios = adev->bios + bios_offset;
688b843c749SSergey Zigachev return copy_to_user(out, bios,
689b843c749SSergey Zigachev min((size_t)size, (size_t)(bios_size - bios_offset)))
690b843c749SSergey Zigachev ? -EFAULT : 0;
691b843c749SSergey Zigachev }
692b843c749SSergey Zigachev default:
693b843c749SSergey Zigachev DRM_DEBUG_KMS("Invalid request %d\n",
694b843c749SSergey Zigachev info->vbios_info.type);
695b843c749SSergey Zigachev return -EINVAL;
696b843c749SSergey Zigachev }
697b843c749SSergey Zigachev }
698b843c749SSergey Zigachev case AMDGPU_INFO_NUM_HANDLES: {
699b843c749SSergey Zigachev struct drm_amdgpu_info_num_handles handle;
700b843c749SSergey Zigachev
701b843c749SSergey Zigachev switch (info->query_hw_ip.type) {
702b843c749SSergey Zigachev case AMDGPU_HW_IP_UVD:
703b843c749SSergey Zigachev /* Starting Polaris, we support unlimited UVD handles */
704b843c749SSergey Zigachev if (adev->asic_type < CHIP_POLARIS10) {
705b843c749SSergey Zigachev handle.uvd_max_handles = adev->uvd.max_handles;
706b843c749SSergey Zigachev handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
707b843c749SSergey Zigachev
708b843c749SSergey Zigachev return copy_to_user(out, &handle,
709b843c749SSergey Zigachev min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
710b843c749SSergey Zigachev } else {
711b843c749SSergey Zigachev return -ENODATA;
712b843c749SSergey Zigachev }
713b843c749SSergey Zigachev
714b843c749SSergey Zigachev break;
715b843c749SSergey Zigachev default:
716b843c749SSergey Zigachev return -EINVAL;
717b843c749SSergey Zigachev }
718b843c749SSergey Zigachev }
719b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR: {
720b843c749SSergey Zigachev if (!adev->pm.dpm_enabled)
721b843c749SSergey Zigachev return -ENOENT;
722b843c749SSergey Zigachev
723b843c749SSergey Zigachev switch (info->sensor_info.type) {
724b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR_GFX_SCLK:
725b843c749SSergey Zigachev /* get sclk in Mhz */
726b843c749SSergey Zigachev if (amdgpu_dpm_read_sensor(adev,
727b843c749SSergey Zigachev AMDGPU_PP_SENSOR_GFX_SCLK,
728b843c749SSergey Zigachev (void *)&ui32, &ui32_size)) {
729b843c749SSergey Zigachev return -EINVAL;
730b843c749SSergey Zigachev }
731b843c749SSergey Zigachev ui32 /= 100;
732b843c749SSergey Zigachev break;
733b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR_GFX_MCLK:
734b843c749SSergey Zigachev /* get mclk in Mhz */
735b843c749SSergey Zigachev if (amdgpu_dpm_read_sensor(adev,
736b843c749SSergey Zigachev AMDGPU_PP_SENSOR_GFX_MCLK,
737b843c749SSergey Zigachev (void *)&ui32, &ui32_size)) {
738b843c749SSergey Zigachev return -EINVAL;
739b843c749SSergey Zigachev }
740b843c749SSergey Zigachev ui32 /= 100;
741b843c749SSergey Zigachev break;
742b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR_GPU_TEMP:
743b843c749SSergey Zigachev /* get temperature in millidegrees C */
744b843c749SSergey Zigachev if (amdgpu_dpm_read_sensor(adev,
745b843c749SSergey Zigachev AMDGPU_PP_SENSOR_GPU_TEMP,
746b843c749SSergey Zigachev (void *)&ui32, &ui32_size)) {
747b843c749SSergey Zigachev return -EINVAL;
748b843c749SSergey Zigachev }
749b843c749SSergey Zigachev break;
750b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR_GPU_LOAD:
751b843c749SSergey Zigachev /* get GPU load */
752b843c749SSergey Zigachev if (amdgpu_dpm_read_sensor(adev,
753b843c749SSergey Zigachev AMDGPU_PP_SENSOR_GPU_LOAD,
754b843c749SSergey Zigachev (void *)&ui32, &ui32_size)) {
755b843c749SSergey Zigachev return -EINVAL;
756b843c749SSergey Zigachev }
757b843c749SSergey Zigachev break;
758b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
759b843c749SSergey Zigachev /* get average GPU power */
760b843c749SSergey Zigachev if (amdgpu_dpm_read_sensor(adev,
761b843c749SSergey Zigachev AMDGPU_PP_SENSOR_GPU_POWER,
762b843c749SSergey Zigachev (void *)&ui32, &ui32_size)) {
763b843c749SSergey Zigachev return -EINVAL;
764b843c749SSergey Zigachev }
765b843c749SSergey Zigachev ui32 >>= 8;
766b843c749SSergey Zigachev break;
767b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR_VDDNB:
768b843c749SSergey Zigachev /* get VDDNB in millivolts */
769b843c749SSergey Zigachev if (amdgpu_dpm_read_sensor(adev,
770b843c749SSergey Zigachev AMDGPU_PP_SENSOR_VDDNB,
771b843c749SSergey Zigachev (void *)&ui32, &ui32_size)) {
772b843c749SSergey Zigachev return -EINVAL;
773b843c749SSergey Zigachev }
774b843c749SSergey Zigachev break;
775b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR_VDDGFX:
776b843c749SSergey Zigachev /* get VDDGFX in millivolts */
777b843c749SSergey Zigachev if (amdgpu_dpm_read_sensor(adev,
778b843c749SSergey Zigachev AMDGPU_PP_SENSOR_VDDGFX,
779b843c749SSergey Zigachev (void *)&ui32, &ui32_size)) {
780b843c749SSergey Zigachev return -EINVAL;
781b843c749SSergey Zigachev }
782b843c749SSergey Zigachev break;
783b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
784b843c749SSergey Zigachev /* get stable pstate sclk in Mhz */
785b843c749SSergey Zigachev if (amdgpu_dpm_read_sensor(adev,
786b843c749SSergey Zigachev AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
787b843c749SSergey Zigachev (void *)&ui32, &ui32_size)) {
788b843c749SSergey Zigachev return -EINVAL;
789b843c749SSergey Zigachev }
790b843c749SSergey Zigachev ui32 /= 100;
791b843c749SSergey Zigachev break;
792b843c749SSergey Zigachev case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
793b843c749SSergey Zigachev /* get stable pstate mclk in Mhz */
794b843c749SSergey Zigachev if (amdgpu_dpm_read_sensor(adev,
795b843c749SSergey Zigachev AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
796b843c749SSergey Zigachev (void *)&ui32, &ui32_size)) {
797b843c749SSergey Zigachev return -EINVAL;
798b843c749SSergey Zigachev }
799b843c749SSergey Zigachev ui32 /= 100;
800b843c749SSergey Zigachev break;
801b843c749SSergey Zigachev default:
802b843c749SSergey Zigachev DRM_DEBUG_KMS("Invalid request %d\n",
803b843c749SSergey Zigachev info->sensor_info.type);
804b843c749SSergey Zigachev return -EINVAL;
805b843c749SSergey Zigachev }
806b843c749SSergey Zigachev return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
807b843c749SSergey Zigachev }
808b843c749SSergey Zigachev case AMDGPU_INFO_VRAM_LOST_COUNTER:
809b843c749SSergey Zigachev ui32 = atomic_read(&adev->vram_lost_counter);
810b843c749SSergey Zigachev return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
811b843c749SSergey Zigachev default:
812b843c749SSergey Zigachev DRM_DEBUG_KMS("Invalid request %d\n", info->query);
813b843c749SSergey Zigachev return -EINVAL;
814b843c749SSergey Zigachev }
815b843c749SSergey Zigachev return 0;
816b843c749SSergey Zigachev }
817b843c749SSergey Zigachev
818b843c749SSergey Zigachev
819b843c749SSergey Zigachev /*
820b843c749SSergey Zigachev * Outdated mess for old drm with Xorg being in charge (void function now).
821b843c749SSergey Zigachev */
822b843c749SSergey Zigachev /**
823b843c749SSergey Zigachev * amdgpu_driver_lastclose_kms - drm callback for last close
824b843c749SSergey Zigachev *
825b843c749SSergey Zigachev * @dev: drm dev pointer
826b843c749SSergey Zigachev *
827b843c749SSergey Zigachev * Switch vga_switcheroo state after last close (all asics).
828b843c749SSergey Zigachev */
amdgpu_driver_lastclose_kms(struct drm_device * dev)829b843c749SSergey Zigachev void amdgpu_driver_lastclose_kms(struct drm_device *dev)
830b843c749SSergey Zigachev {
831*78973132SSergey Zigachev #if 0
832*78973132SSergey Zigachev // empty function as of 4.19
833b843c749SSergey Zigachev drm_fb_helper_lastclose(dev);
834*78973132SSergey Zigachev #endif
835b843c749SSergey Zigachev vga_switcheroo_process_delayed_switch();
836b843c749SSergey Zigachev }
837b843c749SSergey Zigachev
838b843c749SSergey Zigachev /**
839b843c749SSergey Zigachev * amdgpu_driver_open_kms - drm callback for open
840b843c749SSergey Zigachev *
841b843c749SSergey Zigachev * @dev: drm dev pointer
842b843c749SSergey Zigachev * @file_priv: drm file
843b843c749SSergey Zigachev *
844b843c749SSergey Zigachev * On device open, init vm on cayman+ (all asics).
845b843c749SSergey Zigachev * Returns 0 on success, error on failure.
846b843c749SSergey Zigachev */
amdgpu_driver_open_kms(struct drm_device * dev,struct drm_file * file_priv)847b843c749SSergey Zigachev int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
848b843c749SSergey Zigachev {
849b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
850b843c749SSergey Zigachev struct amdgpu_fpriv *fpriv;
851b843c749SSergey Zigachev int r, pasid;
852b843c749SSergey Zigachev
853b843c749SSergey Zigachev /* Ensure IB tests are run on ring */
854b843c749SSergey Zigachev flush_delayed_work(&adev->late_init_work);
855b843c749SSergey Zigachev
856b843c749SSergey Zigachev file_priv->driver_priv = NULL;
857b843c749SSergey Zigachev
858*78973132SSergey Zigachev #if 0
859b843c749SSergey Zigachev r = pm_runtime_get_sync(dev->dev);
860b843c749SSergey Zigachev if (r < 0)
861b843c749SSergey Zigachev goto pm_put;
862*78973132SSergey Zigachev #endif
863b843c749SSergey Zigachev
864b843c749SSergey Zigachev fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
865b843c749SSergey Zigachev if (unlikely(!fpriv)) {
866b843c749SSergey Zigachev r = -ENOMEM;
867b843c749SSergey Zigachev goto out_suspend;
868b843c749SSergey Zigachev }
869b843c749SSergey Zigachev
870b843c749SSergey Zigachev pasid = amdgpu_pasid_alloc(16);
871b843c749SSergey Zigachev if (pasid < 0) {
872b843c749SSergey Zigachev dev_warn(adev->dev, "No more PASIDs available!");
873b843c749SSergey Zigachev pasid = 0;
874b843c749SSergey Zigachev }
875b843c749SSergey Zigachev r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
876b843c749SSergey Zigachev if (r)
877b843c749SSergey Zigachev goto error_pasid;
878b843c749SSergey Zigachev
879b843c749SSergey Zigachev fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
880b843c749SSergey Zigachev if (!fpriv->prt_va) {
881b843c749SSergey Zigachev r = -ENOMEM;
882b843c749SSergey Zigachev goto error_vm;
883b843c749SSergey Zigachev }
884b843c749SSergey Zigachev
885b843c749SSergey Zigachev if (amdgpu_sriov_vf(adev)) {
886b843c749SSergey Zigachev r = amdgpu_map_static_csa(adev, &fpriv->vm, &fpriv->csa_va);
887b843c749SSergey Zigachev if (r)
888b843c749SSergey Zigachev goto error_vm;
889b843c749SSergey Zigachev }
890b843c749SSergey Zigachev
891*78973132SSergey Zigachev lockinit(&fpriv->bo_list_lock, "agfbll", 0, LK_CANRECURSE);
892b843c749SSergey Zigachev idr_init(&fpriv->bo_list_handles);
893b843c749SSergey Zigachev
894b843c749SSergey Zigachev amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
895b843c749SSergey Zigachev
896b843c749SSergey Zigachev file_priv->driver_priv = fpriv;
897b843c749SSergey Zigachev goto out_suspend;
898b843c749SSergey Zigachev
899b843c749SSergey Zigachev error_vm:
900b843c749SSergey Zigachev amdgpu_vm_fini(adev, &fpriv->vm);
901b843c749SSergey Zigachev
902b843c749SSergey Zigachev error_pasid:
903b843c749SSergey Zigachev if (pasid)
904b843c749SSergey Zigachev amdgpu_pasid_free(pasid);
905b843c749SSergey Zigachev
906b843c749SSergey Zigachev kfree(fpriv);
907b843c749SSergey Zigachev
908b843c749SSergey Zigachev out_suspend:
909b843c749SSergey Zigachev pm_runtime_mark_last_busy(dev->dev);
910*78973132SSergey Zigachev #if 0
911b843c749SSergey Zigachev pm_put:
912b843c749SSergey Zigachev pm_runtime_put_autosuspend(dev->dev);
913*78973132SSergey Zigachev #endif
914b843c749SSergey Zigachev
915b843c749SSergey Zigachev return r;
916b843c749SSergey Zigachev }
917b843c749SSergey Zigachev
918b843c749SSergey Zigachev /**
919b843c749SSergey Zigachev * amdgpu_driver_postclose_kms - drm callback for post close
920b843c749SSergey Zigachev *
921b843c749SSergey Zigachev * @dev: drm dev pointer
922b843c749SSergey Zigachev * @file_priv: drm file
923b843c749SSergey Zigachev *
924b843c749SSergey Zigachev * On device post close, tear down vm on cayman+ (all asics).
925b843c749SSergey Zigachev */
amdgpu_driver_postclose_kms(struct drm_device * dev,struct drm_file * file_priv)926b843c749SSergey Zigachev void amdgpu_driver_postclose_kms(struct drm_device *dev,
927b843c749SSergey Zigachev struct drm_file *file_priv)
928b843c749SSergey Zigachev {
929b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
930b843c749SSergey Zigachev struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
931b843c749SSergey Zigachev struct amdgpu_bo_list *list;
932b843c749SSergey Zigachev struct amdgpu_bo *pd;
933b843c749SSergey Zigachev unsigned int pasid;
934b843c749SSergey Zigachev int handle;
935b843c749SSergey Zigachev
936b843c749SSergey Zigachev if (!fpriv)
937b843c749SSergey Zigachev return;
938b843c749SSergey Zigachev
939b843c749SSergey Zigachev pm_runtime_get_sync(dev->dev);
940b843c749SSergey Zigachev
941b843c749SSergey Zigachev if (adev->asic_type != CHIP_RAVEN) {
942b843c749SSergey Zigachev amdgpu_uvd_free_handles(adev, file_priv);
943b843c749SSergey Zigachev amdgpu_vce_free_handles(adev, file_priv);
944b843c749SSergey Zigachev }
945b843c749SSergey Zigachev
946b843c749SSergey Zigachev amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
947b843c749SSergey Zigachev
948b843c749SSergey Zigachev if (amdgpu_sriov_vf(adev)) {
949b843c749SSergey Zigachev /* TODO: how to handle reserve failure */
950b843c749SSergey Zigachev BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
951b843c749SSergey Zigachev amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
952b843c749SSergey Zigachev fpriv->csa_va = NULL;
953b843c749SSergey Zigachev amdgpu_bo_unreserve(adev->virt.csa_obj);
954b843c749SSergey Zigachev }
955b843c749SSergey Zigachev
956b843c749SSergey Zigachev pasid = fpriv->vm.pasid;
957b843c749SSergey Zigachev pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
958b843c749SSergey Zigachev
959b843c749SSergey Zigachev amdgpu_vm_fini(adev, &fpriv->vm);
960b843c749SSergey Zigachev amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
961b843c749SSergey Zigachev
962b843c749SSergey Zigachev if (pasid)
963b843c749SSergey Zigachev amdgpu_pasid_free_delayed(pd->tbo.resv, pasid);
964b843c749SSergey Zigachev amdgpu_bo_unref(&pd);
965b843c749SSergey Zigachev
966b843c749SSergey Zigachev idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
967b843c749SSergey Zigachev amdgpu_bo_list_put(list);
968b843c749SSergey Zigachev
969b843c749SSergey Zigachev idr_destroy(&fpriv->bo_list_handles);
970b843c749SSergey Zigachev mutex_destroy(&fpriv->bo_list_lock);
971b843c749SSergey Zigachev
972b843c749SSergey Zigachev kfree(fpriv);
973b843c749SSergey Zigachev file_priv->driver_priv = NULL;
974b843c749SSergey Zigachev
975b843c749SSergey Zigachev pm_runtime_mark_last_busy(dev->dev);
976b843c749SSergey Zigachev pm_runtime_put_autosuspend(dev->dev);
977b843c749SSergey Zigachev }
978b843c749SSergey Zigachev
979b843c749SSergey Zigachev /*
980b843c749SSergey Zigachev * VBlank related functions.
981b843c749SSergey Zigachev */
982b843c749SSergey Zigachev /**
983b843c749SSergey Zigachev * amdgpu_get_vblank_counter_kms - get frame count
984b843c749SSergey Zigachev *
985b843c749SSergey Zigachev * @dev: drm dev pointer
986b843c749SSergey Zigachev * @pipe: crtc to get the frame count from
987b843c749SSergey Zigachev *
988b843c749SSergey Zigachev * Gets the frame count on the requested crtc (all asics).
989b843c749SSergey Zigachev * Returns frame count on success, -EINVAL on failure.
990b843c749SSergey Zigachev */
amdgpu_get_vblank_counter_kms(struct drm_device * dev,unsigned int pipe)991b843c749SSergey Zigachev u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
992b843c749SSergey Zigachev {
993b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
994b843c749SSergey Zigachev int vpos, hpos, stat;
995b843c749SSergey Zigachev u32 count;
996b843c749SSergey Zigachev
997b843c749SSergey Zigachev if (pipe >= adev->mode_info.num_crtc) {
998b843c749SSergey Zigachev DRM_ERROR("Invalid crtc %u\n", pipe);
999b843c749SSergey Zigachev return -EINVAL;
1000b843c749SSergey Zigachev }
1001b843c749SSergey Zigachev
1002b843c749SSergey Zigachev /* The hw increments its frame counter at start of vsync, not at start
1003b843c749SSergey Zigachev * of vblank, as is required by DRM core vblank counter handling.
1004b843c749SSergey Zigachev * Cook the hw count here to make it appear to the caller as if it
1005b843c749SSergey Zigachev * incremented at start of vblank. We measure distance to start of
1006b843c749SSergey Zigachev * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1007b843c749SSergey Zigachev * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1008b843c749SSergey Zigachev * result by 1 to give the proper appearance to caller.
1009b843c749SSergey Zigachev */
1010b843c749SSergey Zigachev if (adev->mode_info.crtcs[pipe]) {
1011b843c749SSergey Zigachev /* Repeat readout if needed to provide stable result if
1012b843c749SSergey Zigachev * we cross start of vsync during the queries.
1013b843c749SSergey Zigachev */
1014b843c749SSergey Zigachev do {
1015b843c749SSergey Zigachev count = amdgpu_display_vblank_get_counter(adev, pipe);
1016b843c749SSergey Zigachev /* Ask amdgpu_display_get_crtc_scanoutpos to return
1017b843c749SSergey Zigachev * vpos as distance to start of vblank, instead of
1018b843c749SSergey Zigachev * regular vertical scanout pos.
1019b843c749SSergey Zigachev */
1020b843c749SSergey Zigachev stat = amdgpu_display_get_crtc_scanoutpos(
1021b843c749SSergey Zigachev dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1022b843c749SSergey Zigachev &vpos, &hpos, NULL, NULL,
1023b843c749SSergey Zigachev &adev->mode_info.crtcs[pipe]->base.hwmode);
1024b843c749SSergey Zigachev } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1025b843c749SSergey Zigachev
1026b843c749SSergey Zigachev if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1027b843c749SSergey Zigachev (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1028b843c749SSergey Zigachev DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1029b843c749SSergey Zigachev } else {
1030b843c749SSergey Zigachev DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1031b843c749SSergey Zigachev pipe, vpos);
1032b843c749SSergey Zigachev
1033b843c749SSergey Zigachev /* Bump counter if we are at >= leading edge of vblank,
1034b843c749SSergey Zigachev * but before vsync where vpos would turn negative and
1035b843c749SSergey Zigachev * the hw counter really increments.
1036b843c749SSergey Zigachev */
1037b843c749SSergey Zigachev if (vpos >= 0)
1038b843c749SSergey Zigachev count++;
1039b843c749SSergey Zigachev }
1040b843c749SSergey Zigachev } else {
1041b843c749SSergey Zigachev /* Fallback to use value as is. */
1042b843c749SSergey Zigachev count = amdgpu_display_vblank_get_counter(adev, pipe);
1043b843c749SSergey Zigachev DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1044b843c749SSergey Zigachev }
1045b843c749SSergey Zigachev
1046b843c749SSergey Zigachev return count;
1047b843c749SSergey Zigachev }
1048b843c749SSergey Zigachev
1049b843c749SSergey Zigachev /**
1050b843c749SSergey Zigachev * amdgpu_enable_vblank_kms - enable vblank interrupt
1051b843c749SSergey Zigachev *
1052b843c749SSergey Zigachev * @dev: drm dev pointer
1053b843c749SSergey Zigachev * @pipe: crtc to enable vblank interrupt for
1054b843c749SSergey Zigachev *
1055b843c749SSergey Zigachev * Enable the interrupt on the requested crtc (all asics).
1056b843c749SSergey Zigachev * Returns 0 on success, -EINVAL on failure.
1057b843c749SSergey Zigachev */
amdgpu_enable_vblank_kms(struct drm_device * dev,unsigned int pipe)1058b843c749SSergey Zigachev int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1059b843c749SSergey Zigachev {
1060b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
1061b843c749SSergey Zigachev int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1062b843c749SSergey Zigachev
1063b843c749SSergey Zigachev return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1064b843c749SSergey Zigachev }
1065b843c749SSergey Zigachev
1066b843c749SSergey Zigachev /**
1067b843c749SSergey Zigachev * amdgpu_disable_vblank_kms - disable vblank interrupt
1068b843c749SSergey Zigachev *
1069b843c749SSergey Zigachev * @dev: drm dev pointer
1070b843c749SSergey Zigachev * @pipe: crtc to disable vblank interrupt for
1071b843c749SSergey Zigachev *
1072b843c749SSergey Zigachev * Disable the interrupt on the requested crtc (all asics).
1073b843c749SSergey Zigachev */
amdgpu_disable_vblank_kms(struct drm_device * dev,unsigned int pipe)1074b843c749SSergey Zigachev void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
1075b843c749SSergey Zigachev {
1076b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
1077b843c749SSergey Zigachev int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1078b843c749SSergey Zigachev
1079b843c749SSergey Zigachev amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1080b843c749SSergey Zigachev }
1081b843c749SSergey Zigachev
1082b843c749SSergey Zigachev const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1083b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1084b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1085b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1086b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1087b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1088b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1089b843c749SSergey Zigachev /* KMS */
1090b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1091b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1092b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1093b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1094b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1095b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1096b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1097b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1098b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1099b843c749SSergey Zigachev DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1100b843c749SSergey Zigachev };
1101b843c749SSergey Zigachev const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1102b843c749SSergey Zigachev
1103b843c749SSergey Zigachev /*
1104b843c749SSergey Zigachev * Debugfs info
1105b843c749SSergey Zigachev */
1106b843c749SSergey Zigachev #if defined(CONFIG_DEBUG_FS)
1107b843c749SSergey Zigachev
amdgpu_debugfs_firmware_info(struct seq_file * m,void * data)1108b843c749SSergey Zigachev static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1109b843c749SSergey Zigachev {
1110b843c749SSergey Zigachev struct drm_info_node *node = (struct drm_info_node *) m->private;
1111b843c749SSergey Zigachev struct drm_device *dev = node->minor->dev;
1112b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private;
1113b843c749SSergey Zigachev struct drm_amdgpu_info_firmware fw_info;
1114b843c749SSergey Zigachev struct drm_amdgpu_query_fw query_fw;
1115b843c749SSergey Zigachev struct atom_context *ctx = adev->mode_info.atom_context;
1116b843c749SSergey Zigachev int ret, i;
1117b843c749SSergey Zigachev
1118b843c749SSergey Zigachev /* VCE */
1119b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1120b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1121b843c749SSergey Zigachev if (ret)
1122b843c749SSergey Zigachev return ret;
1123b843c749SSergey Zigachev seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1124b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1125b843c749SSergey Zigachev
1126b843c749SSergey Zigachev /* UVD */
1127b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1128b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1129b843c749SSergey Zigachev if (ret)
1130b843c749SSergey Zigachev return ret;
1131b843c749SSergey Zigachev seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1132b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1133b843c749SSergey Zigachev
1134b843c749SSergey Zigachev /* GMC */
1135b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1136b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1137b843c749SSergey Zigachev if (ret)
1138b843c749SSergey Zigachev return ret;
1139b843c749SSergey Zigachev seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1140b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1141b843c749SSergey Zigachev
1142b843c749SSergey Zigachev /* ME */
1143b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1144b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1145b843c749SSergey Zigachev if (ret)
1146b843c749SSergey Zigachev return ret;
1147b843c749SSergey Zigachev seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1148b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1149b843c749SSergey Zigachev
1150b843c749SSergey Zigachev /* PFP */
1151b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1152b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1153b843c749SSergey Zigachev if (ret)
1154b843c749SSergey Zigachev return ret;
1155b843c749SSergey Zigachev seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1156b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1157b843c749SSergey Zigachev
1158b843c749SSergey Zigachev /* CE */
1159b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1160b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1161b843c749SSergey Zigachev if (ret)
1162b843c749SSergey Zigachev return ret;
1163b843c749SSergey Zigachev seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1164b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1165b843c749SSergey Zigachev
1166b843c749SSergey Zigachev /* RLC */
1167b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1168b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1169b843c749SSergey Zigachev if (ret)
1170b843c749SSergey Zigachev return ret;
1171b843c749SSergey Zigachev seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1172b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1173b843c749SSergey Zigachev
1174b843c749SSergey Zigachev /* RLC SAVE RESTORE LIST CNTL */
1175b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1176b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1177b843c749SSergey Zigachev if (ret)
1178b843c749SSergey Zigachev return ret;
1179b843c749SSergey Zigachev seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1180b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1181b843c749SSergey Zigachev
1182b843c749SSergey Zigachev /* RLC SAVE RESTORE LIST GPM MEM */
1183b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1184b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1185b843c749SSergey Zigachev if (ret)
1186b843c749SSergey Zigachev return ret;
1187b843c749SSergey Zigachev seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1188b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1189b843c749SSergey Zigachev
1190b843c749SSergey Zigachev /* RLC SAVE RESTORE LIST SRM MEM */
1191b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1192b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1193b843c749SSergey Zigachev if (ret)
1194b843c749SSergey Zigachev return ret;
1195b843c749SSergey Zigachev seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1196b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1197b843c749SSergey Zigachev
1198b843c749SSergey Zigachev /* MEC */
1199b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1200b843c749SSergey Zigachev query_fw.index = 0;
1201b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1202b843c749SSergey Zigachev if (ret)
1203b843c749SSergey Zigachev return ret;
1204b843c749SSergey Zigachev seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1205b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1206b843c749SSergey Zigachev
1207b843c749SSergey Zigachev /* MEC2 */
1208b843c749SSergey Zigachev if (adev->asic_type == CHIP_KAVERI ||
1209b843c749SSergey Zigachev (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) {
1210b843c749SSergey Zigachev query_fw.index = 1;
1211b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1212b843c749SSergey Zigachev if (ret)
1213b843c749SSergey Zigachev return ret;
1214b843c749SSergey Zigachev seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1215b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1216b843c749SSergey Zigachev }
1217b843c749SSergey Zigachev
1218b843c749SSergey Zigachev /* PSP SOS */
1219b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1220b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1221b843c749SSergey Zigachev if (ret)
1222b843c749SSergey Zigachev return ret;
1223b843c749SSergey Zigachev seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1224b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1225b843c749SSergey Zigachev
1226b843c749SSergey Zigachev
1227b843c749SSergey Zigachev /* PSP ASD */
1228b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1229b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1230b843c749SSergey Zigachev if (ret)
1231b843c749SSergey Zigachev return ret;
1232b843c749SSergey Zigachev seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1233b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1234b843c749SSergey Zigachev
1235b843c749SSergey Zigachev /* SMC */
1236b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1237b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1238b843c749SSergey Zigachev if (ret)
1239b843c749SSergey Zigachev return ret;
1240b843c749SSergey Zigachev seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1241b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1242b843c749SSergey Zigachev
1243b843c749SSergey Zigachev /* SDMA */
1244b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1245b843c749SSergey Zigachev for (i = 0; i < adev->sdma.num_instances; i++) {
1246b843c749SSergey Zigachev query_fw.index = i;
1247b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1248b843c749SSergey Zigachev if (ret)
1249b843c749SSergey Zigachev return ret;
1250b843c749SSergey Zigachev seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1251b843c749SSergey Zigachev i, fw_info.feature, fw_info.ver);
1252b843c749SSergey Zigachev }
1253b843c749SSergey Zigachev
1254b843c749SSergey Zigachev /* VCN */
1255b843c749SSergey Zigachev query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1256b843c749SSergey Zigachev ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1257b843c749SSergey Zigachev if (ret)
1258b843c749SSergey Zigachev return ret;
1259b843c749SSergey Zigachev seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1260b843c749SSergey Zigachev fw_info.feature, fw_info.ver);
1261b843c749SSergey Zigachev
1262b843c749SSergey Zigachev
1263b843c749SSergey Zigachev seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1264b843c749SSergey Zigachev
1265b843c749SSergey Zigachev return 0;
1266b843c749SSergey Zigachev }
1267b843c749SSergey Zigachev
1268b843c749SSergey Zigachev static const struct drm_info_list amdgpu_firmware_info_list[] = {
1269b843c749SSergey Zigachev {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1270b843c749SSergey Zigachev };
1271b843c749SSergey Zigachev #endif
1272b843c749SSergey Zigachev
amdgpu_debugfs_firmware_init(struct amdgpu_device * adev)1273b843c749SSergey Zigachev int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1274b843c749SSergey Zigachev {
1275b843c749SSergey Zigachev #if defined(CONFIG_DEBUG_FS)
1276b843c749SSergey Zigachev return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1277b843c749SSergey Zigachev ARRAY_SIZE(amdgpu_firmware_info_list));
1278b843c749SSergey Zigachev #else
1279b843c749SSergey Zigachev return 0;
1280b843c749SSergey Zigachev #endif
1281b843c749SSergey Zigachev }
1282