1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2014 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef __AMDGPU_IRQ_H__ 25*b843c749SSergey Zigachev #define __AMDGPU_IRQ_H__ 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include <linux/irqdomain.h> 28*b843c749SSergey Zigachev #include "amdgpu_ih.h" 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define AMDGPU_MAX_IRQ_SRC_ID 0x100 31*b843c749SSergey Zigachev #define AMDGPU_MAX_IRQ_CLIENT_ID 0x100 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev struct amdgpu_device; 34*b843c749SSergey Zigachev struct amdgpu_iv_entry; 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev enum amdgpu_interrupt_state { 37*b843c749SSergey Zigachev AMDGPU_IRQ_STATE_DISABLE, 38*b843c749SSergey Zigachev AMDGPU_IRQ_STATE_ENABLE, 39*b843c749SSergey Zigachev }; 40*b843c749SSergey Zigachev 41*b843c749SSergey Zigachev struct amdgpu_irq_src { 42*b843c749SSergey Zigachev unsigned num_types; 43*b843c749SSergey Zigachev atomic_t *enabled_types; 44*b843c749SSergey Zigachev const struct amdgpu_irq_src_funcs *funcs; 45*b843c749SSergey Zigachev void *data; 46*b843c749SSergey Zigachev }; 47*b843c749SSergey Zigachev 48*b843c749SSergey Zigachev struct amdgpu_irq_client { 49*b843c749SSergey Zigachev struct amdgpu_irq_src **sources; 50*b843c749SSergey Zigachev }; 51*b843c749SSergey Zigachev 52*b843c749SSergey Zigachev /* provided by interrupt generating IP blocks */ 53*b843c749SSergey Zigachev struct amdgpu_irq_src_funcs { 54*b843c749SSergey Zigachev int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 55*b843c749SSergey Zigachev unsigned type, enum amdgpu_interrupt_state state); 56*b843c749SSergey Zigachev 57*b843c749SSergey Zigachev int (*process)(struct amdgpu_device *adev, 58*b843c749SSergey Zigachev struct amdgpu_irq_src *source, 59*b843c749SSergey Zigachev struct amdgpu_iv_entry *entry); 60*b843c749SSergey Zigachev }; 61*b843c749SSergey Zigachev 62*b843c749SSergey Zigachev struct amdgpu_irq { 63*b843c749SSergey Zigachev bool installed; 64*b843c749SSergey Zigachev spinlock_t lock; 65*b843c749SSergey Zigachev /* interrupt sources */ 66*b843c749SSergey Zigachev struct amdgpu_irq_client client[AMDGPU_IH_CLIENTID_MAX]; 67*b843c749SSergey Zigachev 68*b843c749SSergey Zigachev /* status, etc. */ 69*b843c749SSergey Zigachev bool msi_enabled; /* msi enabled */ 70*b843c749SSergey Zigachev 71*b843c749SSergey Zigachev /* interrupt ring */ 72*b843c749SSergey Zigachev struct amdgpu_ih_ring ih; 73*b843c749SSergey Zigachev const struct amdgpu_ih_funcs *ih_funcs; 74*b843c749SSergey Zigachev 75*b843c749SSergey Zigachev /* gen irq stuff */ 76*b843c749SSergey Zigachev struct irq_domain *domain; /* GPU irq controller domain */ 77*b843c749SSergey Zigachev unsigned virq[AMDGPU_MAX_IRQ_SRC_ID]; 78*b843c749SSergey Zigachev uint32_t srbm_soft_reset; 79*b843c749SSergey Zigachev }; 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev void amdgpu_irq_disable_all(struct amdgpu_device *adev); 82*b843c749SSergey Zigachev irqreturn_t amdgpu_irq_handler(int irq, void *arg); 83*b843c749SSergey Zigachev 84*b843c749SSergey Zigachev int amdgpu_irq_init(struct amdgpu_device *adev); 85*b843c749SSergey Zigachev void amdgpu_irq_fini(struct amdgpu_device *adev); 86*b843c749SSergey Zigachev int amdgpu_irq_add_id(struct amdgpu_device *adev, 87*b843c749SSergey Zigachev unsigned client_id, unsigned src_id, 88*b843c749SSergey Zigachev struct amdgpu_irq_src *source); 89*b843c749SSergey Zigachev void amdgpu_irq_dispatch(struct amdgpu_device *adev, 90*b843c749SSergey Zigachev struct amdgpu_iv_entry *entry); 91*b843c749SSergey Zigachev int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 92*b843c749SSergey Zigachev unsigned type); 93*b843c749SSergey Zigachev int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 94*b843c749SSergey Zigachev unsigned type); 95*b843c749SSergey Zigachev int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 96*b843c749SSergey Zigachev unsigned type); 97*b843c749SSergey Zigachev bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 98*b843c749SSergey Zigachev unsigned type); 99*b843c749SSergey Zigachev void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev); 100*b843c749SSergey Zigachev 101*b843c749SSergey Zigachev int amdgpu_irq_add_domain(struct amdgpu_device *adev); 102*b843c749SSergey Zigachev void amdgpu_irq_remove_domain(struct amdgpu_device *adev); 103*b843c749SSergey Zigachev unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id); 104*b843c749SSergey Zigachev 105*b843c749SSergey Zigachev #endif 106