1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev */
23*b843c749SSergey Zigachev #include <drm/drmP.h>
24*b843c749SSergey Zigachev #include <drm/amdgpu_drm.h>
25*b843c749SSergey Zigachev #include "amdgpu.h"
26*b843c749SSergey Zigachev #include "atomfirmware.h"
27*b843c749SSergey Zigachev #include "amdgpu_atomfirmware.h"
28*b843c749SSergey Zigachev #include "atom.h"
29*b843c749SSergey Zigachev #include "atombios.h"
30*b843c749SSergey Zigachev
31*b843c749SSergey Zigachev #define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))
32*b843c749SSergey Zigachev
amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device * adev)33*b843c749SSergey Zigachev bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
34*b843c749SSergey Zigachev {
35*b843c749SSergey Zigachev int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
36*b843c749SSergey Zigachev firmwareinfo);
37*b843c749SSergey Zigachev uint16_t data_offset;
38*b843c749SSergey Zigachev
39*b843c749SSergey Zigachev if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
40*b843c749SSergey Zigachev NULL, NULL, &data_offset)) {
41*b843c749SSergey Zigachev struct atom_firmware_info_v3_1 *firmware_info =
42*b843c749SSergey Zigachev (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
43*b843c749SSergey Zigachev data_offset);
44*b843c749SSergey Zigachev
45*b843c749SSergey Zigachev if (le32_to_cpu(firmware_info->firmware_capability) &
46*b843c749SSergey Zigachev ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
47*b843c749SSergey Zigachev return true;
48*b843c749SSergey Zigachev }
49*b843c749SSergey Zigachev return false;
50*b843c749SSergey Zigachev }
51*b843c749SSergey Zigachev
amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device * adev)52*b843c749SSergey Zigachev void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
53*b843c749SSergey Zigachev {
54*b843c749SSergey Zigachev int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
55*b843c749SSergey Zigachev firmwareinfo);
56*b843c749SSergey Zigachev uint16_t data_offset;
57*b843c749SSergey Zigachev
58*b843c749SSergey Zigachev if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
59*b843c749SSergey Zigachev NULL, NULL, &data_offset)) {
60*b843c749SSergey Zigachev struct atom_firmware_info_v3_1 *firmware_info =
61*b843c749SSergey Zigachev (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
62*b843c749SSergey Zigachev data_offset);
63*b843c749SSergey Zigachev
64*b843c749SSergey Zigachev adev->bios_scratch_reg_offset =
65*b843c749SSergey Zigachev le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
66*b843c749SSergey Zigachev }
67*b843c749SSergey Zigachev }
68*b843c749SSergey Zigachev
amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device * adev)69*b843c749SSergey Zigachev int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
70*b843c749SSergey Zigachev {
71*b843c749SSergey Zigachev struct atom_context *ctx = adev->mode_info.atom_context;
72*b843c749SSergey Zigachev int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
73*b843c749SSergey Zigachev vram_usagebyfirmware);
74*b843c749SSergey Zigachev struct vram_usagebyfirmware_v2_1 * firmware_usage;
75*b843c749SSergey Zigachev uint32_t start_addr, size;
76*b843c749SSergey Zigachev uint16_t data_offset;
77*b843c749SSergey Zigachev int usage_bytes = 0;
78*b843c749SSergey Zigachev
79*b843c749SSergey Zigachev if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
80*b843c749SSergey Zigachev firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
81*b843c749SSergey Zigachev DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
82*b843c749SSergey Zigachev le32_to_cpu(firmware_usage->start_address_in_kb),
83*b843c749SSergey Zigachev le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
84*b843c749SSergey Zigachev le16_to_cpu(firmware_usage->used_by_driver_in_kb));
85*b843c749SSergey Zigachev
86*b843c749SSergey Zigachev start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
87*b843c749SSergey Zigachev size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
88*b843c749SSergey Zigachev
89*b843c749SSergey Zigachev if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
90*b843c749SSergey Zigachev (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
91*b843c749SSergey Zigachev ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
92*b843c749SSergey Zigachev /* Firmware request VRAM reservation for SR-IOV */
93*b843c749SSergey Zigachev adev->fw_vram_usage.start_offset = (start_addr &
94*b843c749SSergey Zigachev (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
95*b843c749SSergey Zigachev adev->fw_vram_usage.size = size << 10;
96*b843c749SSergey Zigachev /* Use the default scratch size */
97*b843c749SSergey Zigachev usage_bytes = 0;
98*b843c749SSergey Zigachev } else {
99*b843c749SSergey Zigachev usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
100*b843c749SSergey Zigachev }
101*b843c749SSergey Zigachev }
102*b843c749SSergey Zigachev ctx->scratch_size_bytes = 0;
103*b843c749SSergey Zigachev if (usage_bytes == 0)
104*b843c749SSergey Zigachev usage_bytes = 20 * 1024;
105*b843c749SSergey Zigachev /* allocate some scratch memory */
106*b843c749SSergey Zigachev ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
107*b843c749SSergey Zigachev if (!ctx->scratch)
108*b843c749SSergey Zigachev return -ENOMEM;
109*b843c749SSergey Zigachev ctx->scratch_size_bytes = usage_bytes;
110*b843c749SSergey Zigachev return 0;
111*b843c749SSergey Zigachev }
112*b843c749SSergey Zigachev
113*b843c749SSergey Zigachev union igp_info {
114*b843c749SSergey Zigachev struct atom_integrated_system_info_v1_11 v11;
115*b843c749SSergey Zigachev };
116*b843c749SSergey Zigachev
117*b843c749SSergey Zigachev union umc_info {
118*b843c749SSergey Zigachev struct atom_umc_info_v3_1 v31;
119*b843c749SSergey Zigachev };
120*b843c749SSergey Zigachev /*
121*b843c749SSergey Zigachev * Return vram width from integrated system info table, if available,
122*b843c749SSergey Zigachev * or 0 if not.
123*b843c749SSergey Zigachev */
amdgpu_atomfirmware_get_vram_width(struct amdgpu_device * adev)124*b843c749SSergey Zigachev int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
125*b843c749SSergey Zigachev {
126*b843c749SSergey Zigachev struct amdgpu_mode_info *mode_info = &adev->mode_info;
127*b843c749SSergey Zigachev int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
128*b843c749SSergey Zigachev integratedsysteminfo);
129*b843c749SSergey Zigachev u16 data_offset, size;
130*b843c749SSergey Zigachev union igp_info *igp_info;
131*b843c749SSergey Zigachev u8 frev, crev;
132*b843c749SSergey Zigachev
133*b843c749SSergey Zigachev /* get any igp specific overrides */
134*b843c749SSergey Zigachev if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
135*b843c749SSergey Zigachev &frev, &crev, &data_offset)) {
136*b843c749SSergey Zigachev igp_info = (union igp_info *)
137*b843c749SSergey Zigachev (mode_info->atom_context->bios + data_offset);
138*b843c749SSergey Zigachev switch (crev) {
139*b843c749SSergey Zigachev case 11:
140*b843c749SSergey Zigachev return igp_info->v11.umachannelnumber * 64;
141*b843c749SSergey Zigachev default:
142*b843c749SSergey Zigachev return 0;
143*b843c749SSergey Zigachev }
144*b843c749SSergey Zigachev }
145*b843c749SSergey Zigachev
146*b843c749SSergey Zigachev return 0;
147*b843c749SSergey Zigachev }
148*b843c749SSergey Zigachev
convert_atom_mem_type_to_vram_type(struct amdgpu_device * adev,int atom_mem_type)149*b843c749SSergey Zigachev static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
150*b843c749SSergey Zigachev int atom_mem_type)
151*b843c749SSergey Zigachev {
152*b843c749SSergey Zigachev int vram_type;
153*b843c749SSergey Zigachev
154*b843c749SSergey Zigachev if (adev->flags & AMD_IS_APU) {
155*b843c749SSergey Zigachev switch (atom_mem_type) {
156*b843c749SSergey Zigachev case Ddr2MemType:
157*b843c749SSergey Zigachev case LpDdr2MemType:
158*b843c749SSergey Zigachev vram_type = AMDGPU_VRAM_TYPE_DDR2;
159*b843c749SSergey Zigachev break;
160*b843c749SSergey Zigachev case Ddr3MemType:
161*b843c749SSergey Zigachev case LpDdr3MemType:
162*b843c749SSergey Zigachev vram_type = AMDGPU_VRAM_TYPE_DDR3;
163*b843c749SSergey Zigachev break;
164*b843c749SSergey Zigachev case Ddr4MemType:
165*b843c749SSergey Zigachev case LpDdr4MemType:
166*b843c749SSergey Zigachev vram_type = AMDGPU_VRAM_TYPE_DDR4;
167*b843c749SSergey Zigachev break;
168*b843c749SSergey Zigachev default:
169*b843c749SSergey Zigachev vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
170*b843c749SSergey Zigachev break;
171*b843c749SSergey Zigachev }
172*b843c749SSergey Zigachev } else {
173*b843c749SSergey Zigachev switch (atom_mem_type) {
174*b843c749SSergey Zigachev case ATOM_DGPU_VRAM_TYPE_GDDR5:
175*b843c749SSergey Zigachev vram_type = AMDGPU_VRAM_TYPE_GDDR5;
176*b843c749SSergey Zigachev break;
177*b843c749SSergey Zigachev case ATOM_DGPU_VRAM_TYPE_HBM:
178*b843c749SSergey Zigachev vram_type = AMDGPU_VRAM_TYPE_HBM;
179*b843c749SSergey Zigachev break;
180*b843c749SSergey Zigachev default:
181*b843c749SSergey Zigachev vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
182*b843c749SSergey Zigachev break;
183*b843c749SSergey Zigachev }
184*b843c749SSergey Zigachev }
185*b843c749SSergey Zigachev
186*b843c749SSergey Zigachev return vram_type;
187*b843c749SSergey Zigachev }
188*b843c749SSergey Zigachev /*
189*b843c749SSergey Zigachev * Return vram type from either integrated system info table
190*b843c749SSergey Zigachev * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
191*b843c749SSergey Zigachev */
amdgpu_atomfirmware_get_vram_type(struct amdgpu_device * adev)192*b843c749SSergey Zigachev int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
193*b843c749SSergey Zigachev {
194*b843c749SSergey Zigachev struct amdgpu_mode_info *mode_info = &adev->mode_info;
195*b843c749SSergey Zigachev int index;
196*b843c749SSergey Zigachev u16 data_offset, size;
197*b843c749SSergey Zigachev union igp_info *igp_info;
198*b843c749SSergey Zigachev union umc_info *umc_info;
199*b843c749SSergey Zigachev u8 frev, crev;
200*b843c749SSergey Zigachev u8 mem_type;
201*b843c749SSergey Zigachev
202*b843c749SSergey Zigachev if (adev->flags & AMD_IS_APU)
203*b843c749SSergey Zigachev index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
204*b843c749SSergey Zigachev integratedsysteminfo);
205*b843c749SSergey Zigachev else
206*b843c749SSergey Zigachev index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
207*b843c749SSergey Zigachev umc_info);
208*b843c749SSergey Zigachev if (amdgpu_atom_parse_data_header(mode_info->atom_context,
209*b843c749SSergey Zigachev index, &size,
210*b843c749SSergey Zigachev &frev, &crev, &data_offset)) {
211*b843c749SSergey Zigachev if (adev->flags & AMD_IS_APU) {
212*b843c749SSergey Zigachev igp_info = (union igp_info *)
213*b843c749SSergey Zigachev (mode_info->atom_context->bios + data_offset);
214*b843c749SSergey Zigachev switch (crev) {
215*b843c749SSergey Zigachev case 11:
216*b843c749SSergey Zigachev mem_type = igp_info->v11.memorytype;
217*b843c749SSergey Zigachev return convert_atom_mem_type_to_vram_type(adev, mem_type);
218*b843c749SSergey Zigachev default:
219*b843c749SSergey Zigachev return 0;
220*b843c749SSergey Zigachev }
221*b843c749SSergey Zigachev } else {
222*b843c749SSergey Zigachev umc_info = (union umc_info *)
223*b843c749SSergey Zigachev (mode_info->atom_context->bios + data_offset);
224*b843c749SSergey Zigachev switch (crev) {
225*b843c749SSergey Zigachev case 1:
226*b843c749SSergey Zigachev mem_type = umc_info->v31.vram_type;
227*b843c749SSergey Zigachev return convert_atom_mem_type_to_vram_type(adev, mem_type);
228*b843c749SSergey Zigachev default:
229*b843c749SSergey Zigachev return 0;
230*b843c749SSergey Zigachev }
231*b843c749SSergey Zigachev }
232*b843c749SSergey Zigachev }
233*b843c749SSergey Zigachev
234*b843c749SSergey Zigachev return 0;
235*b843c749SSergey Zigachev }
236*b843c749SSergey Zigachev
237*b843c749SSergey Zigachev union firmware_info {
238*b843c749SSergey Zigachev struct atom_firmware_info_v3_1 v31;
239*b843c749SSergey Zigachev };
240*b843c749SSergey Zigachev
241*b843c749SSergey Zigachev union smu_info {
242*b843c749SSergey Zigachev struct atom_smu_info_v3_1 v31;
243*b843c749SSergey Zigachev };
244*b843c749SSergey Zigachev
amdgpu_atomfirmware_get_clock_info(struct amdgpu_device * adev)245*b843c749SSergey Zigachev int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
246*b843c749SSergey Zigachev {
247*b843c749SSergey Zigachev struct amdgpu_mode_info *mode_info = &adev->mode_info;
248*b843c749SSergey Zigachev struct amdgpu_pll *spll = &adev->clock.spll;
249*b843c749SSergey Zigachev struct amdgpu_pll *mpll = &adev->clock.mpll;
250*b843c749SSergey Zigachev uint8_t frev, crev;
251*b843c749SSergey Zigachev uint16_t data_offset;
252*b843c749SSergey Zigachev int ret = -EINVAL, index;
253*b843c749SSergey Zigachev
254*b843c749SSergey Zigachev index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
255*b843c749SSergey Zigachev firmwareinfo);
256*b843c749SSergey Zigachev if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
257*b843c749SSergey Zigachev &frev, &crev, &data_offset)) {
258*b843c749SSergey Zigachev union firmware_info *firmware_info =
259*b843c749SSergey Zigachev (union firmware_info *)(mode_info->atom_context->bios +
260*b843c749SSergey Zigachev data_offset);
261*b843c749SSergey Zigachev
262*b843c749SSergey Zigachev adev->clock.default_sclk =
263*b843c749SSergey Zigachev le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
264*b843c749SSergey Zigachev adev->clock.default_mclk =
265*b843c749SSergey Zigachev le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
266*b843c749SSergey Zigachev
267*b843c749SSergey Zigachev adev->pm.current_sclk = adev->clock.default_sclk;
268*b843c749SSergey Zigachev adev->pm.current_mclk = adev->clock.default_mclk;
269*b843c749SSergey Zigachev
270*b843c749SSergey Zigachev /* not technically a clock, but... */
271*b843c749SSergey Zigachev adev->mode_info.firmware_flags =
272*b843c749SSergey Zigachev le32_to_cpu(firmware_info->v31.firmware_capability);
273*b843c749SSergey Zigachev
274*b843c749SSergey Zigachev ret = 0;
275*b843c749SSergey Zigachev }
276*b843c749SSergey Zigachev
277*b843c749SSergey Zigachev index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
278*b843c749SSergey Zigachev smu_info);
279*b843c749SSergey Zigachev if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
280*b843c749SSergey Zigachev &frev, &crev, &data_offset)) {
281*b843c749SSergey Zigachev union smu_info *smu_info =
282*b843c749SSergey Zigachev (union smu_info *)(mode_info->atom_context->bios +
283*b843c749SSergey Zigachev data_offset);
284*b843c749SSergey Zigachev
285*b843c749SSergey Zigachev /* system clock */
286*b843c749SSergey Zigachev spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
287*b843c749SSergey Zigachev
288*b843c749SSergey Zigachev spll->reference_div = 0;
289*b843c749SSergey Zigachev spll->min_post_div = 1;
290*b843c749SSergey Zigachev spll->max_post_div = 1;
291*b843c749SSergey Zigachev spll->min_ref_div = 2;
292*b843c749SSergey Zigachev spll->max_ref_div = 0xff;
293*b843c749SSergey Zigachev spll->min_feedback_div = 4;
294*b843c749SSergey Zigachev spll->max_feedback_div = 0xff;
295*b843c749SSergey Zigachev spll->best_vco = 0;
296*b843c749SSergey Zigachev
297*b843c749SSergey Zigachev ret = 0;
298*b843c749SSergey Zigachev }
299*b843c749SSergey Zigachev
300*b843c749SSergey Zigachev index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
301*b843c749SSergey Zigachev umc_info);
302*b843c749SSergey Zigachev if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
303*b843c749SSergey Zigachev &frev, &crev, &data_offset)) {
304*b843c749SSergey Zigachev union umc_info *umc_info =
305*b843c749SSergey Zigachev (union umc_info *)(mode_info->atom_context->bios +
306*b843c749SSergey Zigachev data_offset);
307*b843c749SSergey Zigachev
308*b843c749SSergey Zigachev /* memory clock */
309*b843c749SSergey Zigachev mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
310*b843c749SSergey Zigachev
311*b843c749SSergey Zigachev mpll->reference_div = 0;
312*b843c749SSergey Zigachev mpll->min_post_div = 1;
313*b843c749SSergey Zigachev mpll->max_post_div = 1;
314*b843c749SSergey Zigachev mpll->min_ref_div = 2;
315*b843c749SSergey Zigachev mpll->max_ref_div = 0xff;
316*b843c749SSergey Zigachev mpll->min_feedback_div = 4;
317*b843c749SSergey Zigachev mpll->max_feedback_div = 0xff;
318*b843c749SSergey Zigachev mpll->best_vco = 0;
319*b843c749SSergey Zigachev
320*b843c749SSergey Zigachev ret = 0;
321*b843c749SSergey Zigachev }
322*b843c749SSergey Zigachev
323*b843c749SSergey Zigachev return ret;
324*b843c749SSergey Zigachev }
325*b843c749SSergey Zigachev
326*b843c749SSergey Zigachev union gfx_info {
327*b843c749SSergey Zigachev struct atom_gfx_info_v2_4 v24;
328*b843c749SSergey Zigachev };
329*b843c749SSergey Zigachev
amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device * adev)330*b843c749SSergey Zigachev int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
331*b843c749SSergey Zigachev {
332*b843c749SSergey Zigachev struct amdgpu_mode_info *mode_info = &adev->mode_info;
333*b843c749SSergey Zigachev int index;
334*b843c749SSergey Zigachev uint8_t frev, crev;
335*b843c749SSergey Zigachev uint16_t data_offset;
336*b843c749SSergey Zigachev
337*b843c749SSergey Zigachev index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
338*b843c749SSergey Zigachev gfx_info);
339*b843c749SSergey Zigachev if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
340*b843c749SSergey Zigachev &frev, &crev, &data_offset)) {
341*b843c749SSergey Zigachev union gfx_info *gfx_info = (union gfx_info *)
342*b843c749SSergey Zigachev (mode_info->atom_context->bios + data_offset);
343*b843c749SSergey Zigachev switch (crev) {
344*b843c749SSergey Zigachev case 4:
345*b843c749SSergey Zigachev adev->gfx.config.max_shader_engines = gfx_info->v24.gc_num_se;
346*b843c749SSergey Zigachev adev->gfx.config.max_cu_per_sh = gfx_info->v24.gc_num_cu_per_sh;
347*b843c749SSergey Zigachev adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se;
348*b843c749SSergey Zigachev adev->gfx.config.max_backends_per_se = gfx_info->v24.gc_num_rb_per_se;
349*b843c749SSergey Zigachev adev->gfx.config.max_texture_channel_caches = gfx_info->v24.gc_num_tccs;
350*b843c749SSergey Zigachev adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
351*b843c749SSergey Zigachev adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
352*b843c749SSergey Zigachev adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
353*b843c749SSergey Zigachev adev->gfx.config.gs_prim_buffer_depth =
354*b843c749SSergey Zigachev le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
355*b843c749SSergey Zigachev adev->gfx.config.double_offchip_lds_buf =
356*b843c749SSergey Zigachev gfx_info->v24.gc_double_offchip_lds_buffer;
357*b843c749SSergey Zigachev adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
358*b843c749SSergey Zigachev adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
359*b843c749SSergey Zigachev adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
360*b843c749SSergey Zigachev adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
361*b843c749SSergey Zigachev return 0;
362*b843c749SSergey Zigachev default:
363*b843c749SSergey Zigachev return -EINVAL;
364*b843c749SSergey Zigachev }
365*b843c749SSergey Zigachev
366*b843c749SSergey Zigachev }
367*b843c749SSergey Zigachev return -EINVAL;
368*b843c749SSergey Zigachev }
369