149436Sbostic /*- 249436Sbostic * Copyright (c) 1982, 1986, 1988 The Regents of the University of California. 349436Sbostic * All rights reserved. 423268Smckusick * 549436Sbostic * %sccs.include.proprietary.c% 649436Sbostic * 7*52627Ssklower * @(#)mtpr.h 7.7 (Berkeley) 02/20/92 823268Smckusick */ 9*52627Ssklower #ifndef _MTPR_H_ 10*52627Ssklower #define _MTPR_H_ 1162Sbill 1262Sbill /* 1362Sbill * VAX processor register numbers 1462Sbill */ 1562Sbill 162612Swnj #define KSP 0x0 /* kernel stack pointer */ 172612Swnj #define ESP 0x1 /* exec stack pointer */ 182612Swnj #define SSP 0x2 /* supervisor stack pointer */ 192612Swnj #define USP 0x3 /* user stack pointer */ 202612Swnj #define ISP 0x4 /* interrupt stack pointer */ 212612Swnj #define P0BR 0x8 /* p0 base register */ 222612Swnj #define P0LR 0x9 /* p0 length register */ 232612Swnj #define P1BR 0xa /* p1 base register */ 242612Swnj #define P1LR 0xb /* p1 length register */ 252612Swnj #define SBR 0xc /* system segment base register */ 262612Swnj #define SLR 0xd /* system segment length register */ 272612Swnj #define PCBB 0x10 /* process control block base */ 282612Swnj #define SCBB 0x11 /* system control block base */ 292612Swnj #define IPL 0x12 /* interrupt priority level */ 302612Swnj #define ASTLVL 0x13 /* async. system trap level */ 312612Swnj #define SIRR 0x14 /* software interrupt request */ 322612Swnj #define SISR 0x15 /* software interrupt summary */ 3334232Skarels #if VAX8200 3434232Skarels #define IPIR 0x16 /* interprocessor interrupt register */ 3534232Skarels #endif 3634232Skarels #if VAX750 || VAX730 3734232Skarels #define MCSR 0x17 /* machine check status register */ 3834232Skarels #endif 392612Swnj #define ICCS 0x18 /* interval clock control */ 402612Swnj #define NICR 0x19 /* next interval count */ 412612Swnj #define ICR 0x1a /* interval count */ 4235398Stef #if VAX8600 || VAX8200 || VAX780 || VAX750 || VAX730 || VAX650 432612Swnj #define TODR 0x1b /* time of year (day) */ 4434232Skarels #endif 4534232Skarels #if VAX750 || VAX730 4634232Skarels #define CSRS 0x1c /* console storage receive status register */ 4734232Skarels #define CSRD 0x1d /* console storage receive data register */ 4834232Skarels #define CSTS 0x1e /* console storage transmit status register */ 4934232Skarels #define CSTD 0x1f /* console storage transmit data register */ 5034232Skarels #endif 512612Swnj #define RXCS 0x20 /* console receiver control and status */ 522612Swnj #define RXDB 0x21 /* console receiver data buffer */ 532612Swnj #define TXCS 0x22 /* console transmitter control and status */ 542612Swnj #define TXDB 0x23 /* console transmitter data buffer */ 5535398Stef #if VAX8200 || VAX750 || VAX730 || VAX650 5634232Skarels #define TBDR 0x24 /* translation buffer disable register */ 5734232Skarels #define CADR 0x25 /* cache disable register */ 5836208Stef #endif 5936208Stef #if VAX8200 || VAX750 || VAX730 6034232Skarels #define MCESR 0x26 /* machine check error summary register */ 6134232Skarels #endif 6235398Stef #if VAX750 || VAX730 || VAX650 6334232Skarels #define CAER 0x27 /* cache error */ 6434232Skarels #endif 6534232Skarels #define ACCS 0x28 /* accelerator control and status */ 6634232Skarels #if VAX780 6734232Skarels #define ACCR 0x29 /* accelerator maintenance */ 6834232Skarels #endif 6934232Skarels #if VAX8200 || VAX780 7034232Skarels #define WCSA 0x2c /* WCS address */ 7134232Skarels #define WCSD 0x2d /* WCS data */ 7234232Skarels #endif 7334232Skarels #if VAX8200 7434232Skarels #define WCSL 0x2e /* WCS load */ 7534232Skarels #endif 7634232Skarels #if VAX8600 || VAX780 7734232Skarels #define SBIFS 0x30 /* SBI fault and status */ 7834232Skarels #define SBIS 0x31 /* SBI silo */ 7934232Skarels #define SBISC 0x32 /* SBI silo comparator */ 8034232Skarels #define SBIMT 0x33 /* SBI maintenance */ 8134232Skarels #define SBIER 0x34 /* SBI error register */ 8234232Skarels #define SBITA 0x35 /* SBI timeout address */ 8334232Skarels #define SBIQC 0x36 /* SBI quadword clear */ 8434232Skarels #endif 8535398Stef #if VAX750 || VAX730 || VAX630 || VAX650 8635398Stef #define IUR 0x37 /* init unibus (Qbus on 6x0) register */ 8734232Skarels #endif 882612Swnj #define MAPEN 0x38 /* memory management enable */ 892612Swnj #define TBIA 0x39 /* translation buffer invalidate all */ 902612Swnj #define TBIS 0x3a /* translation buffer invalidate single */ 9134232Skarels #if VAX750 || VAX730 9234232Skarels #define TB 0x3b /* translation buffer */ 9334232Skarels #endif 9434232Skarels #if VAX780 9534232Skarels #define MBRK 0x3c /* micro-program breakpoint */ 9634232Skarels #endif 972612Swnj #define PMR 0x3d /* performance monitor enable */ 982612Swnj #define SID 0x3e /* system identification */ 9935398Stef #if VAX8600 || VAX8200 || VAX650 10034232Skarels #define TBCHK 0x3f /* Translation Buffer Check */ 10124178Sbloom #endif 10234232Skarels #if VAX8600 10324178Sbloom #define PAMACC 0x40 /* PAMM access */ 10424178Sbloom #define PAMLOC 0x41 /* PAMM location */ 10524178Sbloom #define CSWP 0x42 /* Cache sweep */ 10624178Sbloom #define MDECC 0x43 /* MBOX data ecc register */ 10724178Sbloom #define MENA 0x44 /* MBOX error enable register */ 10824178Sbloom #define MDCTL 0x45 /* MBOX data control register */ 10924178Sbloom #define MCCTL 0x46 /* MBOX mcc control register */ 11024178Sbloom #define MERG 0x47 /* MBOX error generator register */ 11124178Sbloom #define CRBT 0x48 /* Console reboot */ 11224178Sbloom #define DFI 0x49 /* Diag fault insertion register */ 11324178Sbloom #define EHSR 0x4a /* Error handling status register */ 11424178Sbloom #define STXCS 0x4c /* Console block storage C/S */ 11524178Sbloom #define STXDB 0x4d /* Console block storage D/B */ 11624178Sbloom #define ESPA 0x4e /* EBOX scratchpad address */ 11724178Sbloom #define ESPD 0x4f /* EBOX sratchpad data */ 11824178Sbloom #endif 11934232Skarels #if VAX8200 12034232Skarels #define RXCS1 0x50 /* receive csr, console line 1 */ 12134232Skarels #define RXDB1 0x51 /* receive data buffer, console line 1 */ 12234232Skarels #define TXCS1 0x52 /* transmit csr, console line 1 */ 12334232Skarels #define TXDB1 0x53 /* transmit data buffer, console line 1 */ 12434232Skarels #define RXCS2 0x54 /* etc */ 12534232Skarels #define RXDB2 0x55 12634232Skarels #define TXCS2 0x56 12734232Skarels #define TXDB2 0x57 12834232Skarels #define RXCS3 0x58 12934232Skarels #define RXDB3 0x59 13034232Skarels #define TXCS3 0x5a 13134232Skarels #define TXDB3 0x5b 13234232Skarels #define RXCD 0x5c /* receive console data register */ 13334232Skarels #define CACHEX 0x5d /* cache invalidate register */ 13434232Skarels #define BINID 0x5e /* VAXBI node ID register */ 13534232Skarels #define BISTOP 0x5f /* VAXBI stop register */ 1361907Swnj #endif 137*52627Ssklower #endif /*_MTPR_H_*/ 138