134406Skarels /* 234406Skarels * Copyright (c) 1988 Regents of the University of California. 334406Skarels * All rights reserved. 434406Skarels * 534406Skarels * Redistribution and use in source and binary forms are permitted 634866Sbostic * provided that the above copyright notice and this paragraph are 734866Sbostic * duplicated in all such forms and that any documentation, 834866Sbostic * advertising materials, and other materials related to such 934866Sbostic * distribution and use acknowledge that the software was developed 1034866Sbostic * by the University of California, Berkeley. The name of the 1134866Sbostic * University may not be used to endorse or promote products derived 1234866Sbostic * from this software without specific prior written permission. 1334866Sbostic * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 1434866Sbostic * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 1534866Sbostic * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 1634406Skarels * 17*35412Skarels * @(#)vdreg.h 7.3 (Berkeley) 08/27/88 1834406Skarels */ 1925677Ssam 2025677Ssam /* 2130519Ssam * Versabus VDDC/SMDE disk controller definitions. 2225677Ssam */ 2331738Skarels #define VDDC_SECSIZE 512 /* sector size for VDDC */ 2431738Skarels #define VD_MAXSECSIZE 1024 /* max sector size for SMD/E */ 2525677Ssam 2625677Ssam /* 2730519Ssam * Controller communications block. 2825677Ssam */ 2930519Ssam struct vddevice { 3030519Ssam u_long vdcdr; /* controller device register */ 3130519Ssam u_long vdreset; /* controller reset register */ 3230519Ssam u_long vdcsr; /* control-status register */ 3330519Ssam long vdrstclr; /* reset clear register */ 3430519Ssam u_short vdstatus[16]; /* per-drive status register */ 3530519Ssam u_short vdicf_status; /* status change interupt control format */ 3630519Ssam u_short vdicf_done; /* interrupt complete control format */ 3730519Ssam u_short vdicf_error; /* interrupt error control format */ 3830519Ssam u_short vdicf_success; /* interrupt success control format */ 3930519Ssam u_short vdtcf_mdcb; /* mdcb transfer control format */ 4030519Ssam u_short vdtcf_dcb; /* dcb transfer control format */ 4130519Ssam u_short vdtcf_trail; /* trail transfer control format */ 4230519Ssam u_short vdtcf_data; /* data transfer control format */ 4330519Ssam u_long vdccf; /* controller configuration flags */ 4430519Ssam u_long vdsecsize; /* sector size */ 4530519Ssam u_short vdfill0; 4630519Ssam u_char vdcylskew; /* cylinder to cylinder skew factor */ 4730519Ssam u_char vdtrackskew; /* track to track skew factor */ 4830519Ssam u_long vdfill1; 4930519Ssam u_long vddfr; /* diagnostic flag register */ 5030519Ssam u_long vddda; /* diagnostic dump address */ 5130519Ssam }; 5225677Ssam 5330519Ssam /* controller types */ 5430519Ssam #define VDTYPE_VDDC 1 /* old vddc controller (smd only) */ 5530519Ssam #define VDTYPE_SMDE 2 /* new smde controller (smd-e) */ 5625677Ssam 5725677Ssam /* 5830519Ssam * Controller status definitions. 5925677Ssam */ 6030519Ssam #define CS_SCS 0xf /* status change source (drive number) */ 6130519Ssam #define CS_ELC 0x10 /* error on last command */ 6230519Ssam #define CS_ICC 0x60 /* interupt cause code */ 6330519Ssam #define ICC_NOI 0x00 /* no interupt */ 6430519Ssam #define ICC_DUN 0x20 /* no interupt */ 6530519Ssam #define ICC_ERR 0x40 /* no interupt */ 6630519Ssam #define ICC_SUC 0x60 /* no interupt */ 6730519Ssam #define CS_GO 0x80 /* go bit (controller busy) */ 6830519Ssam #define CS_BE 0x100 /* buss error */ 6930519Ssam #define CS_BOK 0x4000 /* board ok */ 7030519Ssam #define CS_SFL 0x8000 /* system fail */ 7130519Ssam #define CS_LEC 0xff000000 /* last error code */ 7225677Ssam 7325677Ssam /* 7430519Ssam * Drive status definitions. 7525677Ssam */ 7630519Ssam #define STA_UR 0x1 /* unit ready */ 7730519Ssam #define STA_OC 0x2 /* on cylinder */ 7830519Ssam #define STA_SE 0x4 /* seek error */ 7930519Ssam #define STA_DF 0x8 /* drive fault */ 8030519Ssam #define STA_WP 0x10 /* write protected */ 8130519Ssam #define STA_US 0x20 /* unit selected */ 82*35412Skarels #define STA_TYPE 0x300 /* drive type: */ 83*35412Skarels #define STA_SMD 0x000 /* SMD */ 84*35412Skarels #define STA_ESDI 0x100 /* ESDI */ 8525677Ssam 8625677Ssam /* 8730519Ssam * Interupt Control Field definitions. 8825677Ssam */ 8930519Ssam #define ICF_IPL 0x7 /* interupt priority level */ 9030519Ssam #define ICF_IEN 0x8 /* interupt enable */ 9130519Ssam #define ICF_IV 0xff00 /* interupt vector */ 9225677Ssam 9325677Ssam /* 9430519Ssam * Transfer Control Format definitions. 9525677Ssam */ 9625677Ssam #define TCF_AM 0xff /* Address Modifier */ 9725677Ssam #define AM_SNPDA 0x01 /* Standard Non-Privileged Data Access */ 9825677Ssam #define AM_SASA 0x81 /* Standard Ascending Sequential Access */ 9925677Ssam #define AM_ENPDA 0xf1 /* Extended Non-Privileged Data Access */ 10025677Ssam #define AM_EASA 0xe1 /* Extended Ascending Sequential Access */ 10125677Ssam #define TCF_BTE 0x800 /* Block Transfer Enable */ 10225677Ssam 10330519Ssam /* 10430519Ssam * Controller Configuration Flags. 10530519Ssam */ 10630519Ssam #define CCF_STS 0x1 /* sectors per track selectable */ 10730519Ssam #define CCF_EAV 0x2 /* enable auto vector */ 10830519Ssam #define CCF_ERR 0x4 /* enable reset register */ 109*35412Skarels #define CCF_RFE 0x8 /* recovery flag enable */ 11030519Ssam #define CCF_XMD 0x60 /* xmd transfer mode (bus size) */ 11130519Ssam #define XMD_8BIT 0x20 /* do only 8 bit transfers */ 11230519Ssam #define XMD_16BIT 0x40 /* do only 16 bit transfers */ 11330519Ssam #define XMD_32BIT 0x60 /* do only 32 bit transfers */ 114*35412Skarels #define CCF_DIU 0x80 /* disable initial update of DCB @cmd start */ 11530519Ssam #define CCF_BSZ 0x300 /* burst size */ 11625677Ssam #define BSZ_16WRD 0x000 /* 16 word transfer burst */ 11725677Ssam #define BSZ_12WRD 0x100 /* 12 word transfer burst */ 11825677Ssam #define BSZ_8WRD 0x200 /* 8 word transfer burst */ 11925677Ssam #define BSZ_4WRD 0x300 /* 4 word transfer burst */ 12030519Ssam #define CCF_SEN 0x400 /* cylinder/track skew enable (for format) */ 12130519Ssam #define CCF_ENP 0x1000 /* enable parity */ 12230519Ssam #define CCF_EPE 0x2000 /* enable parity errors */ 12330519Ssam #define CCF_EDE 0x10000 /* error detection enable */ 12430519Ssam #define CCF_ECE 0x20000 /* error correction enable */ 12525677Ssam 12625677Ssam /* 12725677Ssam * Diagnostic register definitions. 12825677Ssam */ 12930519Ssam #define DIA_DC 0x7f /* dump count mask */ 13030519Ssam #define DIA_DWR 0x80 /* dump write/read flag */ 13130519Ssam #define DIA_ARE 0x100 /* auto rebuild enable */ 13230519Ssam #define DIA_CEN 0x200 /* call enable flag */ 13330519Ssam #define DIA_KEY 0xAA550000 /* reset enable key */ 13425677Ssam 13525677Ssam /* 13631738Skarels * Hardware interface flags, in dcb.devselect and d_devflags 13731738Skarels */ 13831738Skarels #define VD_ESDI 0x10 /* drive is on ESDI interface */ 13931738Skarels #define d_devflags d_drivedata[0] /* in disk label */ 14031738Skarels 14131738Skarels /* 14231738Skarels * Error recovery flags. 14331738Skarels */ 14431738Skarels #define VDRF_RTZ 0x0001 /* return to zero */ 14531738Skarels #define VDRF_OCF 0x0002 /* on cylinder false */ 14631738Skarels #define VDRF_OSP 0x0004 /* offset plus */ 14731738Skarels #define VDRF_OSM 0x0008 /* offset minus */ 14831738Skarels #define VDRF_DSE 0x0080 /* data strobe early */ 14931738Skarels #define VDRF_DSL 0x0100 /* data strobe late */ 15031738Skarels 15131738Skarels #define VDRF_NONE 0 15231738Skarels #define VDRF_NORMAL (VDRF_RTZ|VDRF_OCF|VDRF_OSP|VDRF_OSM|VDRF_DSE|VDRF_DSE) 15331738Skarels 15431738Skarels /* 15525677Ssam * Perform a reset on the controller. 15625677Ssam */ 15730519Ssam #define VDRESET(a,t) { \ 15830519Ssam if ((t) == VDTYPE_SMDE) { \ 15930519Ssam ((struct vddevice *)(a))->vddfr = DIA_KEY|DIA_CEN; \ 16030519Ssam ((struct vddevice *)(a))->vdcdr = (u_long)0xffffffff; \ 16125677Ssam DELAY(5000000); \ 16225677Ssam } else { \ 16330519Ssam ((struct vddevice *)(a))->vdreset = 0; \ 16425677Ssam DELAY(1500000); \ 16525677Ssam } \ 16625677Ssam } 16725677Ssam 16825677Ssam /* 16925677Ssam * Abort a controller operation. 17025677Ssam */ 17130519Ssam #define VDABORT(a,t) { \ 17230519Ssam if ((t) == VDTYPE_VDDC) { \ 17330519Ssam movow((a), (VDOP_ABORT&0xffff0000)>>16) ; \ 17430519Ssam movow((int)(a)+2, VDOP_ABORT&0xffff); \ 17525677Ssam } else \ 17630519Ssam ((struct vddevice *)(a))->vdcdr = (u_long)VDOP_ABORT; \ 17725677Ssam DELAY(1000000); \ 17825677Ssam } 17925677Ssam 18025677Ssam /* 18130519Ssam * Start a command. 18225677Ssam */ 18330519Ssam #define VDGO(a,mdcb,t) {\ 18430519Ssam if ((t) == VDTYPE_VDDC) { \ 18530519Ssam movow((a), ((int)(mdcb)&0xffff0000)>>16) ; \ 18630519Ssam movow((int)((a))+2, (int)(mdcb)&0xffff); \ 18725677Ssam } else \ 18830519Ssam ((struct vddevice *)(a))->vdcdr = (mdcb); \ 18925677Ssam } 19025677Ssam 19125677Ssam /* 19230519Ssam * MDCB layout. 19330519Ssam */ 19430519Ssam struct mdcb { 19530519Ssam struct dcb *mdcb_head; /* first dcb in list */ 19630519Ssam struct dcb *mdcb_busy; /* dcb being processed */ 19730519Ssam struct dcb *mdcb_intr; /* dcb causing interrupt */ 19830519Ssam long mdcb_status; /* status of dcb in mdcb_busy */ 19930519Ssam }; 20030519Ssam 20130519Ssam /* 20230519Ssam * DCB definitions. 20330519Ssam */ 20430519Ssam 20530519Ssam /* 20625677Ssam * A disk address. 20725677Ssam */ 20825677Ssam typedef struct { 20930519Ssam u_char track; /* all 8 bits */ 21030519Ssam u_char sector; /* all 8 bits */ 21130519Ssam u_short cylinder; /* low order 12 bits */ 21225677Ssam } dskadr; 21325677Ssam 21425677Ssam /* 21525677Ssam * DCB trailer formats. 21625677Ssam */ 21725677Ssam /* read/write trailer */ 21830756Skarels struct trrw { 21930601Skarels u_long memadr; /* memory address */ 22025677Ssam u_long wcount; /* 16 bit word count */ 22125677Ssam dskadr disk; /* disk address */ 22230756Skarels }; 22325677Ssam 22425677Ssam /* scatter/gather trailer */ 22530756Skarels #define VDMAXPAGES (MAXPHYS / NBPG) 22630756Skarels struct trsg { 22730756Skarels struct trrw start_addr; 22830756Skarels struct addr_chain { 22930601Skarels u_long nxt_addr; 23025677Ssam u_long nxt_len; 23130756Skarels } addr_chain[VDMAXPAGES + 1]; 23230756Skarels }; 23325677Ssam 23425677Ssam /* seek trailer format */ 23530756Skarels struct trseek { 23625677Ssam dskadr skaddr; 23730756Skarels }; 23825677Ssam 23925677Ssam /* format trailer */ 24030756Skarels struct trfmt { 24125677Ssam char *addr; /* data buffer to be filled on sector*/ 24225677Ssam long nsectors; /* # of sectors to be formatted */ 24325677Ssam dskadr disk; /* disk physical address info */ 24425677Ssam dskadr hdr; /* header address info */ 24530756Skarels }; 24625677Ssam 24725677Ssam /* reset/configure trailer */ 24830756Skarels struct treset { 24925677Ssam long ncyl; /* # cylinders */ 25025677Ssam long nsurfaces; /* # surfaces */ 25125677Ssam long nsectors; /* # sectors */ 25225677Ssam long slip_sec; /* # of slip sectors */ 25329683Ssam long recovery; /* recovery flags */ 25430756Skarels }; 25525677Ssam 25630756Skarels /* ident trailer */ 25730756Skarels struct trid { 25830756Skarels long name; 259*35412Skarels long rev; 26030756Skarels long date; 26130756Skarels }; 26230756Skarels 26325677Ssam /* 26425677Ssam * DCB layout. 26525677Ssam */ 26630519Ssam struct dcb { 26730519Ssam struct dcb *nxtdcb; /* next dcb */ 26825677Ssam short intflg; /* interrupt settings and flags */ 26925677Ssam short opcode; /* DCB command code etc... */ 27025677Ssam long operrsta; /* error & status info */ 27125677Ssam short fill; /* not used */ 27225677Ssam char devselect; /* drive selection */ 27325677Ssam char trailcnt; /* trailer Word Count */ 27425677Ssam long err_memadr; /* error memory address */ 275*35412Skarels u_char err_code; /* error codes for SMD/E */ 27625677Ssam char fill2; /* not used */ 27725677Ssam short err_wcount; /* error word count */ 27825677Ssam char err_trk; /* error track/sector */ 27925677Ssam char err_sec; /* error track/sector */ 28025677Ssam short err_cyl; /* error cylinder adr */ 28125677Ssam union { 28230756Skarels struct trid idtrail; /* ident command trailer */ 28330756Skarels struct trseek sktrail; /* seek command trailer */ 28430756Skarels struct trsg sgtrail; /* scatter/gather trailer */ 28530756Skarels struct trrw rwtrail; /* read/write trailer */ 28630756Skarels struct trfmt fmtrail; /* format trailer */ 28730756Skarels struct treset rstrail; /* reset/configure trailer */ 28825677Ssam } trail; 28930519Ssam }; 29025677Ssam 29125677Ssam /* 29230756Skarels * smaller DCB with seek trailer only (no scatter-gather). 29330756Skarels */ 29430756Skarels struct skdcb { 29530756Skarels struct dcb *nxtdcb; /* next dcb */ 29630756Skarels short intflg; /* interrupt settings and flags */ 29730756Skarels short opcode; /* DCB command code etc... */ 29830756Skarels long operrsta; /* error & status info */ 29930756Skarels short fill; /* not used */ 30030756Skarels char devselect; /* drive selection */ 30130756Skarels char trailcnt; /* trailer Word Count */ 30230756Skarels long err_memadr; /* error memory address */ 303*35412Skarels u_char err_code; /* error codes for SMD/E */ 30430756Skarels char fill2; /* not used */ 30530756Skarels short err_wcount; /* error word count */ 30630756Skarels char err_trk; /* error track/sector */ 30730756Skarels char err_sec; /* error track/sector */ 30830756Skarels short err_cyl; /* error cylinder adr */ 30930756Skarels union { 31030756Skarels struct trseek sktrail; /* seek command trailer */ 31130756Skarels } trail; 31230756Skarels }; 31330756Skarels 31430756Skarels /* 31530519Ssam * DCB command codes. 31625677Ssam */ 31730519Ssam #define VDOP_RD 0x80 /* read data */ 31830519Ssam #define VDOP_FTR 0xc0 /* full track read */ 31930519Ssam #define VDOP_RAS 0x90 /* read and scatter */ 32030519Ssam #define VDOP_RDRAW 0x600 /* read unformatted disk sector */ 32130519Ssam #define VDOP_CMP 0xa0 /* compare */ 32230519Ssam #define VDOP_FTC 0xe0 /* full track compare */ 32330519Ssam #define VDOP_RHDE 0x180 /* read header, data & ecc */ 32430519Ssam #define VDOP_WD 0x00 /* write data */ 32530519Ssam #define VDOP_FTW 0x40 /* full track write */ 32630519Ssam #define VDOP_WTC 0x20 /* write then compare */ 32730519Ssam #define VDOP_FTWTC 0x60 /* full track write then compare */ 32830519Ssam #define VDOP_GAW 0x10 /* gather and write */ 32930519Ssam #define VDOP_WDE 0x100 /* write data & ecc */ 33030519Ssam #define VDOP_FSECT 0x900 /* format sector */ 33130519Ssam #define VDOP_GWC 0x30 /* gather write & compare */ 33230519Ssam #define VDOP_START 0x800 /* start drives */ 33330519Ssam #define VDOP_RELEASE 0xa00 /* stop drives */ 33430519Ssam #define VDOP_SEEK 0xb00 /* seek */ 33530519Ssam #define VDOP_INIT 0xc00 /* initialize controller */ 33630519Ssam #define VDOP_DIAG 0xd00 /* diagnose (self-test) controller */ 33730519Ssam #define VDOP_CONFIG 0xe00 /* reset & configure drive */ 33830519Ssam #define VDOP_STATUS 0xf00 /* get drive status */ 33930756Skarels #define VDOP_IDENT 0x700 /* identify controller */ 34025677Ssam 34130519Ssam #define VDOP_ABORT 0x80000000 /* abort current command */ 34230519Ssam 34325677Ssam /* 34430519Ssam * DCB status definitions. 34525677Ssam */ 34630519Ssam #define DCBS_HCRC 0x00000001 /* header crc error */ 34730519Ssam #define DCBS_HCE 0x00000002 /* header compare error */ 34830519Ssam #define DCBS_WPT 0x00000004 /* drive write protected */ 34930519Ssam #define DCBS_CHE 0x00000008 /* controller hardware error */ 35030519Ssam #define DCBS_SKI 0x00000010 /* seek incomplete */ 35130519Ssam #define DCBS_UDE 0x00000020 /* uncorrectable data error */ 35230519Ssam #define DCBS_OCYL 0x00000040 /* off cylinder */ 35330519Ssam #define DCBS_NRDY 0x00000080 /* drive not ready */ 35430519Ssam #define DCBS_ATA 0x00000100 /* alternate track accessed */ 35530519Ssam #define DCBS_SKS 0x00000200 /* seek started */ 35630519Ssam #define DCBS_IVA 0x00000400 /* invalid disk address error */ 35730519Ssam #define DCBS_NEM 0x00000800 /* non-existant memory error */ 35830519Ssam #define DCBS_DPE 0x00001000 /* memory data parity error */ 35930519Ssam #define DCBS_DCE 0x00002000 /* data compare error */ 36030519Ssam #define DCBS_DDI 0x00004000 /* ddi ready */ 36130519Ssam #define DCBS_OAB 0x00008000 /* operation aborted */ 36230519Ssam #define DCBS_DSE 0x00010000 /* data strobe early */ 36330519Ssam #define DCBS_DSL 0x00020000 /* data strobe late */ 36430519Ssam #define DCBS_TOP 0x00040000 /* track offset plus */ 36530519Ssam #define DCBS_TOM 0x00080000 /* track offset minus */ 36630519Ssam #define DCBS_CCD 0x00100000 /* controller corrected data */ 36730519Ssam #define DCBS_HARD 0x00200000 /* hard error */ 36830519Ssam #define DCBS_SOFT 0x00400000 /* soft error (retry succesful) */ 36930519Ssam #define DCBS_ERR 0x00800000 /* composite error */ 37030519Ssam #define DCBS_IVC 0x01000000 /* invalid command error */ 37130519Ssam /* bits 24-27 unused */ 37230519Ssam #define DCBS_BSY 0x10000000 /* controller busy */ 37330519Ssam #define DCBS_ICC 0x60000000 /* interrupt cause code */ 37430519Ssam #define DCBS_INT 0x80000000 /* interrupt generated for this dcb */ 37525677Ssam 37630519Ssam #define VDERRBITS "\20\1HCRC\2HCE\3WPT\4CHE\5DSKI\6UDE\7OCYL\10NRDY\ 37730519Ssam \11ATA\12SKS\13IVA\14NEM\15DPE\16DCE\17DDI\20OAB\21DSE\22DSL\23TOP\24TOM\ 37830519Ssam \25CCD\26HARD\27SOFT\30ERR\31IVC\35ABORTED\36FAIL\37COMPLETE\40STARTED" 37925677Ssam 38030519Ssam /* drive related errors */ 38130519Ssam #define VDERR_DRIVE (DCBS_SKI|DCBS_OCYL|DCBS_NRDY|DCBS_IVA) 38230519Ssam /* controller related errors */ 38330519Ssam #define VDERR_CTLR (DCBS_CHE|DCBS_OAB|DCBS_IVC|DCBS_NEM) 38430519Ssam /* potentially recoverable errors */ 38530601Skarels #define VDERR_RETRY \ 38630519Ssam (VDERR_DRIVE|VDERR_CTLR|DCBS_DCE|DCBS_DPE|DCBS_HCRC|DCBS_HCE) 38730519Ssam /* uncorrected data errors */ 38830601Skarels #define VDERR_HARD (VDERR_RETRY|DCBS_WPT|DCBS_UDE) 38925677Ssam 39025677Ssam /* 39130519Ssam * DCB status codes. 39225677Ssam */ 39330519Ssam #define DCBS_ABORT 0x10000000 /* dcb aborted */ 39430519Ssam #define DCBS_FAIL 0x20000000 /* dcb unsuccesfully completed */ 39530519Ssam #define DCBS_DONE 0x40000000 /* dcb complete */ 39630519Ssam #define DCBS_START 0x80000000 /* dcb started */ 39725677Ssam 39830519Ssam /* 39930519Ssam * DCB interrupt control. 40030519Ssam */ 40130519Ssam #define DCBINT_NONE 0x0 /* don't interrupt */ 40230519Ssam #define DCBINT_ERR 0x2 /* interrupt on error */ 40330519Ssam #define DCBINT_SUC 0x1 /* interrupt on success */ 40430519Ssam #define DCBINT_DONE (DCBINT_ERR|DCBINT_SUC) 40530519Ssam #define DCBINT_PBA 0x4 /* proceed before acknowledge */ 40625677Ssam 40730519Ssam /* 40830519Ssam * Sector formats. 40930519Ssam */ 41030519Ssam typedef union { 41130519Ssam struct { 41230519Ssam dskadr hdr_addr; 41330519Ssam short smd_crc; 41430519Ssam } smd; 41530519Ssam struct { 41630519Ssam dskadr physical; 41730519Ssam dskadr logical; 41830519Ssam long smd_e_crc; 41930519Ssam } smd_e; 42030519Ssam } fmt_hdr; 42125677Ssam 42230519Ssam /* Sector Header bit assignments */ 42330519Ssam #define VDMF 0x8000 /* Manufacturer Fault 1=good sector */ 42430519Ssam #define VDUF 0x4000 /* User Fault 1=good sector */ 42530519Ssam #define VDALT 0x2000 /* Alternate Sector 1=alternate */ 42630519Ssam #define VDWPT 0x1000 /* Write Protect 1=Read Only Sector */ 42734396Skarels 42834396Skarels /* input register assignments for DIOCWFORMAT ioctl */ 42934396Skarels #define dk_op df_reg[0] /* opcode */ 43034396Skarels #define dk_althdr df_reg[1] /* alt. sect. header, in an int! */ 43134396Skarels #define dk_fmtflags df_reg[2] /* header format flags */ 43234396Skarels 43334396Skarels /* output register assignments for DIOCWFORMAT ioctl */ 43434396Skarels #define dk_operrsta df_reg[0] /* dcb operrsta */ 43534396Skarels #define dk_ecode df_reg[1] /* smd-e err_code */ 436