134406Skarels /* 234406Skarels * Copyright (c) 1988 Regents of the University of California. 334406Skarels * All rights reserved. 434406Skarels * 540237Skarels * This code is derived from software contributed to Berkeley by 640237Skarels * Computer Consoles Inc. 740237Skarels * 8*44535Sbostic * %sccs.include.redist.c% 934406Skarels * 10*44535Sbostic * @(#)vdreg.h 7.7 (Berkeley) 06/28/90 1134406Skarels */ 1225677Ssam 1325677Ssam /* 1430519Ssam * Versabus VDDC/SMDE disk controller definitions. 1525677Ssam */ 1631738Skarels #define VDDC_SECSIZE 512 /* sector size for VDDC */ 1731738Skarels #define VD_MAXSECSIZE 1024 /* max sector size for SMD/E */ 1825677Ssam 1925677Ssam /* 2030519Ssam * Controller communications block. 2125677Ssam */ 2230519Ssam struct vddevice { 2330519Ssam u_long vdcdr; /* controller device register */ 2430519Ssam u_long vdreset; /* controller reset register */ 2530519Ssam u_long vdcsr; /* control-status register */ 2630519Ssam long vdrstclr; /* reset clear register */ 2730519Ssam u_short vdstatus[16]; /* per-drive status register */ 2830519Ssam u_short vdicf_status; /* status change interupt control format */ 2930519Ssam u_short vdicf_done; /* interrupt complete control format */ 3030519Ssam u_short vdicf_error; /* interrupt error control format */ 3130519Ssam u_short vdicf_success; /* interrupt success control format */ 3230519Ssam u_short vdtcf_mdcb; /* mdcb transfer control format */ 3330519Ssam u_short vdtcf_dcb; /* dcb transfer control format */ 3430519Ssam u_short vdtcf_trail; /* trail transfer control format */ 3530519Ssam u_short vdtcf_data; /* data transfer control format */ 3630519Ssam u_long vdccf; /* controller configuration flags */ 3730519Ssam u_long vdsecsize; /* sector size */ 3830519Ssam u_short vdfill0; 3930519Ssam u_char vdcylskew; /* cylinder to cylinder skew factor */ 4030519Ssam u_char vdtrackskew; /* track to track skew factor */ 4130519Ssam u_long vdfill1; 4230519Ssam u_long vddfr; /* diagnostic flag register */ 4330519Ssam u_long vddda; /* diagnostic dump address */ 4430519Ssam }; 4525677Ssam 4630519Ssam /* controller types */ 4730519Ssam #define VDTYPE_VDDC 1 /* old vddc controller (smd only) */ 4830519Ssam #define VDTYPE_SMDE 2 /* new smde controller (smd-e) */ 4925677Ssam 5025677Ssam /* 5130519Ssam * Controller status definitions. 5225677Ssam */ 5330519Ssam #define CS_SCS 0xf /* status change source (drive number) */ 5430519Ssam #define CS_ELC 0x10 /* error on last command */ 5530519Ssam #define CS_ICC 0x60 /* interupt cause code */ 5630519Ssam #define ICC_NOI 0x00 /* no interupt */ 5730519Ssam #define ICC_DUN 0x20 /* no interupt */ 5830519Ssam #define ICC_ERR 0x40 /* no interupt */ 5930519Ssam #define ICC_SUC 0x60 /* no interupt */ 6030519Ssam #define CS_GO 0x80 /* go bit (controller busy) */ 6130519Ssam #define CS_BE 0x100 /* buss error */ 6230519Ssam #define CS_BOK 0x4000 /* board ok */ 6330519Ssam #define CS_SFL 0x8000 /* system fail */ 6430519Ssam #define CS_LEC 0xff000000 /* last error code */ 6525677Ssam 6625677Ssam /* 6730519Ssam * Drive status definitions. 6825677Ssam */ 6930519Ssam #define STA_UR 0x1 /* unit ready */ 7030519Ssam #define STA_OC 0x2 /* on cylinder */ 7130519Ssam #define STA_SE 0x4 /* seek error */ 7230519Ssam #define STA_DF 0x8 /* drive fault */ 7330519Ssam #define STA_WP 0x10 /* write protected */ 7430519Ssam #define STA_US 0x20 /* unit selected */ 7535412Skarels #define STA_TYPE 0x300 /* drive type: */ 7635412Skarels #define STA_SMD 0x000 /* SMD */ 7735412Skarels #define STA_ESDI 0x100 /* ESDI */ 7825677Ssam 7925677Ssam /* 8030519Ssam * Interupt Control Field definitions. 8125677Ssam */ 8230519Ssam #define ICF_IPL 0x7 /* interupt priority level */ 8330519Ssam #define ICF_IEN 0x8 /* interupt enable */ 8430519Ssam #define ICF_IV 0xff00 /* interupt vector */ 8525677Ssam 8625677Ssam /* 8730519Ssam * Transfer Control Format definitions. 8825677Ssam */ 8925677Ssam #define TCF_AM 0xff /* Address Modifier */ 9025677Ssam #define AM_SNPDA 0x01 /* Standard Non-Privileged Data Access */ 9125677Ssam #define AM_SASA 0x81 /* Standard Ascending Sequential Access */ 9225677Ssam #define AM_ENPDA 0xf1 /* Extended Non-Privileged Data Access */ 9325677Ssam #define AM_EASA 0xe1 /* Extended Ascending Sequential Access */ 9425677Ssam #define TCF_BTE 0x800 /* Block Transfer Enable */ 9525677Ssam 9630519Ssam /* 9730519Ssam * Controller Configuration Flags. 9830519Ssam */ 9930519Ssam #define CCF_STS 0x1 /* sectors per track selectable */ 10030519Ssam #define CCF_EAV 0x2 /* enable auto vector */ 10130519Ssam #define CCF_ERR 0x4 /* enable reset register */ 10235412Skarels #define CCF_RFE 0x8 /* recovery flag enable */ 10330519Ssam #define CCF_XMD 0x60 /* xmd transfer mode (bus size) */ 10430519Ssam #define XMD_8BIT 0x20 /* do only 8 bit transfers */ 10530519Ssam #define XMD_16BIT 0x40 /* do only 16 bit transfers */ 10630519Ssam #define XMD_32BIT 0x60 /* do only 32 bit transfers */ 10735412Skarels #define CCF_DIU 0x80 /* disable initial update of DCB @cmd start */ 10830519Ssam #define CCF_BSZ 0x300 /* burst size */ 10925677Ssam #define BSZ_16WRD 0x000 /* 16 word transfer burst */ 11025677Ssam #define BSZ_12WRD 0x100 /* 12 word transfer burst */ 11125677Ssam #define BSZ_8WRD 0x200 /* 8 word transfer burst */ 11225677Ssam #define BSZ_4WRD 0x300 /* 4 word transfer burst */ 11330519Ssam #define CCF_SEN 0x400 /* cylinder/track skew enable (for format) */ 11430519Ssam #define CCF_ENP 0x1000 /* enable parity */ 11530519Ssam #define CCF_EPE 0x2000 /* enable parity errors */ 11630519Ssam #define CCF_EDE 0x10000 /* error detection enable */ 11730519Ssam #define CCF_ECE 0x20000 /* error correction enable */ 11825677Ssam 11925677Ssam /* 12025677Ssam * Diagnostic register definitions. 12125677Ssam */ 12230519Ssam #define DIA_DC 0x7f /* dump count mask */ 12330519Ssam #define DIA_DWR 0x80 /* dump write/read flag */ 12430519Ssam #define DIA_ARE 0x100 /* auto rebuild enable */ 12530519Ssam #define DIA_CEN 0x200 /* call enable flag */ 12630519Ssam #define DIA_KEY 0xAA550000 /* reset enable key */ 12725677Ssam 12825677Ssam /* 12931738Skarels * Hardware interface flags, in dcb.devselect and d_devflags 13031738Skarels */ 13131738Skarels #define VD_ESDI 0x10 /* drive is on ESDI interface */ 13231738Skarels #define d_devflags d_drivedata[0] /* in disk label */ 13331738Skarels 13431738Skarels /* 13531738Skarels * Error recovery flags. 13631738Skarels */ 13731738Skarels #define VDRF_RTZ 0x0001 /* return to zero */ 13831738Skarels #define VDRF_OCF 0x0002 /* on cylinder false */ 13931738Skarels #define VDRF_OSP 0x0004 /* offset plus */ 14031738Skarels #define VDRF_OSM 0x0008 /* offset minus */ 14131738Skarels #define VDRF_DSE 0x0080 /* data strobe early */ 14231738Skarels #define VDRF_DSL 0x0100 /* data strobe late */ 14331738Skarels 14431738Skarels #define VDRF_NONE 0 14540736Skarels #define VDRF_NORMAL (VDRF_RTZ|VDRF_OCF|VDRF_OSP|VDRF_OSM|VDRF_DSE|VDRF_DSL) 14631738Skarels 14731738Skarels /* 14825677Ssam * Perform a reset on the controller. 14925677Ssam */ 15030519Ssam #define VDRESET(a,t) { \ 15130519Ssam if ((t) == VDTYPE_SMDE) { \ 15230519Ssam ((struct vddevice *)(a))->vddfr = DIA_KEY|DIA_CEN; \ 15330519Ssam ((struct vddevice *)(a))->vdcdr = (u_long)0xffffffff; \ 15425677Ssam DELAY(5000000); \ 15525677Ssam } else { \ 15630519Ssam ((struct vddevice *)(a))->vdreset = 0; \ 15725677Ssam DELAY(1500000); \ 15825677Ssam } \ 15925677Ssam } 16025677Ssam 16125677Ssam /* 16225677Ssam * Abort a controller operation. 16325677Ssam */ 16430519Ssam #define VDABORT(a,t) { \ 16530519Ssam if ((t) == VDTYPE_VDDC) { \ 16630519Ssam movow((a), (VDOP_ABORT&0xffff0000)>>16) ; \ 16730519Ssam movow((int)(a)+2, VDOP_ABORT&0xffff); \ 16825677Ssam } else \ 16930519Ssam ((struct vddevice *)(a))->vdcdr = (u_long)VDOP_ABORT; \ 17025677Ssam DELAY(1000000); \ 17125677Ssam } 17225677Ssam 17325677Ssam /* 17430519Ssam * Start a command. 17525677Ssam */ 17630519Ssam #define VDGO(a,mdcb,t) {\ 17730519Ssam if ((t) == VDTYPE_VDDC) { \ 17830519Ssam movow((a), ((int)(mdcb)&0xffff0000)>>16) ; \ 17930519Ssam movow((int)((a))+2, (int)(mdcb)&0xffff); \ 18025677Ssam } else \ 18130519Ssam ((struct vddevice *)(a))->vdcdr = (mdcb); \ 18225677Ssam } 18325677Ssam 18425677Ssam /* 18530519Ssam * MDCB layout. 18630519Ssam */ 18730519Ssam struct mdcb { 18830519Ssam struct dcb *mdcb_head; /* first dcb in list */ 18930519Ssam struct dcb *mdcb_busy; /* dcb being processed */ 19030519Ssam struct dcb *mdcb_intr; /* dcb causing interrupt */ 19130519Ssam long mdcb_status; /* status of dcb in mdcb_busy */ 19230519Ssam }; 19330519Ssam 19430519Ssam /* 19530519Ssam * DCB definitions. 19630519Ssam */ 19730519Ssam 19830519Ssam /* 19925677Ssam * A disk address. 20025677Ssam */ 20125677Ssam typedef struct { 20230519Ssam u_char track; /* all 8 bits */ 20330519Ssam u_char sector; /* all 8 bits */ 20430519Ssam u_short cylinder; /* low order 12 bits */ 20525677Ssam } dskadr; 20625677Ssam 20725677Ssam /* 20825677Ssam * DCB trailer formats. 20925677Ssam */ 21025677Ssam /* read/write trailer */ 21130756Skarels struct trrw { 21230601Skarels u_long memadr; /* memory address */ 21325677Ssam u_long wcount; /* 16 bit word count */ 21425677Ssam dskadr disk; /* disk address */ 21530756Skarels }; 21625677Ssam 21725677Ssam /* scatter/gather trailer */ 21830756Skarels #define VDMAXPAGES (MAXPHYS / NBPG) 21930756Skarels struct trsg { 22030756Skarels struct trrw start_addr; 22130756Skarels struct addr_chain { 22230601Skarels u_long nxt_addr; 22325677Ssam u_long nxt_len; 22430756Skarels } addr_chain[VDMAXPAGES + 1]; 22530756Skarels }; 22625677Ssam 22725677Ssam /* seek trailer format */ 22830756Skarels struct trseek { 22925677Ssam dskadr skaddr; 23030756Skarels }; 23125677Ssam 23225677Ssam /* format trailer */ 23330756Skarels struct trfmt { 23425677Ssam char *addr; /* data buffer to be filled on sector*/ 23525677Ssam long nsectors; /* # of sectors to be formatted */ 23625677Ssam dskadr disk; /* disk physical address info */ 23725677Ssam dskadr hdr; /* header address info */ 23830756Skarels }; 23925677Ssam 24025677Ssam /* reset/configure trailer */ 24130756Skarels struct treset { 24225677Ssam long ncyl; /* # cylinders */ 24325677Ssam long nsurfaces; /* # surfaces */ 24425677Ssam long nsectors; /* # sectors */ 24525677Ssam long slip_sec; /* # of slip sectors */ 24629683Ssam long recovery; /* recovery flags */ 24730756Skarels }; 24825677Ssam 24930756Skarels /* ident trailer */ 25030756Skarels struct trid { 25130756Skarels long name; 25235412Skarels long rev; 25330756Skarels long date; 25430756Skarels }; 25530756Skarels 25625677Ssam /* 25725677Ssam * DCB layout. 25825677Ssam */ 25930519Ssam struct dcb { 26030519Ssam struct dcb *nxtdcb; /* next dcb */ 26125677Ssam short intflg; /* interrupt settings and flags */ 26225677Ssam short opcode; /* DCB command code etc... */ 26325677Ssam long operrsta; /* error & status info */ 26425677Ssam short fill; /* not used */ 26525677Ssam char devselect; /* drive selection */ 26625677Ssam char trailcnt; /* trailer Word Count */ 26725677Ssam long err_memadr; /* error memory address */ 26835412Skarels u_char err_code; /* error codes for SMD/E */ 26925677Ssam char fill2; /* not used */ 27025677Ssam short err_wcount; /* error word count */ 27125677Ssam char err_trk; /* error track/sector */ 27225677Ssam char err_sec; /* error track/sector */ 27325677Ssam short err_cyl; /* error cylinder adr */ 27425677Ssam union { 27530756Skarels struct trid idtrail; /* ident command trailer */ 27630756Skarels struct trseek sktrail; /* seek command trailer */ 27730756Skarels struct trsg sgtrail; /* scatter/gather trailer */ 27830756Skarels struct trrw rwtrail; /* read/write trailer */ 27930756Skarels struct trfmt fmtrail; /* format trailer */ 28030756Skarels struct treset rstrail; /* reset/configure trailer */ 28125677Ssam } trail; 28230519Ssam }; 28325677Ssam 28425677Ssam /* 28530756Skarels * smaller DCB with seek trailer only (no scatter-gather). 28630756Skarels */ 28730756Skarels struct skdcb { 28830756Skarels struct dcb *nxtdcb; /* next dcb */ 28930756Skarels short intflg; /* interrupt settings and flags */ 29030756Skarels short opcode; /* DCB command code etc... */ 29130756Skarels long operrsta; /* error & status info */ 29230756Skarels short fill; /* not used */ 29330756Skarels char devselect; /* drive selection */ 29430756Skarels char trailcnt; /* trailer Word Count */ 29530756Skarels long err_memadr; /* error memory address */ 29635412Skarels u_char err_code; /* error codes for SMD/E */ 29730756Skarels char fill2; /* not used */ 29830756Skarels short err_wcount; /* error word count */ 29930756Skarels char err_trk; /* error track/sector */ 30030756Skarels char err_sec; /* error track/sector */ 30130756Skarels short err_cyl; /* error cylinder adr */ 30230756Skarels union { 30330756Skarels struct trseek sktrail; /* seek command trailer */ 30430756Skarels } trail; 30530756Skarels }; 30630756Skarels 30730756Skarels /* 30830519Ssam * DCB command codes. 30925677Ssam */ 31030519Ssam #define VDOP_RD 0x80 /* read data */ 31130519Ssam #define VDOP_FTR 0xc0 /* full track read */ 31230519Ssam #define VDOP_RAS 0x90 /* read and scatter */ 31330519Ssam #define VDOP_RDRAW 0x600 /* read unformatted disk sector */ 31430519Ssam #define VDOP_CMP 0xa0 /* compare */ 31530519Ssam #define VDOP_FTC 0xe0 /* full track compare */ 31630519Ssam #define VDOP_RHDE 0x180 /* read header, data & ecc */ 31730519Ssam #define VDOP_WD 0x00 /* write data */ 31830519Ssam #define VDOP_FTW 0x40 /* full track write */ 31930519Ssam #define VDOP_WTC 0x20 /* write then compare */ 32030519Ssam #define VDOP_FTWTC 0x60 /* full track write then compare */ 32130519Ssam #define VDOP_GAW 0x10 /* gather and write */ 32230519Ssam #define VDOP_WDE 0x100 /* write data & ecc */ 32330519Ssam #define VDOP_FSECT 0x900 /* format sector */ 32430519Ssam #define VDOP_GWC 0x30 /* gather write & compare */ 32530519Ssam #define VDOP_START 0x800 /* start drives */ 32630519Ssam #define VDOP_RELEASE 0xa00 /* stop drives */ 32730519Ssam #define VDOP_SEEK 0xb00 /* seek */ 32830519Ssam #define VDOP_INIT 0xc00 /* initialize controller */ 32930519Ssam #define VDOP_DIAG 0xd00 /* diagnose (self-test) controller */ 33030519Ssam #define VDOP_CONFIG 0xe00 /* reset & configure drive */ 33130519Ssam #define VDOP_STATUS 0xf00 /* get drive status */ 33230756Skarels #define VDOP_IDENT 0x700 /* identify controller */ 33338973Skarels #define VDOP_PROBE 0x500 /* probe drives and update status */ 33425677Ssam 33530519Ssam #define VDOP_ABORT 0x80000000 /* abort current command */ 33630519Ssam 33725677Ssam /* 33830519Ssam * DCB status definitions. 33925677Ssam */ 34030519Ssam #define DCBS_HCRC 0x00000001 /* header crc error */ 34130519Ssam #define DCBS_HCE 0x00000002 /* header compare error */ 34230519Ssam #define DCBS_WPT 0x00000004 /* drive write protected */ 34330519Ssam #define DCBS_CHE 0x00000008 /* controller hardware error */ 34430519Ssam #define DCBS_SKI 0x00000010 /* seek incomplete */ 34530519Ssam #define DCBS_UDE 0x00000020 /* uncorrectable data error */ 34630519Ssam #define DCBS_OCYL 0x00000040 /* off cylinder */ 34730519Ssam #define DCBS_NRDY 0x00000080 /* drive not ready */ 34830519Ssam #define DCBS_ATA 0x00000100 /* alternate track accessed */ 34930519Ssam #define DCBS_SKS 0x00000200 /* seek started */ 35030519Ssam #define DCBS_IVA 0x00000400 /* invalid disk address error */ 35130519Ssam #define DCBS_NEM 0x00000800 /* non-existant memory error */ 35230519Ssam #define DCBS_DPE 0x00001000 /* memory data parity error */ 35330519Ssam #define DCBS_DCE 0x00002000 /* data compare error */ 35430519Ssam #define DCBS_DDI 0x00004000 /* ddi ready */ 35530519Ssam #define DCBS_OAB 0x00008000 /* operation aborted */ 35630519Ssam #define DCBS_DSE 0x00010000 /* data strobe early */ 35730519Ssam #define DCBS_DSL 0x00020000 /* data strobe late */ 35830519Ssam #define DCBS_TOP 0x00040000 /* track offset plus */ 35930519Ssam #define DCBS_TOM 0x00080000 /* track offset minus */ 36030519Ssam #define DCBS_CCD 0x00100000 /* controller corrected data */ 36130519Ssam #define DCBS_HARD 0x00200000 /* hard error */ 36230519Ssam #define DCBS_SOFT 0x00400000 /* soft error (retry succesful) */ 36330519Ssam #define DCBS_ERR 0x00800000 /* composite error */ 36430519Ssam #define DCBS_IVC 0x01000000 /* invalid command error */ 36530519Ssam /* bits 24-27 unused */ 36630519Ssam #define DCBS_BSY 0x10000000 /* controller busy */ 36730519Ssam #define DCBS_ICC 0x60000000 /* interrupt cause code */ 36830519Ssam #define DCBS_INT 0x80000000 /* interrupt generated for this dcb */ 36925677Ssam 37030519Ssam #define VDERRBITS "\20\1HCRC\2HCE\3WPT\4CHE\5DSKI\6UDE\7OCYL\10NRDY\ 37130519Ssam \11ATA\12SKS\13IVA\14NEM\15DPE\16DCE\17DDI\20OAB\21DSE\22DSL\23TOP\24TOM\ 37230519Ssam \25CCD\26HARD\27SOFT\30ERR\31IVC\35ABORTED\36FAIL\37COMPLETE\40STARTED" 37325677Ssam 37430519Ssam /* drive related errors */ 37530519Ssam #define VDERR_DRIVE (DCBS_SKI|DCBS_OCYL|DCBS_NRDY|DCBS_IVA) 37630519Ssam /* controller related errors */ 37730519Ssam #define VDERR_CTLR (DCBS_CHE|DCBS_OAB|DCBS_IVC|DCBS_NEM) 37830519Ssam /* potentially recoverable errors */ 37930601Skarels #define VDERR_RETRY \ 38030519Ssam (VDERR_DRIVE|VDERR_CTLR|DCBS_DCE|DCBS_DPE|DCBS_HCRC|DCBS_HCE) 38130519Ssam /* uncorrected data errors */ 38230601Skarels #define VDERR_HARD (VDERR_RETRY|DCBS_WPT|DCBS_UDE) 38325677Ssam 38425677Ssam /* 38530519Ssam * DCB status codes. 38625677Ssam */ 38730519Ssam #define DCBS_ABORT 0x10000000 /* dcb aborted */ 38830519Ssam #define DCBS_FAIL 0x20000000 /* dcb unsuccesfully completed */ 38930519Ssam #define DCBS_DONE 0x40000000 /* dcb complete */ 39030519Ssam #define DCBS_START 0x80000000 /* dcb started */ 39125677Ssam 39230519Ssam /* 39330519Ssam * DCB interrupt control. 39430519Ssam */ 39530519Ssam #define DCBINT_NONE 0x0 /* don't interrupt */ 39630519Ssam #define DCBINT_ERR 0x2 /* interrupt on error */ 39730519Ssam #define DCBINT_SUC 0x1 /* interrupt on success */ 39830519Ssam #define DCBINT_DONE (DCBINT_ERR|DCBINT_SUC) 39930519Ssam #define DCBINT_PBA 0x4 /* proceed before acknowledge */ 40025677Ssam 40130519Ssam /* 40230519Ssam * Sector formats. 40330519Ssam */ 40430519Ssam typedef union { 40530519Ssam struct { 40630519Ssam dskadr hdr_addr; 40730519Ssam short smd_crc; 40830519Ssam } smd; 40930519Ssam struct { 41030519Ssam dskadr physical; 41130519Ssam dskadr logical; 41230519Ssam long smd_e_crc; 41330519Ssam } smd_e; 41430519Ssam } fmt_hdr; 41525677Ssam 41630519Ssam /* Sector Header bit assignments */ 41730519Ssam #define VDMF 0x8000 /* Manufacturer Fault 1=good sector */ 41830519Ssam #define VDUF 0x4000 /* User Fault 1=good sector */ 41930519Ssam #define VDALT 0x2000 /* Alternate Sector 1=alternate */ 42030519Ssam #define VDWPT 0x1000 /* Write Protect 1=Read Only Sector */ 42134396Skarels 42234396Skarels /* input register assignments for DIOCWFORMAT ioctl */ 42334396Skarels #define dk_op df_reg[0] /* opcode */ 42440736Skarels #define dk_althdr df_reg[1] /* alt. sect. dskadr, in an int! */ 42534396Skarels #define dk_fmtflags df_reg[2] /* header format flags */ 42634396Skarels 42734396Skarels /* output register assignments for DIOCWFORMAT ioctl */ 42834396Skarels #define dk_operrsta df_reg[0] /* dcb operrsta */ 42940736Skarels #define dk_ecodecnt df_reg[1] /* smd-e ecode and error word count */ 43040736Skarels #define dk_ecode(ecodecnt) ((u_long)(ecodecnt) >> 2) 43140736Skarels #define dk_errcnt(ecodecnt) (((ecodecnt) & 0xffff) << 1) 43240736Skarels #define dk_erraddr df_reg[2] /* error dskadr, in an int! */ 433