1*23999Ssam /* vddc.h 1.1 85/07/21 */ 2*23999Ssam 3*23999Ssam /* 4*23999Ssam ** Header file for the VDDC (Versabus Direct Disk Controller) Driver 5*23999Ssam */ 6*23999Ssam 7*23999Ssam #define NSECPTRK 32 /* #sectors/track - fixed by VDDC */ 8*23999Ssam #define SECTSIZ 512 /* sector size fixed by VDDC */ 9*23999Ssam #define L2SIZ 9 /* log2 of sector size */ 10*23999Ssam #define L2BSIZ 10 /* log2 of block size */ 11*23999Ssam #define NVDDRV 3 /* number of drive types supported */ 12*23999Ssam 13*23999Ssam /* 14*23999Ssam ** DCB Command Codes 15*23999Ssam */ 16*23999Ssam 17*23999Ssam #define RD 0x80 /* Read Data */ 18*23999Ssam #define FTR 0xc0 /* Full Track Read */ 19*23999Ssam #define RAS 0x90 /* Read and Scatter */ 20*23999Ssam #define C 0xa0 /* Compare */ 21*23999Ssam #define FTC 0xe0 /* Full Track Compare */ 22*23999Ssam #define RHDE 0x180 /* Read Header, Data & ECC (not used) */ 23*23999Ssam #define WD 0x00 /* Write Data */ 24*23999Ssam #define FTW 0x40 /* Full Track Write */ 25*23999Ssam #define WTC 0x20 /* Write Then Compare */ 26*23999Ssam #define FTWTC 0x60 /* Full Track Write Then Compare */ 27*23999Ssam #define GAW 0x10 /* Gather and Write */ 28*23999Ssam #define WDE 0x100 /* Write Data & ECC (not used) */ 29*23999Ssam #define FSECT 0x900 /* Format Sector */ 30*23999Ssam #define GWC 0x30 /* Gather Write & Compare */ 31*23999Ssam #define VDSTART 0x800 /* Start drives */ 32*23999Ssam #define VDRELEASE 0xa00 /* Stop drives */ 33*23999Ssam #define SEEK 0xb00 /* Seek */ 34*23999Ssam #define INIT 0xc00 /* Initialize VDDC */ 35*23999Ssam #define DIAG 0xd00 /* Diagnose (self-test) VDDC */ 36*23999Ssam #define RSTCFG 0xe00 /* Reset/Configure VDDC/DDI/Drive(s) */ 37*23999Ssam #define VDSTATUS 0xf00 /* VDDC Status */ 38*23999Ssam #define ABORT 0x80000000 /* To be written to VDDC Cntrl Register */ 39*23999Ssam 40*23999Ssam /* 41*23999Ssam * Error/Status Symbolic Constants 42*23999Ssam */ 43*23999Ssam #define HCRCERR 0x1 /* Header CRC Error */ 44*23999Ssam #define HCMPERR 0x2 /* Header Compare Error */ 45*23999Ssam #define WPTERR 0x4 /* Write Protect Error/Status */ 46*23999Ssam #define SZTIMEOUT 0x8 /* Seize timeout Error */ 47*23999Ssam #define DSEEKERR 0x10 /* Disk Seek Error */ 48*23999Ssam #define UCDATERR 0x20 /* Uncorrectable Data Error */ 49*23999Ssam #define NOTCYLERR 0x40 /* Not on Cylinder Error */ 50*23999Ssam #define DRVNRDY 0x80 /* Drive Not Ready Error/Status */ 51*23999Ssam #define ALTACC 0x100 /* Alternate (track) accessed Status */ 52*23999Ssam #define SEEKSTRT 0x200 /* Seek Started Status */ 53*23999Ssam #define INVDADR 0x400 /* Invalid Disk Address Error */ 54*23999Ssam #define DNEMEM 0x800 /* Non-Existant Memory Error */ 55*23999Ssam #define PARERR 0x1000 /* Memory Parity Error */ 56*23999Ssam #define DCOMPERR 0x2000 /* Data Compare Error */ 57*23999Ssam #define DDIRDY 0x4000 /* DDI Ready Error/Status */ 58*23999Ssam #define OPABRT 0x8000 /* Operator Abort (Host) Error/Status */ 59*23999Ssam #define DSERLY 0x10000 /* Data Strobe Early */ 60*23999Ssam #define DSLATE 0x20000 /* Data Strobe Late */ 61*23999Ssam #define TOPLUS 0x40000 /* Track Offset Plus */ 62*23999Ssam #define TOMNUS 0x80000 /* Track Offset Minus */ 63*23999Ssam #define CPDCRT 0x100000 /* Cntlr Performed Data Correction */ 64*23999Ssam #define HRDERR 0x200000 /* Hard Error */ 65*23999Ssam #define SFTERR 0x400000 /* Soft Error (retry succesful) */ 66*23999Ssam #define ANYERR 0x800000 /* Any Error */ 67*23999Ssam 68*23999Ssam #define ERRBITS "\20\30\27SOFT\26HARD\25CPDCRT\24TOMNUS\23TOPLUS\22DSLATE\ 69*23999Ssam \21DSERLY\20OPABRT\17DDIRDY\16DCOMPERR\15PARERR\14DNEMEM\13INVADR\12SEEKSTRT\ 70*23999Ssam \11ALTACC\10\DRVNRDY\7NOTCYLERR\6UCDATERR\5DSEEKERR\4SZTIMEOUT\3WPTERR\2HCMPERR\ 71*23999Ssam \1HCRCERR" 72*23999Ssam 73*23999Ssam /* 74*23999Ssam * DCB Status Symbolic Constants 75*23999Ssam */ 76*23999Ssam #define DCBABT 0x10000000 /* DCB Aborted */ 77*23999Ssam #define DCBUSC 0x20000000 /* DCB Unsuccesfully Completed */ 78*23999Ssam #define DCBCMP 0x40000000 /* DCB Complete */ 79*23999Ssam #define DCBSTR 0x80000000 /* DCB Started */ 80*23999Ssam 81*23999Ssam #define DCBBITS "\20\40DCBSTR\37DCBCMP\36DCBUSC\35DCBABT" 82*23999Ssam 83*23999Ssam /* 84*23999Ssam * MDCB Status Symbolic Constants 85*23999Ssam */ 86*23999Ssam #define CTLRBSY 0x10000000 /* Cntlr Busy */ 87*23999Ssam #define INTCCDE 0x60000000 /* Interrupt Cause Code */ 88*23999Ssam #define DCBINT 0x80000000 /* DCB Interrupt Flag */ 89*23999Ssam 90*23999Ssam #define MDCBBITS "\20\40DCBINT\37INTCCDE\36CTRLBSY" 91*23999Ssam 92*23999Ssam /* 93*23999Ssam ** Hard Error Types 94*23999Ssam */ 95*23999Ssam 96*23999Ssam #define HTYPES (HCRCERR|HCMPERR|WPTERR|SZTIMEOUT|DSEEKERR|UCDATERR|NOTCYLERR| \ 97*23999Ssam DRVNRDY|INVDADR|DNEMEM|PARERR|DCOMPERR) 98*23999Ssam 99*23999Ssam 100*23999Ssam /* 101*23999Ssam ** Errors 102*23999Ssam */ 103*23999Ssam 104*23999Ssam #define ERRS 0x3FFF 105*23999Ssam #define CANRETRY (SZTIMEOUT|DSEEKERR|NOTCYLERR|DCOMPERR|UCDATERR| \ 106*23999Ssam PARERR|DNEMEM|HCRCERR|HCMPERR) 107*23999Ssam /* 108*23999Ssam ** VDDC Interrupt Modes 109*23999Ssam */ 110*23999Ssam 111*23999Ssam #define NOINT 0x0 /* No Interrupt */ 112*23999Ssam #define INTERR 0x2 /* Interrupt on Error */ 113*23999Ssam #define INTSUC 0x1 /* Interrupt on Success */ 114*23999Ssam #define INTDUN 0x3 /* Interrupt on Error or Success */ 115*23999Ssam 116*23999Ssam #define CMD_MASK 0xFF0 /* Command code mask */ 117*23999Ssam /* When a tabular approach can be used */ 118*23999Ssam /* again change this back to 0x1F0 */ 119*23999Ssam 120*23999Ssam #define vdaddr ( (char *)(0xff0000+IOBASE) ) 121*23999Ssam 122*23999Ssam struct size 123*23999Ssam { 124*23999Ssam daddr_t nblocks; 125*23999Ssam int block0; 126*23999Ssam }; 127*23999Ssam 128*23999Ssam 129*23999Ssam 130*23999Ssam #define VDMF 0x8000 /* Manufacturer Fault 1=good sector */ 131*23999Ssam #define VDUF 0x4000 /* User Fault 1=good sector */ 132*23999Ssam #define VDALT 0x2000 /* Alternate Sector 1=alternate */ 133*23999Ssam #define VDWPT 0x1000 /* Write Protect 1=Read Only Sector */ 134*23999Ssam 135*23999Ssam /* 136*23999Ssam ** Addr of Memory-Mapped I/O port for VDDC Control Register 137*23999Ssam */ 138*23999Ssam 139*23999Ssam #define VDDC_ADR (char *)(0xFF2000 + IOBASE) /* device address register */ 140*23999Ssam /* this is the logical value */ 141*23999Ssam /* physically @ 0xFF2000 */ 142*23999Ssam /* location was extracted */ 143*23999Ssam /* from the VDDC diagnostic */ 144*23999Ssam /* package */ 145*23999Ssam 146*23999Ssam /* 147*23999Ssam ** Address of Memory-Mapped I/O Port for VDDC H/W Reset 148*23999Ssam */ 149*23999Ssam 150*23999Ssam #define VDDC_RESET(addr) *(addr + 4) = 0; /* reset controller */ 151*23999Ssam 152*23999Ssam /* 153*23999Ssam ** Start i/o to/from controller. 154*23999Ssam */ 155*23999Ssam 156*23999Ssam #define VDDC_ATTENTION(ctrl,mdcbadr) \ 157*23999Ssam { movow(((int)mdcbadr & 0xffff0000)>>16,ctrl) ;\ 158*23999Ssam movow( (int)mdcbadr & 0xffff, ctrl+2);\ 159*23999Ssam } 160