134406Skarels /* 2*35514Sbostic * Copyright (c) 1986 The Regents of the University of California. 3*35514Sbostic * All rights reserved. 4*35514Sbostic * 5*35514Sbostic * Redistribution and use in source and binary forms are permitted 6*35514Sbostic * provided that the above copyright notice and this paragraph are 7*35514Sbostic * duplicated in all such forms and that any documentation, 8*35514Sbostic * advertising materials, and other materials related to such 9*35514Sbostic * distribution and use acknowledge that the software was developed 10*35514Sbostic * by the University of California, Berkeley. The name of the 11*35514Sbostic * University may not be used to endorse or promote products derived 12*35514Sbostic * from this software without specific prior written permission. 13*35514Sbostic * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 14*35514Sbostic * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 15*35514Sbostic * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16*35514Sbostic * 17*35514Sbostic * @(#)ikreg.h 7.2 (Berkeley) 09/16/88 1834406Skarels */ 1930223Ssam 2030223Ssam /* 2130223Ssam * IKON DR-11W register definitions. 2230223Ssam */ 2330285Ssam struct ikdevice { 2430285Ssam u_short ik_csr; /* control status register */ 2530285Ssam u_short ik_data; /* data in/out register */ 2630285Ssam u_char ik_mod; /* address modifier */ 2730285Ssam u_char ik_vec; /* interrupt vector */ 2830285Ssam u_short ik_pulse; /* pulse commands (w) */ 2930285Ssam u_short ik_fill[5]; 3030285Ssam u_short ik_balo; /* low word of dma beginning address (w) */ 3130285Ssam u_short ik_wc; /* dma word count */ 3230285Ssam u_short ik_calo; /* low word of dma current address (r) */ 3330285Ssam u_short ik_fill1; 3430285Ssam u_short ik_bahi; /* high word of dma beginning address (w) */ 3530285Ssam u_short ik_fill2; 3630285Ssam u_short ik_cahi; /* high word of dma current address (r) */ 3730223Ssam }; 3830223Ssam 3930223Ssam /* 4030223Ssam * CSR control definitions (write-only). 4130223Ssam */ 4230285Ssam #define IKCSR_GO 0x0001 /* start dma */ 4330285Ssam #define IKCSR_FNC1 0x0002 /* function bit 1 */ 4430285Ssam #define IKCSR_FNC2 0x0004 /* function bit 2 */ 4530285Ssam #define IKCSR_FNC3 0x0008 /* function bit 3 */ 4630223Ssam /* bits 4-5 are unused */ 4730285Ssam #define IKCSR_IENA 0x0040 /* enable/disable interrupts */ 4830223Ssam /* bit 7 is unused */ 4930285Ssam #define IKCSR_CYCLE 0x0100 /* force dma to cycle */ 5030223Ssam /* bits 9-11 are unused */ 5130285Ssam #define IKCSR_MCLR 0x1000 /* master clear board */ 5230285Ssam #define IKCSR_RPERR 0x2000 /* reset parity error */ 5330285Ssam #define IKCSR_RATTF 0x4000 /* reset attention */ 5430285Ssam #define IKCSR_RDMAF 0x8000 /* reset dma completion */ 5530223Ssam 5630223Ssam /* 5730223Ssam * CSR status definitions (read-only). 5830223Ssam */ 5930285Ssam #define IKCSR_DEV 0x0001 /* device flag (0 = 10083, 1 = 10077) */ 6030223Ssam /* bits 1-3 reflect the function latch state */ 6130285Ssam #define IKCSR_TIMO 0x0010 /* bus timeout during dma */ 6230285Ssam #define IKCSR_BERR 0x0020 /* bus error during dma */ 6330223Ssam /* bit 6 reflects interrupt enable state */ 6430285Ssam #define IKCSR_READY 0x0080 /* device ready for next command */ 6530223Ssam /* bit 8 should be 0 */ 6630285Ssam #define IKCSR_STATC 0x0200 /* status bit C */ 6730285Ssam #define IKCSR_STATB 0x0400 /* status bit B */ 6830285Ssam #define IKCSR_STATA 0x0800 /* status bit A */ 6930285Ssam #define IKCSR_PERR 0x1000 /* parity error during pi/o or dma */ 7030285Ssam #define IKCSR_ATTN 0x2000 /* current state of attention bit */ 7130285Ssam #define IKCSR_ATTF 0x4000 /* latched attention t-f transition */ 7230285Ssam #define IKCSR_DMAF 0x8000 /* dma completed or terminated */ 7330223Ssam 7430223Ssam #define IKCSR_BITS \ 7530223Ssam "\020\1DEV\2FNC1\3FNC2\4FNC3\5TIMO\6BERR\7IENA\10READY\12STATC\13STATB\14STATA\ 7630223Ssam \15PERR\16ATTN\17ATTF\20DMAF" 7730223Ssam 7830223Ssam /* 7930223Ssam * Pulse command register definitions (write-only). 8030223Ssam */ 8130285Ssam #define IKPULSE_GO 0x0001 /* enable dma */ 8230285Ssam #define IKPULSE_FNC2 0x0004 /* pulse function bit 1 */ 8330285Ssam #define IKPULSE_RIENA 0x0020 /* reset IKCSR_IENA */ 8430285Ssam #define IKPULSE_SIENA 0x0040 /* set IKCSR_IENA */ 8530285Ssam #define IKPULSE_CYCL 0x0100 /* force dma to cycle */ 8630285Ssam #define IKPULSE_MCLR 0x1000 /* initialize interface */ 8730285Ssam #define IKPULSE_RPERR 0x2000 /* reset IKCSR_PERR */ 8830285Ssam #define IKPULSE_RATTF 0x4000 /* reset IKCSR_ATTF */ 8930285Ssam #define IKPULSE_RDMAF 0x8000 /* reset IKCSR_DMAF */ 90