1*30223Ssam /* ikreg.h 1.1 86/11/29 */ 2*30223Ssam 3*30223Ssam /* 4*30223Ssam * IKON DR-11W register definitions. 5*30223Ssam */ 6*30223Ssam struct ikdevice { 7*30223Ssam u_short ik_csr; /* control status register */ 8*30223Ssam u_short ik_data; /* data in/out register */ 9*30223Ssam u_char ik_mod; /* address modifier */ 10*30223Ssam u_char ik_vec; /* interrupt vector */ 11*30223Ssam u_short ik_pulse; /* pulse commands (w) */ 12*30223Ssam u_short ik_fill[5]; 13*30223Ssam u_short ik_balo; /* low word of dma beginning address (w) */ 14*30223Ssam u_short ik_wc; /* dma word count */ 15*30223Ssam u_short ik_calo; /* low word of dma current address (r) */ 16*30223Ssam u_short ik_fill1; 17*30223Ssam u_short ik_bahi; /* high word of dma beginning address (w) */ 18*30223Ssam u_short ik_fill2; 19*30223Ssam u_short ik_cahi; /* high word of dma current address (r) */ 20*30223Ssam }; 21*30223Ssam 22*30223Ssam /* 23*30223Ssam * CSR control definitions (write-only). 24*30223Ssam */ 25*30223Ssam #define IKCSR_GO 0x0001 /* start dma */ 26*30223Ssam #define IKCSR_FNC1 0x0002 /* function bit 1 */ 27*30223Ssam #define IKCSR_FNC2 0x0004 /* function bit 2 */ 28*30223Ssam #define IKCSR_FNC3 0x0008 /* function bit 3 */ 29*30223Ssam /* bits 4-5 are unused */ 30*30223Ssam #define IKCSR_IENA 0x0040 /* enable/disable interrupts */ 31*30223Ssam /* bit 7 is unused */ 32*30223Ssam #define IKCSR_CYCLE 0x0100 /* force dma to cycle */ 33*30223Ssam /* bits 9-11 are unused */ 34*30223Ssam #define IKCSR_MCLR 0x1000 /* master clear board */ 35*30223Ssam #define IKCSR_RPERR 0x2000 /* reset parity error */ 36*30223Ssam #define IKCSR_RATTF 0x4000 /* reset attention */ 37*30223Ssam #define IKCSR_RDMAF 0x8000 /* reset dma completion */ 38*30223Ssam 39*30223Ssam /* 40*30223Ssam * CSR status definitions (read-only). 41*30223Ssam */ 42*30223Ssam #define IKCSR_DEV 0x0001 /* device flag (0 = 10083, 1 = 10077) */ 43*30223Ssam /* bits 1-3 reflect the function latch state */ 44*30223Ssam #define IKCSR_TIMO 0x0010 /* bus timeout during dma */ 45*30223Ssam #define IKCSR_BERR 0x0020 /* bus error during dma */ 46*30223Ssam /* bit 6 reflects interrupt enable state */ 47*30223Ssam #define IKCSR_READY 0x0080 /* device ready for next command */ 48*30223Ssam /* bit 8 should be 0 */ 49*30223Ssam #define IKCSR_STATC 0x0200 /* status bit C */ 50*30223Ssam #define IKCSR_STATB 0x0400 /* status bit B */ 51*30223Ssam #define IKCSR_STATA 0x0800 /* status bit A */ 52*30223Ssam #define IKCSR_PERR 0x1000 /* parity error during pi/o or dma */ 53*30223Ssam #define IKCSR_ATTN 0x2000 /* current state of attention bit */ 54*30223Ssam #define IKCSR_ATTF 0x4000 /* latched attention t-f transition */ 55*30223Ssam #define IKCSR_DMAF 0x8000 /* dma completed or terminated */ 56*30223Ssam 57*30223Ssam #define IKCSR_BITS \ 58*30223Ssam "\020\1DEV\2FNC1\3FNC2\4FNC3\5TIMO\6BERR\7IENA\10READY\12STATC\13STATB\14STATA\ 59*30223Ssam \15PERR\16ATTN\17ATTF\20DMAF" 60*30223Ssam 61*30223Ssam #define IKMOD_STD 0x1 /* std memory map address modifier */ 62*30223Ssam #define IKVEC_BASE 0x9c /* base of reserved interrupt vectors */ 63*30223Ssam 64*30223Ssam /* 65*30223Ssam * Pulse command register definitions (write-only). 66*30223Ssam */ 67*30223Ssam #define IKPULSE_GO 0x0001 /* enable dma */ 68*30223Ssam #define IKPULSE_FNC2 0x0004 /* pulse function bit 1 */ 69*30223Ssam #define IKPULSE_RIENA 0x0020 /* reset IKCSR_IENA */ 70*30223Ssam #define IKPULSE_SIENA 0x0040 /* set IKCSR_IENA */ 71*30223Ssam #define IKPULSE_CYCL 0x0100 /* force dma to cycle */ 72*30223Ssam #define IKPULSE_MCLR 0x1000 /* initialize interface */ 73*30223Ssam #define IKPULSE_RPERR 0x2000 /* reset IKCSR_PERR */ 74*30223Ssam #define IKPULSE_RATTF 0x4000 /* reset IKCSR_ATTF */ 75*30223Ssam #define IKPULSE_RDMAF 0x8000 /* reset IKCSR_DMAF */ 76