134406Skarels /* 235514Sbostic * Copyright (c) 1986 The Regents of the University of California. 335514Sbostic * All rights reserved. 435514Sbostic * 5*44534Sbostic * %sccs.include.redist.c% 635514Sbostic * 7*44534Sbostic * @(#)ikreg.h 7.3 (Berkeley) 06/28/90 834406Skarels */ 930223Ssam 1030223Ssam /* 1130223Ssam * IKON DR-11W register definitions. 1230223Ssam */ 1330285Ssam struct ikdevice { 1430285Ssam u_short ik_csr; /* control status register */ 1530285Ssam u_short ik_data; /* data in/out register */ 1630285Ssam u_char ik_mod; /* address modifier */ 1730285Ssam u_char ik_vec; /* interrupt vector */ 1830285Ssam u_short ik_pulse; /* pulse commands (w) */ 1930285Ssam u_short ik_fill[5]; 2030285Ssam u_short ik_balo; /* low word of dma beginning address (w) */ 2130285Ssam u_short ik_wc; /* dma word count */ 2230285Ssam u_short ik_calo; /* low word of dma current address (r) */ 2330285Ssam u_short ik_fill1; 2430285Ssam u_short ik_bahi; /* high word of dma beginning address (w) */ 2530285Ssam u_short ik_fill2; 2630285Ssam u_short ik_cahi; /* high word of dma current address (r) */ 2730223Ssam }; 2830223Ssam 2930223Ssam /* 3030223Ssam * CSR control definitions (write-only). 3130223Ssam */ 3230285Ssam #define IKCSR_GO 0x0001 /* start dma */ 3330285Ssam #define IKCSR_FNC1 0x0002 /* function bit 1 */ 3430285Ssam #define IKCSR_FNC2 0x0004 /* function bit 2 */ 3530285Ssam #define IKCSR_FNC3 0x0008 /* function bit 3 */ 3630223Ssam /* bits 4-5 are unused */ 3730285Ssam #define IKCSR_IENA 0x0040 /* enable/disable interrupts */ 3830223Ssam /* bit 7 is unused */ 3930285Ssam #define IKCSR_CYCLE 0x0100 /* force dma to cycle */ 4030223Ssam /* bits 9-11 are unused */ 4130285Ssam #define IKCSR_MCLR 0x1000 /* master clear board */ 4230285Ssam #define IKCSR_RPERR 0x2000 /* reset parity error */ 4330285Ssam #define IKCSR_RATTF 0x4000 /* reset attention */ 4430285Ssam #define IKCSR_RDMAF 0x8000 /* reset dma completion */ 4530223Ssam 4630223Ssam /* 4730223Ssam * CSR status definitions (read-only). 4830223Ssam */ 4930285Ssam #define IKCSR_DEV 0x0001 /* device flag (0 = 10083, 1 = 10077) */ 5030223Ssam /* bits 1-3 reflect the function latch state */ 5130285Ssam #define IKCSR_TIMO 0x0010 /* bus timeout during dma */ 5230285Ssam #define IKCSR_BERR 0x0020 /* bus error during dma */ 5330223Ssam /* bit 6 reflects interrupt enable state */ 5430285Ssam #define IKCSR_READY 0x0080 /* device ready for next command */ 5530223Ssam /* bit 8 should be 0 */ 5630285Ssam #define IKCSR_STATC 0x0200 /* status bit C */ 5730285Ssam #define IKCSR_STATB 0x0400 /* status bit B */ 5830285Ssam #define IKCSR_STATA 0x0800 /* status bit A */ 5930285Ssam #define IKCSR_PERR 0x1000 /* parity error during pi/o or dma */ 6030285Ssam #define IKCSR_ATTN 0x2000 /* current state of attention bit */ 6130285Ssam #define IKCSR_ATTF 0x4000 /* latched attention t-f transition */ 6230285Ssam #define IKCSR_DMAF 0x8000 /* dma completed or terminated */ 6330223Ssam 6430223Ssam #define IKCSR_BITS \ 6530223Ssam "\020\1DEV\2FNC1\3FNC2\4FNC3\5TIMO\6BERR\7IENA\10READY\12STATC\13STATB\14STATA\ 6630223Ssam \15PERR\16ATTN\17ATTF\20DMAF" 6730223Ssam 6830223Ssam /* 6930223Ssam * Pulse command register definitions (write-only). 7030223Ssam */ 7130285Ssam #define IKPULSE_GO 0x0001 /* enable dma */ 7230285Ssam #define IKPULSE_FNC2 0x0004 /* pulse function bit 1 */ 7330285Ssam #define IKPULSE_RIENA 0x0020 /* reset IKCSR_IENA */ 7430285Ssam #define IKPULSE_SIENA 0x0040 /* set IKCSR_IENA */ 7530285Ssam #define IKPULSE_CYCL 0x0100 /* force dma to cycle */ 7630285Ssam #define IKPULSE_MCLR 0x1000 /* initialize interface */ 7730285Ssam #define IKPULSE_RPERR 0x2000 /* reset IKCSR_PERR */ 7830285Ssam #define IKPULSE_RATTF 0x4000 /* reset IKCSR_ATTF */ 7930285Ssam #define IKPULSE_RDMAF 0x8000 /* reset IKCSR_DMAF */ 80