1 /* 2 * Copyright (c) 1988 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Computer Consoles Inc. 7 * 8 * Redistribution and use in source and binary forms are permitted 9 * provided that the above copyright notice and this paragraph are 10 * duplicated in all such forms and that any documentation, 11 * advertising materials, and other materials related to such 12 * distribution and use acknowledge that the software was developed 13 * by the University of California, Berkeley. The name of the 14 * University may not be used to endorse or promote products derived 15 * from this software without specific prior written permission. 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 18 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 19 * 20 * @(#)drreg.h 7.2 (Berkeley) 09/16/88 21 */ 22 23 /* 24 ------------------------------------------ 25 Must include <h/types.h> and <h/buf.h> 26 ------------------------------------------ 27 */ 28 29 #define DRINTV 0x9c /* Has to match with ml/scb.s */ 30 #define DRADDMOD 0x01 /* Addr modifier used to access TAHOE memory */ 31 #define DR_ZERO 0 32 #define DRPRI (PZERO+1) 33 34 #define DR_TICK 600 /* Default # of clock ticks between call 35 to local timer watchdog routine */ 36 #define DR_TOCK 2 /* default # of calls to local watch dog 37 before an IO or wait is determined to 38 have timeout */ 39 40 41 struct rsdevice { 42 ushort dr_cstat; /* Control & status registers */ 43 ushort dr_data; /* Input/Ouptut data registers */ 44 char dr_addmod; /* Address modifier for DMA */ 45 char dr_intvect; /* Interrupt vector */ 46 ushort dr_pulse; /* Pulse command register */ 47 ushort dr_xx08; /* Not used */ 48 ushort dr_xx0A; /* Not used */ 49 ushort dr_xx0C; /* Not used */ 50 ushort dr_xx0E; /* Not used */ 51 ushort dr_xx10; /* Not used */ 52 ushort dr_walo; /* Low DMA address register --when written-- */ 53 ushort dr_range; /* DMA range counter */ 54 ushort dr_ralo; /* Low DMA address register --when read-- */ 55 ushort dr_xx18; /* Not used */ 56 ushort dr_wahi; /* High DMA address register --when written-- */ 57 ushort dr_xx1C; /* Not used */ 58 ushort dr_rahi; /* High DMA address register --when read-- */ 59 }; 60 61 62 struct dr_aux { 63 struct rsdevice *dr_addr; /* Physical addr of currently active DR11 */ 64 struct buf *dr_actf; /* Pointers to DR11's active buffers list */ 65 unsigned int dr_flags; /* State: Hold open, active,... */ 66 ushort dr_cmd; /* Hold cmd placed here by ioctl 67 for later execution by rsstrategy() */ 68 ushort dr_op; /* Current operation: DR_READ/DR_WRITE */ 69 long dr_bycnt; /* Total byte cnt of current operation */ 70 /* decremented by completion interrupt */ 71 caddr_t dr_oba; /* original xfer addr, count */ 72 long dr_obc; 73 unsigned long 74 rtimoticks, /* No of ticks before timing out on no stall 75 read */ 76 wtimoticks, /* No of ticks before timing out on no stall 77 write */ 78 currenttimo; /* the number of current timeout call to 79 omrwtimo() */ 80 ushort dr_istat; /* Latest interrupt status */ 81 struct buf dr_buf; 82 83 /*ushort dr_time; /* # of ticks until timeout */ 84 /*ushort dr_tock; /* # of ticks accumulated */ 85 /*ushort dr_cseq; /* Current sequence number */ 86 /*ushort dr_lseq; /* Last sequence number */ 87 }; 88 89 /* Command used by drioctl() 90 */ 91 struct dr11io { 92 ushort arg[8]; 93 }; 94 95 #define RSADDR(unit) ((struct rsdevice *)drinfo[unit]->ui_addr) 96 97 /* Control register bits */ 98 #define RDMA 0x8000 /* reset DMA end-of-range flag */ 99 #define RATN 0x4000 /* reset attention flag */ 100 #define RPER 0x2000 /* reset device parity error flag */ 101 #define MCLR 0x1000 /* master clear board and INT device */ 102 #define CYCL 0x0100 /* forces DMA cycle if DMA enabled */ 103 #define IENB 0x0040 /* enables interrupt */ 104 #define FCN3 0x0008 /* func. bit 3 to device (FNCT3 H) */ 105 #define FCN2 0x0004 /* func. bit 2 to device (FNCT2 H) */ 106 /* also asserts ACLO FCNT2 H to device */ 107 #define FCN1 0x0002 /* func. bit 1 to device (FNCT1 H) */ 108 #define GO 0x0001 /* enable DMA and pulse GO to device */ 109 110 /* Status register bits */ 111 #define DMAF 0x8000 /* indicates DMA end-of-range */ 112 #define ATTF 0x4000 /* indicates attention false-to-true */ 113 #define ATTN 0x2000 /* current state of ATTENTION H input */ 114 #define PERR 0x1000 /* Set by external parity error */ 115 #define STTA 0x0800 /* STATUS A H input state */ 116 #define STTB 0x0400 /* STATUS B H input state */ 117 #define STTC 0x0200 /* STATUS C H input state */ 118 #define REDY 0x0080 /* board ready for cmd (dma not on) */ 119 #define IENF 0x0040 /* Interrupt enabled if on */ 120 #define BERR 0x0020 /* Set if bus error during DMA */ 121 #define TERR 0x0010 /* Set if bus timeout during DMA */ 122 #define FC3S 0x0008 /* State of FCN3 latch */ 123 #define FC2S 0x0004 /* State of FCN2 latch */ 124 #define FC1S 0x0002 /* State of FCN1 latch */ 125 #define DLFG 0x0001 /* 0 -> IKON-10083 *** 1 -> IKON-10077 */ 126 127 /* Pulse command register bits */ 128 #define SMSK 0x0040 /* pulse interrupt mask on: Set IENB */ 129 #define RMSK 0x0020 /* pulse interrupt mask off: Reset IENB */ 130 131 132 /* 133 * DR11 driver's internal flags -- to be stored in dr_flags 134 */ 135 #define DR_FMSK 0x0000E /* function bits mask */ 136 #define DR_OPEN 0x00001 /* This dr11 has been opened */ 137 #define DR_PRES 0x00002 /* This dr11 is present */ 138 #define DR_ACTV 0x00004 /* waiting for end-of-range */ 139 #define DR_ATWT 0x00008 /* waiting for attention interrupt */ 140 #define DR_ATRX 0x00010 /* attn received-resets when read */ 141 #define DR_TMDM 0x00020 /* timeout waiting for end-of-range */ 142 #define DR_TMAT 0x00040 /* timeout waiting for attention */ 143 #define DR_DMAX 0x00080 /* end-of-range interrupt received */ 144 #define DR_PCYL 0x00100 /* set cycle with next go */ 145 #define DR_DFCN 0x00200 /* donot update function bits until next go */ 146 #define DR_DACL 0x00400 /* defer alco pulse until go */ 147 #define DR_LOOPTST 0x02000 /* This dr11 is in loopback test mode */ 148 #define DR_LNKMODE 0x04000 /* This dr11 is in link mode */ 149 #define DR_NORSTALL 0x10000 /* Device is set to no stall mode for reads. */ 150 #define DR_NOWSTALL 0x20000 /* Device is set to no stall mode for writes. */ 151 #define DR_TIMEDOUT 0x40000 /* The device timed out on a stall mode R/W */ 152 153 /* 154 * DR11 driver's internal flags -- to be stored in dr_op 155 */ 156 #define DR_READ FCN1 157 #define DR_WRITE 0 158 159 /* 160 * Ioctl commands 161 */ 162 #define DRWAIT _IOWR('d',1,long) 163 #define DRPIOW _IOWR('d',2,long) 164 #define DRPACL _IOWR('d',3,long) 165 #define DRDACL _IOWR('d',4,long) 166 #define DRPCYL _IOWR('d',5,long) 167 #define DRDFCN _IOWR('d',6,long) 168 #define DRRPER _IOWR('d',7,long) 169 #define DRRATN _IOWR('d',8,long) 170 #define DRRDMA _IOWR('d',9,long) 171 #define DRSFCN _IOWR('d',10,long) 172 173 #define DRSETRSTALL _IOWR('d',13,long) 174 #define DRSETNORSTALL _IOWR('d',14,long) 175 #define DRGETRSTALL _IOWR('d',15,long) 176 #define DRSETRTIMEOUT _IOWR('d',16,long) 177 #define DRGETRTIMEOUT _IOWR('d',17,long) 178 #define DRSETWSTALL _IOWR('d',18,long) 179 #define DRSETNOWSTALL _IOWR('d',19,long) 180 #define DRGETWSTALL _IOWR('d',20,long) 181 #define DRSETWTIMEOUT _IOWR('d',21,long) 182 #define DRGETWTIMEOUT _IOWR('d',22,long) 183 #define DRWRITEREADY _IOWR('d',23,long) 184 #define DRREADREADY _IOWR('d',24,long) 185 #define DRBUSY _IOWR('d',25,long) 186 #define DRRESET _IOWR('d',26,long) 187 188 /* The block size for buffering and DMA transfers. */ 189 /* OM_BLOCKSIZE must be even and <= 32768. Multiples of 512 are prefered. */ 190 #define OM_BLOCKSIZE 32768 191 192 193 /* --- Define ioctl call used by dr11 utility device -- */ 194 195 #define DR11STAT _IOWR('d',30,struct dr11io) /* Get status dr11, unit 196 number is dr11io.arg[0] */ 197 #define DR11LOOP _IOR('d',31,struct dr11io) /* Perform loopback test */ 198 199 /* ---------------------------------------------------- */ 200 201