1*56816Sralph /*- 2*56816Sralph * Copyright (c) 1992 The Regents of the University of California. 3*56816Sralph * All rights reserved. 4*56816Sralph * 5*56816Sralph * This code is derived from software contributed to Berkeley by 6*56816Sralph * Ralph Campbell and Rick Macklem. 7*56816Sralph * 8*56816Sralph * %sccs.include.redist.c% 9*56816Sralph * 10*56816Sralph * @(#)mfbreg.h 7.1 (Berkeley) 11/15/92 11*56816Sralph */ 12*56816Sralph 13*56816Sralph /* 14*56816Sralph * Mach Operating System 15*56816Sralph * Copyright (c) 1991,1990,1989 Carnegie Mellon University 16*56816Sralph * All Rights Reserved. 17*56816Sralph * 18*56816Sralph * Permission to use, copy, modify and distribute this software and its 19*56816Sralph * documentation is hereby granted, provided that both the copyright 20*56816Sralph * notice and this permission notice appear in all copies of the 21*56816Sralph * software, derivative works or modified versions, and any portions 22*56816Sralph * thereof, and that both notices appear in supporting documentation. 23*56816Sralph * 24*56816Sralph * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS 25*56816Sralph * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 26*56816Sralph * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 27*56816Sralph * 28*56816Sralph * Carnegie Mellon requests users of this software to return to 29*56816Sralph * 30*56816Sralph * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 31*56816Sralph * School of Computer Science 32*56816Sralph * Carnegie Mellon University 33*56816Sralph * Pittsburgh PA 15213-3890 34*56816Sralph * 35*56816Sralph * any improvements or extensions that they make and grant Carnegie the 36*56816Sralph * rights to redistribute these changes. 37*56816Sralph */ 38*56816Sralph /* 39*56816Sralph * This configuration uses two twin Bt431s and a single Bt455 colour map. 40*56816Sralph * (Yep, that's a colour map on a single bitplane mono display) 41*56816Sralph */ 42*56816Sralph #define SET_VALUE(x) (((x)<<8)|((x)&0xff)) 43*56816Sralph #define GET_VALUE(x) ((x)&0xff) 44*56816Sralph 45*56816Sralph typedef struct { 46*56816Sralph volatile u_short addr_lo; 47*56816Sralph short pad0; 48*56816Sralph volatile u_short addr_hi; 49*56816Sralph short pad1; 50*56816Sralph volatile u_short addr_cmap; 51*56816Sralph short pad2; 52*56816Sralph volatile u_short addr_reg; 53*56816Sralph short pad3; 54*56816Sralph } bt431_regmap_t; 55*56816Sralph 56*56816Sralph /* 57*56816Sralph * Generic register access 58*56816Sralph */ 59*56816Sralph /* when using autoincrement */ 60*56816Sralph #define BT431_WRITE_REG_AUTOI(regs, val) { \ 61*56816Sralph (regs)->addr_reg = SET_VALUE(val); \ 62*56816Sralph MachEmptyWriteBuffer(); \ 63*56816Sralph } 64*56816Sralph 65*56816Sralph #define BT431_READ_REG_AUTOI(regs) \ 66*56816Sralph GET_VALUE(((regs)->addr_reg)) 67*56816Sralph 68*56816Sralph #define BT431_WRITE_CMAP_AUTOI(regs, val) { \ 69*56816Sralph (regs)->addr_cmap = (val); \ 70*56816Sralph MachEmptyWriteBuffer(); \ 71*56816Sralph } 72*56816Sralph 73*56816Sralph #define BT431_READ_CMAP_AUTOI(regs) \ 74*56816Sralph ((regs)->addr_cmap) 75*56816Sralph 76*56816Sralph typedef struct { 77*56816Sralph volatile u_char addr_cmap; 78*56816Sralph char pad0[3]; 79*56816Sralph volatile u_char addr_cmap_data; 80*56816Sralph char pad1[3]; 81*56816Sralph volatile u_char addr_clr; 82*56816Sralph char pad2[3]; 83*56816Sralph volatile u_char addr_ovly; 84*56816Sralph char pad3[3]; 85*56816Sralph } bt455_regmap_t; 86*56816Sralph 87*56816Sralph 88*56816Sralph /* 89*56816Sralph * Generic register access 90*56816Sralph */ 91*56816Sralph #define BT455_SELECT_ENTRY(regs, regno) { \ 92*56816Sralph (regs)->addr_cmap = (regno)&0x0f; \ 93*56816Sralph MachEmptyWriteBuffer(); \ 94*56816Sralph } 95*56816Sralph 96*56816Sralph /* 97*56816Sralph * Additional registers addressed indirectly 98*56816Sralph */ 99*56816Sralph #define BT431_REG_CMD 0x0000 100*56816Sralph #define BT431_REG_CXLO 0x0001 101*56816Sralph #define BT431_REG_CXHI 0x0002 102*56816Sralph #define BT431_REG_CYLO 0x0003 103*56816Sralph #define BT431_REG_CYHI 0x0004 104*56816Sralph #define BT431_REG_WXLO 0x0005 105*56816Sralph #define BT431_REG_WXHI 0x0006 106*56816Sralph #define BT431_REG_WYLO 0x0007 107*56816Sralph #define BT431_REG_WYHI 0x0008 108*56816Sralph #define BT431_REG_WWLO 0x0009 109*56816Sralph #define BT431_REG_WWHI 0x000a 110*56816Sralph #define BT431_REG_WHLO 0x000b 111*56816Sralph #define BT431_REG_WHHI 0x000c 112*56816Sralph 113*56816Sralph #define BT431_REG_CRAM_BASE 0x0000 114*56816Sralph #define BT431_REG_CRAM_END 0x01ff 115*56816Sralph 116*56816Sralph /* 117*56816Sralph * Command register 118*56816Sralph */ 119*56816Sralph 120*56816Sralph #define BT431_CMD_CURS_ENABLE 0x40 121*56816Sralph #define BT431_CMD_XHAIR_ENABLE 0x20 122*56816Sralph #define BT431_CMD_OR_CURSORS 0x10 123*56816Sralph #define BT431_CMD_AND_CURSORS 0x00 124*56816Sralph #define BT431_CMD_1_1_MUX 0x00 125*56816Sralph #define BT431_CMD_4_1_MUX 0x04 126*56816Sralph #define BT431_CMD_5_1_MUX 0x08 127*56816Sralph #define BT431_CMD_xxx_MUX 0x0c 128*56816Sralph #define BT431_CMD_THICK_1 0x00 129*56816Sralph #define BT431_CMD_THICK_3 0x01 130*56816Sralph #define BT431_CMD_THICK_5 0x02 131*56816Sralph #define BT431_CMD_THICK_7 0x03 132